From patchwork Mon Mar 13 13:04:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95213 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1162238qgd; Mon, 13 Mar 2017 06:05:41 -0700 (PDT) X-Received: by 10.28.169.199 with SMTP id s190mr10058239wme.2.1489410340978; Mon, 13 Mar 2017 06:05:40 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id m4si565948wrm.249.2017.03.13.06.05.40; Mon, 13 Mar 2017 06:05:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 1E499C21C6E; Mon, 13 Mar 2017 13:05:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 580BCC21C32; Mon, 13 Mar 2017 13:05:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BBE52C21C32; Mon, 13 Mar 2017 13:05:32 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 056D5C21C2D for ; Mon, 13 Mar 2017 13:05:31 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4d6b030077; Mon, 13 Mar 2017 08:04:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410279; bh=gK83Y/5a8bsamnj3+EETNZb6rZ8A/bhlNAZOkAItVHQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yq9XCbGptZNHR5oxcsAhrBQsYwVbMOxAOOcrZoLPrbS/rgDEN07my9Z7bH6XymlPM Ln1oR7TjaKw4GSWNwQAF5YJCl6wTgQy99m4PUnlO8ILjbkTKcfr0cojjYuBp7pPpA9 12kp8+GMDdrTa1nNaqB2hv1H0sLs9hwz8IRWmI7M= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4dFq030991; Mon, 13 Mar 2017 08:04:39 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:38 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjK003968; Mon, 13 Mar 2017 08:04:37 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:24 +0200 Message-ID: <1489410273-10159-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 01/10] ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index from the GPIO bank number and bank's GPIO offset number. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/gpio.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h index 9dd03c9..48e8ca5 100644 --- a/arch/arm/include/asm/arch-omap5/gpio.h +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -34,4 +34,8 @@ #define OMAP54XX_GPIO7_BASE 0x48051000 #define OMAP54XX_GPIO8_BASE 0x48053000 + +/* Get the GPIO index from the given bank number and bank gpio */ +#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio)) + #endif /* _GPIO_OMAP5_H */ From patchwork Mon Mar 13 13:04:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95214 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1162883qgd; Mon, 13 Mar 2017 06:06:56 -0700 (PDT) X-Received: by 10.223.177.151 with SMTP id q23mr26933116wra.65.1489410416339; Mon, 13 Mar 2017 06:06:56 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id k55si598413wrk.55.2017.03.13.06.06.56; Mon, 13 Mar 2017 06:06:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id DCBC0C21C4F; Mon, 13 Mar 2017 13:05:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1631BC21C57; Mon, 13 Mar 2017 13:05:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 697B1C21C63; Mon, 13 Mar 2017 13:05:44 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 3A5C4C21C61 for ; Mon, 13 Mar 2017 13:05:41 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4f3O030086; Mon, 13 Mar 2017 08:04:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410281; bh=eksugmci4WMYO5fsWkU7vHi6yRDl7Qp1PgAacmQbrXA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZtfG0oYORI56AESMde2mNPk9oPi4bCKxrm+4gVyrcHIau60om1X9Lx+ksqJGcut5x 2jJhqYC7pmakk9awt0568+VKQJ3Oqkj2j8qXCqP63PYdSUv/JybuFoujLzBz9bH3TA VR9iO+3mB4dCOwyos/yHayzaB2LNMdQ64hJGiLWU= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4fXa031015; Mon, 13 Mar 2017 08:04:41 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:40 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjL003968; Mon, 13 Mar 2017 08:04:39 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:25 +0200 Message-ID: <1489410273-10159-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 02/10] ti: common: board_detect: Rename EEPROM scratch start macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Lokesh Vutla Non OMAP platforms i.e. Keystone will also need to use the board EEPROM helpers so let's make the macro platform independent. Signed-off-by: Roger Quadros Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 8 +++++--- board/ti/common/board_detect.h | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2034a5e..c1a70b1 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -767,9 +767,11 @@ static inline u8 is_dra72x(void) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) -#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) -#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) -#define OMAP_SRAM_SCRATCH_SPACE_END (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END) +#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#endif +#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* Boot parameters */ #define DEVICE_DATA_OFFSET 0x18 diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index 343fcb4..52b0075 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -98,7 +98,7 @@ struct ti_common_eeprom { }; #define TI_EEPROM_DATA ((struct ti_common_eeprom *)\ - OMAP_SRAM_SCRATCH_BOARD_EEPROM_START) + TI_SRAM_SCRATCH_BOARD_EEPROM_START) /** * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs From patchwork Mon Mar 13 13:04:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95221 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1165258qgd; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) X-Received: by 10.28.45.212 with SMTP id t203mr9571320wmt.37.1489410707085; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z64si585574wrc.261.2017.03.13.06.11.46; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 99967C21C8D; Mon, 13 Mar 2017 13:08:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F1B9EC21C61; Mon, 13 Mar 2017 13:08:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 38919C21C51; Mon, 13 Mar 2017 13:06:28 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 179DEC21C6A for ; Mon, 13 Mar 2017 13:06:23 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4mrB006694; Mon, 13 Mar 2017 08:04:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410288; bh=yVOmFqGmgaNT0PMEWDpiU4IJwah/imJ+Gs3l0ezTM0s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mPyq067L1o3QGCv50LuNmGhIEsfkmJcdmT5ljADamkKy2sU5l6HZwh0ttRcvW7aKX 9p+fUIlELtPt7WzHMphqr1dkxpfwercWbWZexLa4n/uZ3XtmlGZYF+RIA0FVjm7pae gQDqkO9MqapJgQaAliPKrpWRKCTvtzUrSSldhxJE= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4hdu031049; Mon, 13 Mar 2017 08:04:43 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:42 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjM003968; Mon, 13 Mar 2017 08:04:41 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:26 +0200 Message-ID: <1489410273-10159-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Franklin S Cooper Jr Subject: [U-Boot] [u-boot PATCH v4 03/10] ti_armv7_keystone2: Define scratch space in SRAM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Franklin S Cooper Jr Scratch space can be used for features such as board detection. Define an area within SRAM that can be used for this purpose. [rogerq@ti.com] Rename EEPROM macro Signed-off-by: Franklin S Cooper Jr Signed-off-by: Roger Quadros --- include/configs/ti_armv7_keystone2.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 5d4ef58..f76e0a5 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -55,6 +55,13 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +/* SRAM scratch space entries */ +#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) + /* UART Configuration */ #define CONFIG_SYS_NS16550_MEM32 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) From patchwork Mon Mar 13 13:04:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95215 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1163467qgd; Mon, 13 Mar 2017 06:08:06 -0700 (PDT) X-Received: by 10.223.135.153 with SMTP id b25mr28070618wrb.169.1489410486320; Mon, 13 Mar 2017 06:08:06 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 8si10815024wmc.94.2017.03.13.06.08.06; Mon, 13 Mar 2017 06:08:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id DCF64C21C78; Mon, 13 Mar 2017 13:06:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0FCD3C21C49; Mon, 13 Mar 2017 13:06:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C01D5C21C49; Mon, 13 Mar 2017 13:05:44 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id E76ECC21C6D for ; Mon, 13 Mar 2017 13:05:39 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4jci019937; Mon, 13 Mar 2017 08:04:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410285; bh=faaf901W5sXRfcF6lWoOOU85l/gvBMYObQZ17eL5xB4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HrHNHYSJOuxNMn+E6uL9Xypo4hZNQznJ66k0gSQ5ft4Dy6cWxE3v4HEcJKP0dJ+OP +f2j1jDh4dJwAxMaeENq5pbes4JJrsRNfis1Shdn2NTYe7w+SDvMoq3YjIlpUVvrx6 v6cGvd4vskJb+9rlxgLjXIgsN6+eWMoh63I3YhnA= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4jMA031059; Mon, 13 Mar 2017 08:04:45 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:44 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjN003968; Mon, 13 Mar 2017 08:04:43 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:27 +0200 Message-ID: <1489410273-10159-5-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 04/10] ti: common: board_detect: commodify ethaddr environment setting code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Keystone and OMAP platforms will need this to set ethernet MAC addresses from board EEPROM. Signed-off-by: Roger Quadros Reviewed-by: Lokesh Vutla Reviewed-by: Tom Rini --- board/ti/common/board_detect.c | 57 ++++++++++++++++++++++++++++++++++++++++++ board/ti/common/board_detect.h | 12 +++++++++ 2 files changed, 69 insertions(+) diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index a5dba94..23388d0 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -314,3 +314,60 @@ void __maybe_unused set_board_info_env(char *name) else setenv("board_serial", unknown); } + +static u64 mac_to_u64(u8 mac[6]) +{ + int i; + u64 addr = 0; + + for (i = 0; i < 6; i++) { + addr <<= 8; + addr |= mac[i]; + } + + return addr; +} + +static void u64_to_mac(u64 addr, u8 mac[6]) +{ + mac[5] = addr; + mac[4] = addr >> 8; + mac[3] = addr >> 16; + mac[2] = addr >> 24; + mac[1] = addr >> 32; + mac[0] = addr >> 40; +} + +void board_ti_set_ethaddr(int index) +{ + uint8_t mac_addr[6]; + int i; + u64 mac1, mac2; + u8 mac_addr1[6], mac_addr2[6]; + int num_macs; + /* + * Export any Ethernet MAC addresses from EEPROM. + * The 2 MAC addresses in EEPROM define the address range. + */ + board_ti_get_eth_mac_addr(0, mac_addr1); + board_ti_get_eth_mac_addr(1, mac_addr2); + + if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { + mac1 = mac_to_u64(mac_addr1); + mac2 = mac_to_u64(mac_addr2); + + /* must contain an address range */ + num_macs = mac2 - mac1 + 1; + /* <= 50 to protect against user programming error */ + if (num_macs > 0 && num_macs <= 50) { + for (i = 0; i < num_macs; i++) { + u64_to_mac(mac1 + i, mac_addr); + if (is_valid_ethaddr(mac_addr)) { + eth_setenv_enetaddr_by_index("eth", + i + index, + mac_addr); + } + } + } + } +} diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index 52b0075..88b0a59 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -193,4 +193,16 @@ u64 board_ti_get_emif2_size(void); */ void set_board_info_env(char *name); +/** + * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM + * @index: The first ethaddr environment variable to set + * + * EEPROM should be already read before calling this function. + * The EEPROM contains 2 MAC addresses which define the MAC address + * range (i.e. first and last MAC address). + * This function sets the ethaddr environment variable for all + * the available MAC addresses starting from ethaddr. + */ +void board_ti_set_ethaddr(int index); + #endif /* __BOARD_DETECT_H */ From patchwork Mon Mar 13 13:04:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95222 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1165459qgd; Mon, 13 Mar 2017 06:12:13 -0700 (PDT) X-Received: by 10.28.209.75 with SMTP id i72mr9578487wmg.31.1489410733754; Mon, 13 Mar 2017 06:12:13 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id o191si10824524wme.129.2017.03.13.06.12.13; Mon, 13 Mar 2017 06:12:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 3855AC21C5B; Mon, 13 Mar 2017 13:09:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7CB10C21C65; Mon, 13 Mar 2017 13:09:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9FD5CC21C6D; Mon, 13 Mar 2017 13:06:32 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 50D94C21C6E for ; Mon, 13 Mar 2017 13:06:28 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4qt7006704; Mon, 13 Mar 2017 08:04:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410292; bh=0BZlA0kZQa7r7D91unttvFgee9LgvpAwodYAUaD6f8s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dwrMxq8FlTmnWcwMyOteZxBoO7h+Rpk53zA9Tb0hq8hy62pvpne3za8ePlIRbiZeb AVCYXewxrwYuYiiN233Ct8df8nSNAxBxpPpfUfeIT5pbdgB68U4jfqMNsft8jIOY+Z bGpYo1ohCPGtekTCWkihHx0X0ktgkVngWVwTK6A4= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4lDk002169; Mon, 13 Mar 2017 08:04:47 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:46 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjO003968; Mon, 13 Mar 2017 08:04:45 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:28 +0200 Message-ID: <1489410273-10159-6-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 05/10] board: ti: am571x-idk: Support 6 port Ethernet or 4 port Ethernet with LCD X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The board can support either ICSS1 Ethernet ports or LCD based on J51 jumper. Factory default is ICSS1 Ethernet ports (i.e. Jumper not populated). Use the GPIO to detect the jumper setting and configure the pinmux accordingly. Also select the right DT blob based on the chosen configuration. J51 absent -> ICSS1 Ethernet, no LCD on VOUT -> am571x-idk.dtb J51 present -> LCD on VOUT, no ICSS1 Ethernet -> am571x-idk-lcd-osd.dtb At present we only support the assume it is the Legacy LCD. LCD detection mechanism needs to be added later to differentiate between legacy vs new LCD. For ICSS1 Ethernet pins use the following convention to set the pinmux as PMT data is not yet finalized. - If pin is output, set as PIN_OUTPUT - If pin is input and external pull resistor present set as PIN_INPUT - If pin is input and external pull resistor absent, set pull to same as that of the external PHY's internall pull. - Do not use SLEW_CONTROLon any pin. Cc: Nishanth Menon Signed-off-by: Roger Quadros Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- board/ti/am57xx/board.c | 40 +++++++++++++++++ board/ti/am57xx/mux_data.h | 104 ++++++++++++++++++++++++++++++--------------- 2 files changed, 109 insertions(+), 35 deletions(-) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 1611514..bf9ac73 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; +#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22) /* GPIO 7_11 */ #define GPIO_DDR_VTT_EN 203 @@ -449,6 +450,21 @@ void hw_data_init(void) *ctrl = &dra7xx_ctrl; } +bool am571x_idk_needs_lcd(void) +{ + bool needs_lcd; + + gpio_request(GPIO_ETH_LCD, "nLCD_Detect"); + if (gpio_get_value(GPIO_ETH_LCD)) + needs_lcd = false; + else + needs_lcd = true; + + gpio_free(GPIO_ETH_LCD); + + return needs_lcd; +} + int board_init(void) { gpmc_init(); @@ -459,6 +475,8 @@ int board_init(void) int board_late_init(void) { + char *idk_lcd; + setup_board_eeprom_env(); u8 val; @@ -489,6 +507,17 @@ int board_late_init(void) omap_die_id_serial(); + /* TBD: Add LCD panel detection once information is available */ + if (am571x_idk_needs_lcd()) + idk_lcd = "osd101t2045"; /* Default to legacy LCD */ + else + idk_lcd = "no"; + setenv("idk_lcd", idk_lcd); + +#if !defined(CONFIG_SPL_BUILD) + board_ti_set_ethaddr(2); +#endif + return 0; } @@ -551,6 +580,17 @@ void recalibrate_iodelay(void) do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); } + if (board_is_am571x_idk()) { + if (am571x_idk_needs_lcd()) { + pconf = core_padconf_array_vout_am571x_idk; + pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); + } else { + pconf = core_padconf_array_icss1eth_am571x_idk; + pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); + } + do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); + } + /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); err: diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 2f5243e..ff0e517 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -549,13 +549,6 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */ - {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mi1_col */ - {VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.pr1_mii1_txd1 */ - {VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_mii1_txd0 */ - {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */ - {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii1_txen */ - {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii1_txd3 */ - {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii1_txd2 */ {VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ @@ -570,35 +563,7 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */ @@ -727,6 +692,75 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */ }; +const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = { + /* PR1 MII0 */ + {VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.pr1_mii_mt0_clk */ + {VOUT1_D9, (M13 | PIN_OUTPUT)}, /* vout1_d9.pr1_mii0_txd3 */ + {VOUT1_D10, (M13 | PIN_OUTPUT)}, /* vout1_d10.pr1_mii0_txd2 */ + {VOUT1_D11, (M13 | PIN_OUTPUT)}, /* vout1_d11.pr1_mii0_txen */ + {VOUT1_D12, (M13 | PIN_OUTPUT)}, /* vout1_d12.pr1_mii0_txd1 */ + {VOUT1_D13, (M13 | PIN_OUTPUT)}, /* vout1_d13.pr1_mii0_txd0 */ + {VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.pr1_mii_mr0_clk */ + {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */ + {VOUT1_D16, (M12 | PIN_INPUT)}, /* vout1_d16.pr1_mii0_rxd3 */ + {VOUT1_D17, (M12 | PIN_INPUT)}, /* vout1_d17.pr1_mii0_rxd2 */ + {VOUT1_D18, (M12 | PIN_INPUT)}, /* vout1_d18.pr1_mii0_rxd1 */ + {VOUT1_D19, (M12 | PIN_INPUT)}, /* vout1_d19.pr1_mii0_rxd0 */ + {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */ + {VOUT1_D21, (M12 | PIN_INPUT)}, /* vout1_d21.pr1_mii0_rxlink */ + {VOUT1_D22, (M12 | PIN_INPUT)}, /* vout1_d22.pr1_mii0_col */ + {VOUT1_D23, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d23.pr1_mii0_crs */ + + /* PR1 MII1 */ + {VIN2A_D3, (M12 | PIN_INPUT)}, /* vin2a_d3.pr1_mi1_col */ + {VIN2A_D4, (M13 | PIN_OUTPUT)}, /* vin2a_d4.pr1_mii1_txd1 */ + {VIN2A_D5, (M13 | PIN_OUTPUT)}, /* vin2a_d5.pr1_mii1_txd0 */ + {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */ + {VIN2A_D7, (M11 | PIN_OUTPUT)}, /* vin2a_d7.pr1_mii1_txen */ + {VIN2A_D8, (M11 | PIN_OUTPUT)}, /* vin2a_d8.pr1_mii1_txd3 */ + {VIN2A_D9, (M11 | PIN_OUTPUT)}, /* vin2a_d9.pr1_mii1_txd2 */ + {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */ + {VOUT1_D0, (M12 | PIN_INPUT)}, /* vout1_d0.pr1_mii1_rxlink */ + {VOUT1_D1, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d1.pr1_mii1_crs */ + {VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.pr1_mii_mr1_clk */ + {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */ + {VOUT1_D4, (M12 | PIN_INPUT)}, /* vout1_d4.pr1_mii1_rxd3 */ + {VOUT1_D5, (M12 | PIN_INPUT)}, /* vout1_d5.pr1_mii1_rxd2 */ + {VOUT1_D6, (M12 | PIN_INPUT)}, /* vout1_d6.pr1_mii1_rxd1 */ + {VOUT1_D7, (M12 | PIN_INPUT)}, /* vout1_d7.pr1_mii1_rxd0 */ +}; + +const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = { + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ +}; + const struct pad_conf_entry early_padconf[] = { {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ From patchwork Mon Mar 13 13:04:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95220 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1164718qgd; Mon, 13 Mar 2017 06:10:40 -0700 (PDT) X-Received: by 10.28.18.134 with SMTP id 128mr9497062wms.53.1489410639988; Mon, 13 Mar 2017 06:10:39 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 18si10836274wms.61.2017.03.13.06.10.39; Mon, 13 Mar 2017 06:10:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 80400C21C81; Mon, 13 Mar 2017 13:08:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4F60C21C66; Mon, 13 Mar 2017 13:08:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2DF90C21C62; Mon, 13 Mar 2017 13:06:37 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 88836C21C66 for ; Mon, 13 Mar 2017 13:06:33 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4sLN006709; Mon, 13 Mar 2017 08:04:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410294; bh=0SRrBXDCuxbeKuNan1UTkfd5eGTWz++KMD3by6OiHxA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DIrE+GdSDbmQeRYRWHRdyBdK8ZDbWQguHk+VQjncwzS2mcCVCTkKOX8gx1ZRew1O7 wq4iBO+4y6RvQEgcdeqqWai4Z/PjhT7G+DuVYGRZ2d/ku42IYG8vuDk4H2L/Hh3gP4 semLrh2kOgcwVDorNk28FnBjxBSIG2TAjMjwjPNE= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4nRW031143; Mon, 13 Mar 2017 08:04:49 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:48 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjP003968; Mon, 13 Mar 2017 08:04:47 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:29 +0200 Message-ID: <1489410273-10159-7-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 06/10] board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use the same convention that was used for ICSS1 Ethernet - If pin is output, set as PIN_OUTPUT - If pin is input and external pull resistor present set as PIN_INPUT - If pin is input and external pull resistor absent, set pull to same as that of the external PHY's internall pull. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- board/ti/am57xx/mux_data.h | 62 +++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index ff0e517..5485212 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -586,46 +586,46 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */ {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */ {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ - {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */ {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */ {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */ {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ - {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */ {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */ {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */ {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */ - {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */ {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */ {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */ {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */ {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */ - {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */ {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */ {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */ {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */ @@ -642,18 +642,18 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */ - {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ - {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ - {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ - {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ - {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ - {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ - {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ - {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ - {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ - {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ - {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ From patchwork Mon Mar 13 13:04:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95216 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1163522qgd; Mon, 13 Mar 2017 06:08:12 -0700 (PDT) X-Received: by 10.223.168.80 with SMTP id l74mr28482614wrc.184.1489410491926; Mon, 13 Mar 2017 06:08:11 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l12si10811641wmd.87.2017.03.13.06.08.11; Mon, 13 Mar 2017 06:08:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 79EA3C21C78; Mon, 13 Mar 2017 13:06:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B3EF2C21C69; Mon, 13 Mar 2017 13:06:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 268A3C21C51; Mon, 13 Mar 2017 13:05:54 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 64625C21C6E for ; Mon, 13 Mar 2017 13:05:50 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4prs030108; Mon, 13 Mar 2017 08:04:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410291; bh=uEByKEyF+UIsyPeAjEgBNJ5RHRjPl9hVianGy/nHfa8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QsjjYTDmI9fa13j5J+Hv+HOJEEvOTlGLHsx4inXSKzaCRAzq1o4ocDlUSvSIyK/Yk eHvUhnvAOX6jbSbIXetbRyOeTzC9ldE7Flu6uJHTncucCXBLF9QSGcd1oeQUCx/bsm ixmm+BJuMQo+qDgbwMsKzROeUAKd9zI/NmC46Z/g= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4p5j031191; Mon, 13 Mar 2017 08:04:51 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:50 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjQ003968; Mon, 13 Mar 2017 08:04:49 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:30 +0200 Message-ID: <1489410273-10159-8-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 07/10] board: ti: am57xx-idk: Auto detect LCD Panel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nishanth Menon AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased. These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel itself has no registers that can be used to identify the panel, however, the touchscreen controllers on the panels are different. Hence to ease user experience, we can use the touch screen controller's ID information to detect what kind of panel we use and select the appropriate kernel dtb for the platform configuration. NOTE: AM572x IDK default configuration is for LCD Connectivity, however the AM571x IDK has a jumper (J51) that needs to be mounted for the IDK to operate with LCD (Vs two PRUSS ethernet port option). Touchscreen ID information is documented in: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf Acked-by: Lokesh Vutla Signed-off-by: Nishanth Menon Signed-off-by: Lokesh Vutla Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- board/ti/am57xx/board.c | 78 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 70 insertions(+), 8 deletions(-) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index bf9ac73..dab7743 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -54,6 +54,19 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO 7_11 */ #define GPIO_DDR_VTT_EN 203 +/* Touch screen controller to identify the LCD */ +#define OSD_TS_FT_BUS_ADDRESS 0 +#define OSD_TS_FT_CHIP_ADDRESS 0x38 +#define OSD_TS_FT_REG_ID 0xA3 +/* + * Touchscreen IDs for various OSD panels + * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf + */ +/* Used on newer osd101t2587 Panels */ +#define OSD_TS_FT_ID_5x46 0x54 +/* Used on older osd101t2045 Panels */ +#define OSD_TS_FT_ID_5606 0x08 + #define SYSINFO_BOARD_NAME_MAX_LEN 45 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB @@ -473,10 +486,64 @@ int board_init(void) return 0; } -int board_late_init(void) +void am57x_idk_lcd_detect(void) { - char *idk_lcd; + int r = -ENODEV; + char *idk_lcd = "no"; + uint8_t buf = 0; + + /* Only valid for IDKs */ + if (board_is_x15() || board_is_am572x_evm()) + return; + + /* Only AM571x IDK has gpio control detect.. so check that */ + if (board_is_am571x_idk() && !am571x_idk_needs_lcd()) + goto out; + + r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS); + if (r) { + printf("%s: Failed to set bus address to %d: %d\n", + __func__, OSD_TS_FT_BUS_ADDRESS, r); + goto out; + } + r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS); + if (r) { + /* AM572x IDK has no explicit settings for optional LCD kit */ + if (board_is_am571x_idk()) { + printf("%s: Touch screen detect failed: %d!\n", + __func__, r); + } + goto out; + } + + /* Read FT ID */ + r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1); + if (r) { + printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n", + __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, + OSD_TS_FT_REG_ID, r); + goto out; + } + + switch (buf) { + case OSD_TS_FT_ID_5606: + idk_lcd = "osd101t2045"; + break; + case OSD_TS_FT_ID_5x46: + idk_lcd = "osd101t2587"; + break; + default: + printf("%s: Unidentifed Touch screen ID 0x%02x\n", + __func__, buf); + /* we will let default be "no lcd" */ + } +out: + setenv("idk_lcd", idk_lcd); + return; +} +int board_late_init(void) +{ setup_board_eeprom_env(); u8 val; @@ -507,12 +574,7 @@ int board_late_init(void) omap_die_id_serial(); - /* TBD: Add LCD panel detection once information is available */ - if (am571x_idk_needs_lcd()) - idk_lcd = "osd101t2045"; /* Default to legacy LCD */ - else - idk_lcd = "no"; - setenv("idk_lcd", idk_lcd); + am57x_idk_lcd_detect(); #if !defined(CONFIG_SPL_BUILD) board_ti_set_ethaddr(2); From patchwork Mon Mar 13 13:04:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95217 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1164207qgd; Mon, 13 Mar 2017 06:09:36 -0700 (PDT) X-Received: by 10.223.155.135 with SMTP id d7mr25848977wrc.99.1489410576584; Mon, 13 Mar 2017 06:09:36 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 135si10823578wmi.92.2017.03.13.06.09.36; Mon, 13 Mar 2017 06:09:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 2C202C21C73; Mon, 13 Mar 2017 13:06:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4D420C21C4E; Mon, 13 Mar 2017 13:06:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9AE1DC21C5D; Mon, 13 Mar 2017 13:05:56 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 4CCE5C21C70 for ; Mon, 13 Mar 2017 13:05:52 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4rR6015651; Mon, 13 Mar 2017 08:04:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410293; bh=a124au5Z4o1rOSdOF/2BS6NRsIW1HMSBMARzUBQIf8I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yuRJBs7fsAln2BPPpd6vByf5S9NxjpJVF3fBVgxSoSJUPpyUendSBkk0ICtA44QTY GH0qZK2+WsO6WVPKL/5RlFcwAQRTeevPqi2arMSDKim5xBayYex06d2BPr/StOOTd3 3ozWFtA80/+W4OhY8QScWm8zPIN/KgQnYT0XhCjw= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4rAe002267; Mon, 13 Mar 2017 08:04:53 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:52 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjR003968; Mon, 13 Mar 2017 08:04:51 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:31 +0200 Message-ID: <1489410273-10159-9-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 08/10] ARM: Use Kconfig for board EEPROM's I2C bus and chip address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In stead of defining the board EEPROM address in the board headers let's define them in the board config files and make them configurable by Kconfig. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- board/ti/common/Kconfig | 20 +++++++++++++++++--- board/ti/ks2_evm/Kconfig | 2 ++ include/configs/am57xx_evm.h | 4 ---- include/configs/dra7xx_evm.h | 4 ---- 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 4980a04..162248c 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -1,12 +1,24 @@ -config SPL_ENV_SUPPORT - default y - config TI_I2C_BOARD_DETECT bool "Support for Board detection for TI platforms" help Support for detection board information on Texas Instrument's Evaluation Boards which have I2C based EEPROM detection +config EEPROM_BUS_ADDRESS + int "Board EEPROM's I2C bus address" + range 0 8 + default 0 + +config EEPROM_CHIP_ADDRESS + hex "Board EEPROM's I2C chip address" + range 0 0xff + default 0x50 + +if ARCH_OMAP2 + +config SPL_ENV_SUPPORT + default y + config SPL_EXT_SUPPORT default y @@ -39,3 +51,5 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y + +endif diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index c0568ec..9477f53 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -49,3 +49,5 @@ config SYS_CONFIG_NAME default "k2g_evm" endif + +source "board/ti/common/Kconfig" diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 3d8b996..40a3bbd 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -103,10 +103,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -/* EEPROM */ -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50 -#define CONFIG_EEPROM_BUS_ADDRESS 0 - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 549439e..2996807 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -261,8 +261,4 @@ #endif #endif /* NOR support */ -/* EEPROM */ -#define CONFIG_EEPROM_CHIP_ADDRESS 0x50 -#define CONFIG_EEPROM_BUS_ADDRESS 0 - #endif /* __CONFIG_DRA7XX_EVM_H */ From patchwork Mon Mar 13 13:04:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95219 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1164493qgd; Mon, 13 Mar 2017 06:10:13 -0700 (PDT) X-Received: by 10.223.171.239 with SMTP id s102mr26936158wrc.23.1489410613114; Mon, 13 Mar 2017 06:10:13 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id f21si606193wrf.78.2017.03.13.06.10.12; Mon, 13 Mar 2017 06:10:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 96FAAC21C53; Mon, 13 Mar 2017 13:07:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A53E4C21C65; Mon, 13 Mar 2017 13:06:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 32D12C21C56; Mon, 13 Mar 2017 13:05:59 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id B2747C21C67 for ; Mon, 13 Mar 2017 13:05:54 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4tZi030133; Mon, 13 Mar 2017 08:04:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410295; bh=jnoXpJt1H8R80jXBUb5NH6LIZgp+htk2/FaGdTzcNG4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qaSg+3ppB9/eQ6b1hW2dVyjB9VEzCx2RQjsoyuMD73+UqtMH2dwYmAhmjAzG8S1QE NROjFlCMBqRprG2CdEv3ujz56Kdnz0F1VuyF/rAc6TP8vPJQh3zCUEXQwO++cBftgL fyg/qXHRe7520T6FnlyuK7ilyi/NPYSCOneOvvrg= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4t5v002286; Mon, 13 Mar 2017 08:04:55 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:54 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjS003968; Mon, 13 Mar 2017 08:04:53 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:32 +0200 Message-ID: <1489410273-10159-10-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 09/10] ARM: k2g: setup PRU ethernet MAC addresses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" PRU ethernet MAC address range is present in the board EEPROM. Parse it and setup eth?addr environment variables. Signed-off-by: Roger Quadros Reviewed-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/mach-keystone/Kconfig | 2 ++ board/ti/ks2_evm/board_k2g.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index e1962c7..67f5fa0 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -15,6 +15,8 @@ config TARGET_K2L_EVM config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" + select BOARD_LATE_INIT + select TI_I2C_BOARD_DETECT endchoice diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 40edbaa..a738dd2 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -12,6 +12,7 @@ #include #include #include "mux-k2g.h" +#include "../common/board_detect.h" #define SYS_CLK 24000000 @@ -149,6 +150,24 @@ int board_early_init_f(void) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) + int rc; + + rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); + + board_ti_set_ethaddr(1); +#endif + + return 0; +} +#endif + #ifdef CONFIG_SPL_BUILD void spl_init_keystone_plls(void) { From patchwork Mon Mar 13 13:04:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95218 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1164339qgd; Mon, 13 Mar 2017 06:09:53 -0700 (PDT) X-Received: by 10.28.196.68 with SMTP id u65mr10461057wmf.8.1489410593109; Mon, 13 Mar 2017 06:09:53 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id w5si598572wra.125.2017.03.13.06.09.52; Mon, 13 Mar 2017 06:09:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 8EE5CC21C79; Mon, 13 Mar 2017 13:06:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B7368C21C71; Mon, 13 Mar 2017 13:06:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C83DAC21C66; Mon, 13 Mar 2017 13:06:03 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 8A998C21C4E for ; Mon, 13 Mar 2017 13:05:59 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4vjf030142; Mon, 13 Mar 2017 08:04:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410297; bh=WlVhfuvpH4LT4Klton4O1VrsQxusAUK77FEJqSGHo/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Becx9wdmShx5MHSTPdcAI2P9qVGD0bNZuB8/qc6aGuqdD34xlRKnV366TRD3dvbGH OiAiUx3hjXhMbPwlikofPQoqRR/10fUS+nbPXMO8eyuWbgovc2ZcsFsKtnUybkfzCx KDfjOwhXYyRlAhxHgzCVRQdTlhox66IbOIED7oww= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4vpc002339; Mon, 13 Mar 2017 08:04:57 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:56 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjT003968; Mon, 13 Mar 2017 08:04:55 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:33 +0200 Message-ID: <1489410273-10159-11-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 10/10] net: don't override ethernet address environment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If the ethernet address environment is set with a valid ethernet address prevent overriding it as it is most likely set by the user and he/she doesn't want board code to automatically override it whatsoever. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini --- net/eth_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/eth_common.c b/net/eth_common.c index e9d3c66..58fa295 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -34,6 +34,9 @@ int eth_setenv_enetaddr(const char *name, const uchar *enetaddr) { char buf[ARP_HLEN_ASCII + 1]; + if (eth_getenv_enetaddr(name, (uchar *)buf)) + return -EEXIST; + sprintf(buf, "%pM", enetaddr); return setenv(name, buf);