From patchwork Tue Sep 15 08:43:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 303981 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2338177ilg; Tue, 15 Sep 2020 01:43:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/aSwoN3QMvO/x+l2j/ad9Dwqzmy/f1QhgXsFdUb2gJzSBHU4ACOW2T/YxlTEkLHdPc4s2 X-Received: by 2002:a17:906:7cc6:: with SMTP id h6mr18890050ejp.266.1600159428988; Tue, 15 Sep 2020 01:43:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600159428; cv=none; d=google.com; s=arc-20160816; b=apLY0vyZqD9wn1vZ5ZIoZhAwKiUs6NvJSKFy4C+hMIAk3V+/XtRuwCVyqOfdTNn8AW 3oBC5K6htnS5u1SypSFSa/2gUqqalKNgXfdpfNrPskpLhGGgpeUPRyp6X+aEqOf2u0bD L7wJbOagaQTA9XyycNp6oTqu0apMCf0RSx1jAKG9w/ava8vZQCwjEci31niu+1XDMrnp EdErFPhftXMdwDJGPCj5Uq9JsFAg5KRPAbalTvPewOheahfC3u3Fh7eDLU/rBWu8Bii+ GddQSWPm/fI7OeinQQUNmuzKe9v16buvWlmW21rvQ77G9mMCv9X/6MME6T9S4LYelUly VYCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=RncGnlpGtNs0WlTRC29Y9GSx5wIGyqkem6ZQbLPSuA4=; b=B83Q+0qaubqrBCJ16gNMAmbiwJ0jeP2renrUxtEwp3UoxFiXOafrVzZOXI/znJr4tg Q/S+6s1Ner1KPB5V/9bFPMuT699cGrG2/XfoWeJx2R8aDgyw0cXPSaggQGUqSEsartcO pZzibtAPu2nYjVnF8RMc+HljluVMzOkJ1L5jmZvso0TxkMdbwejvUZKZdPtfOdunaNHM 4on7RHhp73HOu8xGVggAJaesTou7wrL48Xu/+u5HnTCKQslOVyURUOqx5h52dXctCX1P Ad2P3tvRRQZG6lk7V5mKWVr76vTCTlnrJMJZxG7iaYZFftSpUShgXbDbzrtON/mwMtD5 vSHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si9170345edr.49.2020.09.15.01.43.48; Tue, 15 Sep 2020 01:43:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726402AbgIOIns (ORCPT + 6 others); Tue, 15 Sep 2020 04:43:48 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56584 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726087AbgIOInm (ORCPT ); Tue, 15 Sep 2020 04:43:42 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 70B9E5729C63E5573513; Tue, 15 Sep 2020 16:43:40 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 15 Sep 2020 16:43:30 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Guo Ren , devicetree , linux-csky , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang , "Jianguo Chen" Subject: [PATCH v4 1/4] genirq: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER Date: Tue, 15 Sep 2020 16:43:02 +0800 Message-ID: <20200915084305.3085-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200915084305.3085-1-thunder.leizhen@huawei.com> References: <20200915084305.3085-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To avoid compilation error if an irqchip driver references the function set_handle_irq() but may not select GENERIC_IRQ_MULTI_HANDLER on some systems. For example, the Synopsys DesignWare APB interrupt controller (dw_apb_ictl) is used as the secondary interrupt controller on arc, csky, arm64, and most arm32 SoCs, and it's also used as the primary interrupt controller on Hisilicon SD5203 (an arm32 SoC). The latter need to use set_handle_irq() to register the top-level IRQ handler, but this multi irq handler registration mechanism is not implemented on arc system. The input parameter "handle_irq" maybe defined as static and only set_handle_irq() references it. This will trigger "defined but not used" warning. So add "(void)handle_irq" to suppress it. Signed-off-by: Zhen Lei --- include/linux/irq.h | 2 ++ 1 file changed, 2 insertions(+) -- 1.8.3 diff --git a/include/linux/irq.h b/include/linux/irq.h index 1b7f4dfee35b397..0848a2aaa9b40b1 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1252,6 +1252,8 @@ void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, * top-level IRQ handler. */ extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; +#else +#define set_handle_irq(handle_irq) do { (void)handle_irq; } while (0) #endif #endif /* _LINUX_IRQ_H */ From patchwork Tue Sep 15 08:43:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 303983 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2338235ilg; Tue, 15 Sep 2020 01:43:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxMnPEz50MkNsiE7fD9gMrldu17YWd2n4D8j4Wab6p6oyMTfS5uAXN1P4cu4OInDV7zP7v X-Received: by 2002:a50:d304:: with SMTP id g4mr21093569edh.248.1600159434154; Tue, 15 Sep 2020 01:43:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600159434; cv=none; d=google.com; s=arc-20160816; b=zevp269QDQVXCEDUbaCWsDaFqXd/+Zg4LhnYqTQiXmpWoGoSLYxMrDdA4WuU35NYTB y5OTtIzZ4YhACqY7fAWzQapCLGxsm5Ld0fIb6c7M0By7KpKhlQVi7w3QZ/1NzItjfDj9 +Fs+DhRPqN9t31ibBPbM/az1lIEQB0ZGuz886xcxD41bOUjgD5K30Sn19yLZLVoZcACv PwaPGGSjhJ/YkbMWEG1VfPiW47hLETGkh5EWcl+r9maUz6+MoxznOpPRxOFYqJUYVMQj 4bR7f3hsmRnjGuhvXX6Lm1N8AU4oGSU5uxMRDs9gTxOlQRH4+V8qcmGpCmM1ThLgRjWX tcOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=jKCPgBoZifUDjMMCwZGOSJO4/f7Mmp752AqKn/FNlvc=; b=HRnNMdX6aPXjhxng9Yy4KMc0uL9bpDKyVvoYaRLMPX+qw5D25DWhFBiyGFHhCr8hZD UO9HdYxafJqGIsZGDgYwyehRXZ9cVwldOh0345FXLby/UYTAR4/YBKJLck852Db0BIiT SnkCIzf3Drlo/H1VIWJG260hpSxV7ontLNSumCrP8e+s5rc6oQOk+rmjex58UwWgvWsZ zBbgIKr8NH+MDpfv9lhOR4fJ5mcAtlUUQEG8nk34wQkLh33Cvz28A6Z3XmDpliulbgdD Gcs9IAjpQOe/e1CYyQEAO0F26e4dXg/atN6AWv/xEQFxTDt48DD6YHHpyHakiNWVEnSa k+mg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k16si8892428ejb.210.2020.09.15.01.43.54; Tue, 15 Sep 2020 01:43:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726426AbgIOInw (ORCPT + 6 others); Tue, 15 Sep 2020 04:43:52 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56580 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726401AbgIOInt (ORCPT ); Tue, 15 Sep 2020 04:43:49 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 6725E6BE1B6002694F14; Tue, 15 Sep 2020 16:43:40 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 15 Sep 2020 16:43:31 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Guo Ren , devicetree , linux-csky , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang , "Jianguo Chen" Subject: [PATCH v4 2/4] irqchip: dw-apb-ictl: prepare for support hierarchy irq domain Date: Tue, 15 Sep 2020 16:43:03 +0800 Message-ID: <20200915084305.3085-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200915084305.3085-1-thunder.leizhen@huawei.com> References: <20200915084305.3085-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename some functions and variables in advance, to make the next patch looks more clear. The details are as follows: 1. rename dw_apb_ictl_handler() to dw_apb_ictl_handle_irq_cascaded(). 2. change (1 << hwirq) to BIT(hwirq). In function dw_apb_ictl_init(): 1. rename local variable irq to parent_irq. 2. add "const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops", then replace &irq_generic_chip_ops in other places with domain_ops. No functional change. Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/irq-dw-apb-ictl.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 1.8.3 diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index e4550e9c810ba94..5458004242e9d20 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -26,7 +26,7 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 -static void dw_apb_ictl_handler(struct irq_desc *desc) +static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -43,7 +43,7 @@ static void dw_apb_ictl_handler(struct irq_desc *desc) u32 virq = irq_find_mapping(d, gc->irq_base + hwirq); generic_handle_irq(virq); - stat &= ~(1 << hwirq); + stat &= ~BIT(hwirq); } } @@ -73,12 +73,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, struct irq_domain *domain; struct irq_chip_generic *gc; void __iomem *iobase; - int ret, nrirqs, irq, i; + int ret, nrirqs, parent_irq, i; u32 reg; + const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; /* Map the parent interrupt for the chained handler */ - irq = irq_of_parse_and_map(np, 0); - if (irq <= 0) { + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { pr_err("%pOF: unable to parse irq\n", np); return -EINVAL; } @@ -120,8 +121,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, else nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); - domain = irq_domain_add_linear(np, nrirqs, - &irq_generic_chip_ops, NULL); + domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL); if (!domain) { pr_err("%pOF: unable to add irq domain\n", np); ret = -ENOMEM; @@ -146,7 +146,8 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain); + irq_set_chained_handler_and_data(parent_irq, + dw_apb_ictl_handle_irq_cascaded, domain); return 0; From patchwork Tue Sep 15 08:43:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 303982 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2338193ilg; Tue, 15 Sep 2020 01:43:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDgZ66STC/NuQoGjmbafhetoMZfLSAZxm+iz0H7nuRcKod6vRpLg8O8fJ09OvzNfjmklol X-Received: by 2002:a17:906:7cc6:: with SMTP id h6mr18890127ejp.266.1600159430295; Tue, 15 Sep 2020 01:43:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600159430; cv=none; d=google.com; s=arc-20160816; b=UtWfCUVNLo33cpOLBiCkqeLRA76hpPGKxDsl3/XeOPNehUEod03R30Uo3V8XvyPa78 mmtCMshxtFzaHyCzp4yDoi0qmvn9KDSnpVuZJs0QzsVOAI+f2xhGjOrYeKLqxSxIMzYu vT3ZfvjVGjsH0P1Ey76/+YuWsewFyd4LJJX+fg7JAt9MNaKJXHFzqbRKMUx9GDUsmxGw IiCNxgaUIoFZrKBzVBqaVhRSsTis8BxE2fzWDRtCMJgtpojNZbmh0DubeZ6gfDNSaF/v HmZYVaQYxu3mL3EWdWV96qIjWR1FJyl/nKmPxOV1+3/MNUq8eevRHjhqI3QpsPOqTDE7 vdqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=RTSWwN5wysrw426Y6GMoSbsnTHALOD9sljibBRw0yjI=; b=caLe81EmENFMgh95MmuBxKVJpf2Z6kKrw4XzDDZoXhzTwySi/ZwBV6qn+XC5j5IAUr EqY1l1yEkBJJTsYuX7eCfjoNEha/RoiOLHoYFrGMELeE3f572MiAdT694QFa3FviOCJV YKzV3cm15D3w3pClRUhIVk3JK8HAA4ZF1GBHV9+H9G46Q3GQ5BILWIKRdk9fPMYJc08+ 6Yqnd/UlcLeNZeXrgmAcythontFKiq4UfvkywS6gcyLDpp6GUrKXKvL9OazoW/7zLRzH dE6ybZ20v2x+WiJlfGFLSIBodrfLeJ3kCr0T8qBWyxAPZtHE83KyPpB9kECeewpo2kZO I5CA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si9170345edr.49.2020.09.15.01.43.50; Tue, 15 Sep 2020 01:43:50 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726417AbgIOIns (ORCPT + 6 others); Tue, 15 Sep 2020 04:43:48 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56516 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726400AbgIOInn (ORCPT ); Tue, 15 Sep 2020 04:43:43 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 5588C4068A3ED1F2C5ED; Tue, 15 Sep 2020 16:43:40 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 15 Sep 2020 16:43:31 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Guo Ren , devicetree , linux-csky , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang , "Jianguo Chen" Subject: [PATCH v4 3/4] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Tue, 15 Sep 2020 16:43:04 +0800 Message-ID: <20200915084305.3085-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200915084305.3085-1-thunder.leizhen@huawei.com> References: <20200915084305.3085-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 74 ++++++++++++++++++++++++++++++++++----- 2 files changed, 67 insertions(+), 9 deletions(-) -- 1.8.3 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc31c..7c2d1c8fa551a66 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 5458004242e9d20..418183b9983dfad 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include #include #include +#include #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,27 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* irq domain of the primary interrupt controller. */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~BIT(hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +72,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -75,13 +121,20 @@ static int __init dw_apb_ictl_init(struct device_node *np, void __iomem *iobase; int ret, nrirqs, parent_irq, i; u32 reg; - const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; - - /* Map the parent interrupt for the chained handler */ - parent_irq = irq_of_parse_and_map(np, 0); - if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + const struct irq_domain_ops *domain_ops; + + if (!parent || (np == parent)) { + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + } else { + /* Map the parent interrupt for the chained handler */ + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + domain_ops = &irq_generic_chip_ops; } ret = of_address_to_resource(np, 0, &r); @@ -146,8 +199,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0; From patchwork Tue Sep 15 08:43:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 303984 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2338401ilg; Tue, 15 Sep 2020 01:44:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+RHv12jd6/QBbt/MQRsiucbWw6llG1PfcsI5HWcN8SyHt/RMdyAqDFYGtf0HrI7xAeCEL X-Received: by 2002:aa7:d891:: with SMTP id u17mr16668157edq.188.1600159450673; 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[23.128.96.18]) by mx.google.com with ESMTP id k16si8892428ejb.210.2020.09.15.01.44.10; Tue, 15 Sep 2020 01:44:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726410AbgIOIns (ORCPT + 6 others); Tue, 15 Sep 2020 04:43:48 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56550 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726403AbgIOInp (ORCPT ); Tue, 15 Sep 2020 04:43:45 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 5EE56B2ACE696567120D; Tue, 15 Sep 2020 16:43:40 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 15 Sep 2020 16:43:32 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Guo Ren , devicetree , linux-csky , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang , "Jianguo Chen" Subject: [PATCH v4 4/4] dt-bindings: dw-apb-ictl: support hierarchy irq domain Date: Tue, 15 Sep 2020 16:43:05 +0800 Message-ID: <20200915084305.3085-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200915084305.3085-1-thunder.leizhen@huawei.com> References: <20200915084305.3085-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Signed-off-by: Zhen Lei --- .../bindings/interrupt-controller/snps,dw-apb-ictl.txt | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt index 086ff08322db94f..2db59df9408f4c6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt @@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl) Synopsys DesignWare provides interrupt controller IP for APB known as dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. +APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt +controller in some SoCs, e.g. Hisilicon SD5203. Required properties: - compatible: shall be "snps,dw-apb-ictl" @@ -10,6 +11,8 @@ Required properties: region starting with ENABLE_LOW register - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +Additional required property when it's used as secondary interrupt controller: - interrupts: interrupt reference to primary interrupt controller The interrupt sources map to the corresponding bits in the interrupt @@ -21,6 +24,7 @@ registers, i.e. - (optional) fast interrupts start at 64. Example: + /* dw_apb_ictl is used as secondary interrupt controller */ aic: interrupt-controller@3000 { compatible = "snps,dw-apb-ictl"; reg = <0x3000 0xc00>; @@ -29,3 +33,11 @@ Example: interrupt-parent = <&gic>; interrupts = ; }; + + /* dw_apb_ictl is used as primary interrupt controller */ + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + };