From patchwork Tue Dec 12 14:52:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121525 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222016qgn; Tue, 12 Dec 2017 06:54:11 -0800 (PST) X-Google-Smtp-Source: ACJfBovhaer/gRQKw4/GkbiTeVONiqTSmYQXqdA2W1Va61CXFc7J1lxju09oO7zDT8j7Xh/V8ONp X-Received: by 10.101.92.74 with SMTP id v10mr2256922pgr.193.1513090451286; Tue, 12 Dec 2017 06:54:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090451; cv=none; d=google.com; s=arc-20160816; b=rYlHa3BFlbyE1uaUWswXzmoE3yXc3nqHpIziW+NKH0YxEMLxVyg6TBvvEMwb7rCgY9 JQ3T0Qld2dSshwYXARO75W5WiFc36d8WwOjaXf9RVHU/Ss9W2pAhYcgJLw9jysSJE302 yVcFRvnv4rJMRLF07MTZAprq3Y+6UHkFBRdRlM4+KiD3MK7IvS9bOaWC2f3qEKdLQovf 7qltO6QiYt7LcgA0pk/Yf8//3BzRfILdOWwe+fP/jKloXz6PqVHG9pqOj0j/E0cGma1D p9fiYXiXnFZg3fIVEZxBprQs4N3XlD9y//mH4T3C8aFVlkBSojvRigV8gMZhvjLFZ9r2 bDmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=wMyB5LMuOBJgfrYDol7+fi4hiVG4yBrVnLkVZli/7fk=; b=uNg6w5gnBomZBx0VnsyKV+5CJyI+wIzisNgdmFq4706IY9Jn3GJiue5T1HgD+3tNSn zZJ7u6ee+gf055Yj+1fyuNwlvBHzuu/DlvvJpljIQcDQNY0xE091iOSwex405oHc2wbk cayw63xNXo+pUYM9c4WeBGTqpzi2H5I2wxQI9J1wgz66KiSSrqWUw+ojG+fVextlfshU FlHwvUhbM7sZ6qVX1dHDVbS1iDxIK332mdhnocX+MApRtqvnTJTZdtMRLc//V8IXnIkn 4UfAkcV3oUDhqhkm2e2BiAtCpNUUFxBgl6YbdR2jpZ+6Ucyn7wbkn+Yrz41rTUFc9R2y bWLg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f84si11276354pfd.161.2017.12.12.06.54.11; Tue, 12 Dec 2017 06:54:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752628AbdLLOyJ (ORCPT + 1 other); Tue, 12 Dec 2017 09:54:09 -0500 Received: from foss.arm.com ([217.140.101.70]:45032 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752582AbdLLOyC (ORCPT ); Tue, 12 Dec 2017 09:54:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 819E015BE; Tue, 12 Dec 2017 06:54:01 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C5F4B3F577; Tue, 12 Dec 2017 06:53:58 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/24] staging: ccree: func params should follow func name Date: Tue, 12 Dec 2017 14:52:50 +0000 Message-Id: <1513090395-7938-5-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Fix some call sites with func params not following func name in AEAD code. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 408ea24..75a578e 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -1226,8 +1226,9 @@ static void cc_hmac_authenc(struct aead_request *req, struct cc_hw_desc desc[], struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *req_ctx = aead_request_ctx(req); int direct = req_ctx->gen_ctx.op_type; - unsigned int data_flow_mode = cc_get_data_flow( - direct, ctx->flow_mode, req_ctx->is_single_pass); + unsigned int data_flow_mode = + cc_get_data_flow(direct, ctx->flow_mode, + req_ctx->is_single_pass); if (req_ctx->is_single_pass) { /** @@ -1278,8 +1279,9 @@ cc_xcbc_authenc(struct aead_request *req, struct cc_hw_desc desc[], struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *req_ctx = aead_request_ctx(req); int direct = req_ctx->gen_ctx.op_type; - unsigned int data_flow_mode = cc_get_data_flow( - direct, ctx->flow_mode, req_ctx->is_single_pass); + unsigned int data_flow_mode = + cc_get_data_flow(direct, ctx->flow_mode, + req_ctx->is_single_pass); if (req_ctx->is_single_pass) { /** From patchwork Tue Dec 12 14:52:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121526 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222097qgn; Tue, 12 Dec 2017 06:54:15 -0800 (PST) X-Google-Smtp-Source: ACJfBoveJHBn5hYNuQAmAE9iGMmvD3p4eHDcT0bgpL6S5+kZ+KC8sS9v8C4HFm2Txc0H9kVM4Xvk X-Received: by 10.84.217.86 with SMTP id e22mr2500635plj.283.1513090455039; Tue, 12 Dec 2017 06:54:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090455; cv=none; d=google.com; s=arc-20160816; b=pcutK9DGgBPcgo025nHrm0BJQ4sYl/zjXybe9l7j0kgRWd0sGgohrH+97lC1o4tUKc nF7AxH8P6EAfwC1EyZ6po7N9+HK5kUk7FPy0TxiJcBFanIUhjuO3ZQLj31vajIZ3VcMj r/DAS/n36OZNvgoPg7B2tfH9YXkCN3pMqllnsIv2d0iKjZRcNydQXwnTwIrygNgbVcob nKYmMWzR8gOQP7QCX13if8m2DPA1/MYSddlRjQb8tlf4JIncRsys1fcVmhdGoT3o7cWN T4res3v8+OrDORqVYTApTpsURbpVFdG24hGeP/5WCvx08ByaoxGrQziv4vz7LOtMG0PL U+YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=S1b0Grvi/UMbAlo4i74++4Sboh4BNOf7hxH7GxANb2U=; b=jv86KwhunCEIQ0w6qBoAUvPkUdrKu0uXlyorRgOgVu8RRWursLNihdnq+khsylqZ+k U4xUwzOR4Rde32ZkPl1cLY1JjPnqQV+37rYhP4rISw850kFJQIJoV6ZuLFWRLlXz0SrQ 3wqwmTk2+8AIF3sJi1qAD/rpGC7CD98AAMNrHCTzgFUVGFMHw0IMxO3fNfB+9Yg/5o49 jk2apE328jEa9Vuj5YdPMcNywtSQFS+bP69auwxjYMxqAQg6vs8oAqdsLJ5APw2oaYdq GZs1qxL1copu7FbwkolmUiXk+SU/fBnWEfC/8CkU/2mDJqhVHnW7/ndKzwonZmBd+lqh B7MA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 12 Dec 2017 06:54:09 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A69FF3F577; Tue, 12 Dec 2017 06:54:06 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/24] staging: ccree: shorten parameter name Date: Tue, 12 Dec 2017 14:52:51 +0000 Message-Id: <1513090395-7938-6-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Shorten parameter name for better code readability Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 75a578e..62d45e9 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -2687,7 +2687,7 @@ static struct ssi_alg_template aead_algs[] = { }; static struct ssi_crypto_alg *cc_create_aead_alg( - struct ssi_alg_template *template, + struct ssi_alg_template *tmpl, struct device *dev) { struct ssi_crypto_alg *t_alg; @@ -2697,26 +2697,26 @@ static struct ssi_crypto_alg *cc_create_aead_alg( if (!t_alg) return ERR_PTR(-ENOMEM); - alg = &template->template_aead; + alg = &tmpl->template_aead; snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", - template->name); + tmpl->name); snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", - template->driver_name); + tmpl->driver_name); alg->base.cra_module = THIS_MODULE; alg->base.cra_priority = SSI_CRA_PRIO; alg->base.cra_ctxsize = sizeof(struct cc_aead_ctx); alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | - template->type; + tmpl->type; alg->init = cc_aead_init; alg->exit = cc_aead_exit; t_alg->aead_alg = *alg; - t_alg->cipher_mode = template->cipher_mode; - t_alg->flow_mode = template->flow_mode; - t_alg->auth_mode = template->auth_mode; + t_alg->cipher_mode = tmpl->cipher_mode; + t_alg->flow_mode = tmpl->flow_mode; + t_alg->auth_mode = tmpl->auth_mode; return t_alg; } From patchwork Tue Dec 12 14:52:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121529 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222514qgn; Tue, 12 Dec 2017 06:54:38 -0800 (PST) X-Google-Smtp-Source: ACJfBossksdECju2ATrDiMuiHD9rhENTumFYP9F+OIGreIivFVBlRf8Swf6si1smT9e88dfrPFk7 X-Received: by 10.99.176.3 with SMTP id h3mr2317743pgf.207.1513090478656; Tue, 12 Dec 2017 06:54:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090478; cv=none; d=google.com; s=arc-20160816; b=qDAuJ+gVxu/XdT9/pL/CzwctzdVeyM4Dj5XzNvYQ9iFp4FDMs/u4WbxFKsclEqDj85 0Itus0OrPRy/VcuTXFm1NBKe70+XMsGDiF2nkbE79lVCwvegWXXEiCTv4VdYHkg1fvGs D5FJQBu/Zq7c9To0b8LIZeG5HbF7MTUoqis3hPuBx9Jl3OrbI1DpVG21mEQcIbAkoKTB r24tGTH9eRGGfGZOvbp1IlPpLpAQpVy1BIvLexdqCZmB6WtNa2wQExZnhMJmiq1emtHM Jy/NIREbJrb1XAddXke9mQ25jtrNwA1STN5ee3q6dsHoqB1Dv//mniGWEZHkvY5RHPxB yHWg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id v9si10144691plo.199.2017.12.12.06.54.38; Tue, 12 Dec 2017 06:54:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751499AbdLLOyf (ORCPT + 1 other); Tue, 12 Dec 2017 09:54:35 -0500 Received: from foss.arm.com ([217.140.101.70]:45090 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752467AbdLLOyd (ORCPT ); Tue, 12 Dec 2017 09:54:33 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 339BD1529; Tue, 12 Dec 2017 06:54:33 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 432FA3F577; Tue, 12 Dec 2017 06:54:30 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/24] staging: ccree: fix func call param indentation Date: Tue, 12 Dec 2017 14:52:54 +0000 Message-Id: <1513090395-7938-9-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Fix function call parameter indentation according to coding style guide lines. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_buffer_mgr.c | 28 +++++++++++----------------- drivers/staging/ccree/ssi_hash.c | 10 ++++------ 2 files changed, 15 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 490dd5a..4ab76dc 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -239,9 +239,9 @@ static int cc_generate_mlli(struct device *dev, struct buffer_array *sg_data, dev_dbg(dev, "NUM of SG's = %d\n", sg_data->num_of_buffers); /* Allocate memory from the pointed pool */ - mlli_params->mlli_virt_addr = dma_pool_alloc( - mlli_params->curr_pool, GFP_KERNEL, - &mlli_params->mlli_dma_addr); + mlli_params->mlli_virt_addr = + dma_pool_alloc(mlli_params->curr_pool, GFP_KERNEL, + &mlli_params->mlli_dma_addr); if (!mlli_params->mlli_virt_addr) { dev_err(dev, "dma_pool_alloc() failed\n"); rc = -ENOMEM; @@ -881,27 +881,21 @@ static void cc_prepare_aead_data_dlli(struct aead_request *req, areq_ctx->is_icv_fragmented = false; if (req->src == req->dst) { /*INPLACE*/ - areq_ctx->icv_dma_addr = sg_dma_address( - areq_ctx->src_sgl) + + areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) + (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - areq_ctx->src_sgl) + + areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) + (*src_last_bytes - authsize); } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { /*NON-INPLACE and DECRYPT*/ - areq_ctx->icv_dma_addr = sg_dma_address( - areq_ctx->src_sgl) + + areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) + (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - areq_ctx->src_sgl) + + areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) + (*src_last_bytes - authsize); } else { /*NON-INPLACE and ENCRYPT*/ - areq_ctx->icv_dma_addr = sg_dma_address( - areq_ctx->dst_sgl) + + areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->dst_sgl) + (*dst_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - areq_ctx->dst_sgl) + + areq_ctx->icv_virt_addr = sg_virt(areq_ctx->dst_sgl) + (*dst_last_bytes - authsize); } } @@ -1660,8 +1654,8 @@ int cc_buffer_mgr_init(struct ssi_drvdata *drvdata) drvdata->buff_mgr_handle = buff_mgr_handle; - buff_mgr_handle->mlli_buffs_pool = dma_pool_create( - "dx_single_mlli_tables", dev, + buff_mgr_handle->mlli_buffs_pool = + dma_pool_create("dx_single_mlli_tables", dev, MAX_NUM_OF_TOTAL_MLLI_ENTRIES * LLI_ENTRY_BYTE_SIZE, MLLI_TABLE_MIN_ALIGNMENT, 0); diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index a80279e..29c17f3 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -951,9 +951,8 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, ctx->is_hmac = true; if (keylen) { - ctx->key_params.key_dma_addr = dma_map_single( - dev, (void *)key, - keylen, DMA_TO_DEVICE); + ctx->key_params.key_dma_addr = + dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE); if (dma_mapping_error(dev, ctx->key_params.key_dma_addr)) { dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n", key, keylen); @@ -1132,9 +1131,8 @@ static int cc_xcbc_setkey(struct crypto_ahash *ahash, ctx->key_params.keylen = keylen; - ctx->key_params.key_dma_addr = dma_map_single( - dev, (void *)key, - keylen, DMA_TO_DEVICE); + ctx->key_params.key_dma_addr = + dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE); if (dma_mapping_error(dev, ctx->key_params.key_dma_addr)) { dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n", key, keylen); From patchwork Tue Dec 12 14:52:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121530 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222699qgn; Tue, 12 Dec 2017 06:54:47 -0800 (PST) X-Google-Smtp-Source: ACJfBov2XOVBIxJAApY7VjGjiCLRNTkI6+Ah1/yiMlTh+dE8Bgejz6p6jfA01VM8YkbyW/JhkY/f X-Received: by 10.159.235.132 with SMTP id f4mr2540069plr.122.1513090487506; Tue, 12 Dec 2017 06:54:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090487; 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[209.132.180.67]) by mx.google.com with ESMTP id v9si10144691plo.199.2017.12.12.06.54.47; Tue, 12 Dec 2017 06:54:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752405AbdLLOyo (ORCPT + 1 other); Tue, 12 Dec 2017 09:54:44 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45102 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752467AbdLLOyl (ORCPT ); Tue, 12 Dec 2017 09:54:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 560301529; Tue, 12 Dec 2017 06:54:41 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 677B73F577; Tue, 12 Dec 2017 06:54:39 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/24] staging: ccree: fix reg mgr naming convention Date: Tue, 12 Dec 2017 14:52:55 +0000 Message-Id: <1513090395-7938-10-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The request manager files were using a func naming convention which was inconsistent (ssi vs. cc), included a useless prefix (ssi_request_mgr) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_driver.c | 8 +++---- drivers/staging/ccree/ssi_request_mgr.c | 40 ++++++++++++++++----------------- drivers/staging/ccree/ssi_request_mgr.h | 4 ++-- 3 files changed, 25 insertions(+), 27 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 513c5e4..491e2b9 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -326,9 +326,9 @@ static int init_cc_resources(struct platform_device *plat_dev) goto post_sram_mgr_err; } - rc = request_mgr_init(new_drvdata); + rc = cc_req_mgr_init(new_drvdata); if (rc) { - dev_err(dev, "request_mgr_init failed\n"); + dev_err(dev, "cc_req_mgr_init failed\n"); goto post_sram_mgr_err; } @@ -389,7 +389,7 @@ static int init_cc_resources(struct platform_device *plat_dev) post_buf_mgr_err: cc_buffer_mgr_fini(new_drvdata); post_req_mgr_err: - request_mgr_fini(new_drvdata); + cc_req_mgr_fini(new_drvdata); post_sram_mgr_err: ssi_sram_mgr_fini(new_drvdata); post_fips_init_err: @@ -422,7 +422,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) ssi_ivgen_fini(drvdata); cc_pm_fini(drvdata); cc_buffer_mgr_fini(drvdata); - request_mgr_fini(drvdata); + cc_req_mgr_fini(drvdata); ssi_sram_mgr_fini(drvdata); ssi_fips_fini(drvdata); #ifdef ENABLE_CC_SYSFS diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 5f34336..dbdfd0c 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -33,7 +33,7 @@ #define SSI_MAX_POLL_ITER 10 -struct ssi_request_mgr_handle { +struct cc_req_mgr_handle { /* Request manager resources */ unsigned int hw_queue_size; /* HW capability */ unsigned int min_free_hw_slots; @@ -68,9 +68,9 @@ static void comp_handler(unsigned long devarg); static void comp_work_handler(struct work_struct *work); #endif -void request_mgr_fini(struct ssi_drvdata *drvdata) +void cc_req_mgr_fini(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; + struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; struct device *dev = drvdata_to_dev(drvdata); if (!req_mgr_h) @@ -92,14 +92,14 @@ void request_mgr_fini(struct ssi_drvdata *drvdata) /* Kill tasklet */ tasklet_kill(&req_mgr_h->comptask); #endif - memset(req_mgr_h, 0, sizeof(struct ssi_request_mgr_handle)); + memset(req_mgr_h, 0, sizeof(struct cc_req_mgr_handle)); kfree(req_mgr_h); drvdata->request_mgr_handle = NULL; } -int request_mgr_init(struct ssi_drvdata *drvdata) +int cc_req_mgr_init(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *req_mgr_h; + struct cc_req_mgr_handle *req_mgr_h; struct device *dev = drvdata_to_dev(drvdata); int rc = 0; @@ -161,7 +161,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata) return 0; req_mgr_init_err: - request_mgr_fini(drvdata); + cc_req_mgr_fini(drvdata); return rc; } @@ -202,9 +202,9 @@ static void request_mgr_complete(struct device *dev, void *dx_compl_h) complete(this_compl); } -static int request_mgr_queues_status_check( +static int cc_queues_status( struct ssi_drvdata *drvdata, - struct ssi_request_mgr_handle *req_mgr_h, + struct cc_req_mgr_handle *req_mgr_h, unsigned int total_seq_len) { unsigned long poll_queue; @@ -264,7 +264,7 @@ int send_request( struct cc_hw_desc *desc, unsigned int len, bool is_dout) { void __iomem *cc_base = drvdata->cc_base; - struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; + struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; unsigned int used_sw_slots; unsigned int iv_seq_len = 0; unsigned int total_seq_len = len; /*initial sequence length*/ @@ -291,8 +291,7 @@ int send_request( * in case iv gen add the max size and in case of no dout add 1 * for the internal completion descriptor */ - rc = request_mgr_queues_status_check(drvdata, req_mgr_h, - max_required_seq_len); + rc = cc_queues_status(drvdata, req_mgr_h, max_required_seq_len); if (rc == 0) /* There is enough place in the queue */ break; @@ -418,14 +417,13 @@ int send_request_init( struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len) { void __iomem *cc_base = drvdata->cc_base; - struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; + struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; unsigned int total_seq_len = len; /*initial sequence length*/ int rc = 0; /* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */ - rc = request_mgr_queues_status_check(drvdata, req_mgr_h, - total_seq_len); + rc = cc_queues_status(drvdata, req_mgr_h, total_seq_len); if (rc) return rc; @@ -448,7 +446,7 @@ int send_request_init( void complete_request(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; complete(&drvdata->hw_queue_avail); @@ -474,7 +472,7 @@ static void proc_completions(struct ssi_drvdata *drvdata) { struct ssi_crypto_req *ssi_req; struct device *dev = drvdata_to_dev(drvdata); - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; unsigned int *tail = &request_mgr_handle->req_queue_tail; unsigned int *head = &request_mgr_handle->req_queue_head; @@ -540,7 +538,7 @@ static inline u32 cc_axi_comp_count(struct ssi_drvdata *drvdata) static void comp_handler(unsigned long devarg) { struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; u32 irq; @@ -590,7 +588,7 @@ static void comp_handler(unsigned long devarg) #if defined(CONFIG_PM) int cc_resume_req_queue(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; spin_lock_bh(&request_mgr_handle->hw_lock); @@ -606,7 +604,7 @@ int cc_resume_req_queue(struct ssi_drvdata *drvdata) */ int cc_suspend_req_queue(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; /* lock the send_request */ @@ -624,7 +622,7 @@ int cc_suspend_req_queue(struct ssi_drvdata *drvdata) bool cc_req_queue_suspended(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *request_mgr_handle = + struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; return request_mgr_handle->is_runtime_suspended; diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index 53eed5f..d018f51 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -23,7 +23,7 @@ #include "cc_hw_queue_defs.h" -int request_mgr_init(struct ssi_drvdata *drvdata); +int cc_req_mgr_init(struct ssi_drvdata *drvdata); /*! * Enqueue caller request to crypto hardware. @@ -47,7 +47,7 @@ int send_request_init( void complete_request(struct ssi_drvdata *drvdata); -void request_mgr_fini(struct ssi_drvdata *drvdata); +void cc_req_mgr_fini(struct ssi_drvdata *drvdata); #if defined(CONFIG_PM) int cc_resume_req_queue(struct ssi_drvdata *drvdata); From patchwork Tue Dec 12 14:52:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121532 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223032qgn; Tue, 12 Dec 2017 06:55:05 -0800 (PST) X-Google-Smtp-Source: ACJfBosjy8RomzFxifivLYCGx48/8w1wj8ubXGVX4kuLq062ozLQdFD5gvu6dfBSy/UvaV4ZNANk X-Received: by 10.159.251.151 with SMTP id m23mr2466234pls.347.1513090505070; Tue, 12 Dec 2017 06:55:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090505; cv=none; d=google.com; s=arc-20160816; b=ssNVBjKqlpIlzukJpbmv4l4DcgluaIVXkpn0F1Gf1lZjlj/hLmCJ4nVlrGLxGIAonj Q6lrf77x1XkUsVKyV40yPLRQQ/SoW7lNyb3NncSa6tiQf+kNf++nl8JaQs1K6m/C3RCe WUAFdhrTPOBWEfKYKXGAXZUYNkM/S5dgfT+opq2zB5UQvo2A7jy5OeNOnW29AGCRPICw uaKgyCkG7Gr/WHWa0DZodFdQtfaL6gpCG1ZNuxUh+g3gt53f5ngxC3Zz+XOb9AFyXdpe U54ctk2tI/uu/hDFQPGPZAVJsr/oGtRldYGXCP+ZfZSyqzb2KGxRl9Q+nLTTmjwq2BtX b11w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=XCAmwUw/NMfK95Ma772LnfXPW8uWjo7dhwgNGAFaXc0=; b=N0/wbzVU7/MjNIh07XYz1jN+ncoJQg8mh2j9Q2PQzVifRDyWO7+QzuWvlFjgImviyX Bwo7HqMVOh9qJYLjCRW6O3clbrtXWFOnieZlMaEr+fsCB5DfRr0Spscp82osA2m1Obj0 5WxBfUephB9uM5NM5j145D0Uhl/j5nAzStKmVgOD3DVJXyC/WFNlL9uvpzxTllaSB6bf MIBFACFAt8M0ayQGg2lTCyyTb57KFG49/OAzLxRaRpQBPea+qp/hU1R4IBAH9uOEbGtE lpx7xtlMCU4m0Zy2FAH3GNWR+kHxOy/LJoHqntvnsSqj8XL5v6RLcbIUPeaQM2vbBn5a QbnQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h1si12825645pfi.35.2017.12.12.06.55.04; Tue, 12 Dec 2017 06:55:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752379AbdLLOzD (ORCPT + 1 other); Tue, 12 Dec 2017 09:55:03 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45122 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751728AbdLLOy7 (ORCPT ); Tue, 12 Dec 2017 09:54:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22B611529; Tue, 12 Dec 2017 06:54:59 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C25D3F318; Tue, 12 Dec 2017 06:54:54 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/24] staging: ccree: remove cipher sync blkcipher remains Date: Tue, 12 Dec 2017 14:52:57 +0000 Message-Id: <1513090395-7938-12-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Remove the remains of no longer existing support for running blkcipher is sync mode. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_cipher.c | 156 ++++++++++++------------------------- 1 file changed, 51 insertions(+), 105 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index 7b484f1..0dc63f1 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -180,7 +180,7 @@ static unsigned int get_max_keysize(struct crypto_tfm *tfm) return 0; } -static int ssi_blkcipher_init(struct crypto_tfm *tfm) +static int ssi_ablkcipher_init(struct crypto_tfm *tfm) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct crypto_alg *alg = tfm->__crt_alg; @@ -189,10 +189,13 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) struct device *dev = drvdata_to_dev(ssi_alg->drvdata); int rc = 0; unsigned int max_key_buf_size = get_max_keysize(tfm); + struct ablkcipher_tfm *ablktfm = &tfm->crt_ablkcipher; dev_dbg(dev, "Initializing context @%p for %s\n", ctx_p, crypto_tfm_alg_name(tfm)); + ablktfm->reqsize = sizeof(struct blkcipher_req_ctx); + ctx_p->cipher_mode = ssi_alg->cipher_mode; ctx_p->flow_mode = ssi_alg->flow_mode; ctx_p->drvdata = ssi_alg->drvdata; @@ -297,10 +300,10 @@ static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num) return END_OF_KEYS; } -static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, - const u8 *key, +static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, unsigned int keylen) { + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(atfm); struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); u32 tmp[DES_EXPKEY_WORDS]; @@ -700,62 +703,59 @@ ssi_blkcipher_create_data_desc( } } -static int ssi_blkcipher_complete(struct device *dev, - struct ssi_ablkcipher_ctx *ctx_p, - struct blkcipher_req_ctx *req_ctx, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int ivsize, - void *areq) +static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req) { + struct ablkcipher_request *areq = (struct ablkcipher_request *)ssi_req; + struct scatterlist *dst = areq->dst; + struct scatterlist *src = areq->src; + struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(areq); + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq); + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm); int completion_error = 0; struct ablkcipher_request *req = (struct ablkcipher_request *)areq; cc_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); kfree(req_ctx->iv); - if (areq) { - /* - * The crypto API expects us to set the req->info to the last - * ciphertext block. For encrypt, simply copy from the result. - * For decrypt, we must copy from a saved buffer since this - * could be an in-place decryption operation and the src is - * lost by this point. - */ - if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { - memcpy(req->info, req_ctx->backup_info, ivsize); - kfree(req_ctx->backup_info); - } else { - scatterwalk_map_and_copy(req->info, req->dst, - (req->nbytes - ivsize), - ivsize, 0); - } - - ablkcipher_request_complete(areq, completion_error); - return 0; + /* + * The crypto API expects us to set the req->info to the last + * ciphertext block. For encrypt, simply copy from the result. + * For decrypt, we must copy from a saved buffer since this + * could be an in-place decryption operation and the src is + * lost by this point. + */ + if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { + memcpy(req->info, req_ctx->backup_info, ivsize); + kfree(req_ctx->backup_info); + } else { + scatterwalk_map_and_copy(req->info, req->dst, + (req->nbytes - ivsize), + ivsize, 0); } - return completion_error; + + ablkcipher_request_complete(areq, completion_error); } -static int ssi_blkcipher_process( - struct crypto_tfm *tfm, - struct blkcipher_req_ctx *req_ctx, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes, - void *info, //req info - unsigned int ivsize, - void *areq, - enum drv_crypto_direction direction) +static int cc_cipher_process(struct ablkcipher_request *req, + enum drv_crypto_direction direction) { + struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req); + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk_tfm); + struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req); + unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm); + struct scatterlist *dst = req->dst; + struct scatterlist *src = req->src; + unsigned int nbytes = req->nbytes; + void *info = req->info; struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; struct ssi_crypto_req ssi_req = {}; int rc, seq_len = 0, cts_restore_flag = 0; - dev_dbg(dev, "%s areq=%p info=%p nbytes=%d\n", + dev_dbg(dev, "%s req=%p info=%p nbytes=%d\n", ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? - "Encrypt" : "Decrypt"), areq, info, nbytes); + "Encrypt" : "Decrypt"), req, info, nbytes); /* STAT_PHASE_0: Init and sanity checks */ @@ -791,7 +791,7 @@ static int ssi_blkcipher_process( /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_ablkcipher_complete; - ssi_req.user_arg = (void *)areq; + ssi_req.user_arg = (void *)req; #ifdef ENABLE_CYCLE_COUNT ssi_req.op_type = (direction == DRV_CRYPTO_DIRECTION_DECRYPT) ? @@ -823,7 +823,7 @@ static int ssi_blkcipher_process( ssi_blkcipher_create_setup_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len); /* Data processing */ - ssi_blkcipher_create_data_desc(tfm, req_ctx, dst, src, nbytes, areq, + ssi_blkcipher_create_data_desc(tfm, req_ctx, dst, src, nbytes, req, desc, &seq_len); /* do we need to generate IV? */ @@ -836,25 +836,12 @@ static int ssi_blkcipher_process( /* STAT_PHASE_3: Lock HW and push sequence */ - rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, - (!areq) ? 0 : 1); - if (areq) { - if (rc != -EINPROGRESS) { - /* Failed to send the request or request completed - * synchronously - */ - cc_unmap_blkcipher_request(dev, req_ctx, ivsize, src, - dst); - } - - } else { - if (rc) { - cc_unmap_blkcipher_request(dev, req_ctx, ivsize, src, - dst); - } else { - rc = ssi_blkcipher_complete(dev, ctx_p, req_ctx, dst, - src, ivsize, NULL); - } + rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, 1); + if (rc != -EINPROGRESS) { + /* Failed to send the request or request completed + * synchronously + */ + cc_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); } exit_process: @@ -869,56 +856,19 @@ static int ssi_blkcipher_process( return rc; } -static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req) -{ - struct ablkcipher_request *areq = (struct ablkcipher_request *)ssi_req; - struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(areq); - struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq); - struct ssi_ablkcipher_ctx *ctx_p = crypto_ablkcipher_ctx(tfm); - unsigned int ivsize = crypto_ablkcipher_ivsize(tfm); - - ssi_blkcipher_complete(dev, ctx_p, req_ctx, areq->dst, areq->src, - ivsize, areq); -} - -/* Async wrap functions */ - -static int ssi_ablkcipher_init(struct crypto_tfm *tfm) -{ - struct ablkcipher_tfm *ablktfm = &tfm->crt_ablkcipher; - - ablktfm->reqsize = sizeof(struct blkcipher_req_ctx); - - return ssi_blkcipher_init(tfm); -} - -static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *tfm, - const u8 *key, - unsigned int keylen) -{ - return ssi_blkcipher_setkey(crypto_ablkcipher_tfm(tfm), key, keylen); -} - static int ssi_ablkcipher_encrypt(struct ablkcipher_request *req) { - struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req); - struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk_tfm); struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req); - unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm); req_ctx->is_giv = false; req_ctx->backup_info = NULL; - return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, - req->nbytes, req->info, ivsize, - (void *)req, - DRV_CRYPTO_DIRECTION_ENCRYPT); + return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT); } static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req) { struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req); - struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk_tfm); struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req); unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm); @@ -934,15 +884,11 @@ static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req) (req->nbytes - ivsize), ivsize, 0); req_ctx->is_giv = false; - return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, - req->nbytes, req->info, ivsize, - (void *)req, - DRV_CRYPTO_DIRECTION_DECRYPT); + return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_DECRYPT); } /* DX Block cipher alg */ static struct ssi_alg_template blkcipher_algs[] = { -/* Async template */ #if SSI_CC_HAS_AES_XTS { .name = "xts(aes)", From patchwork Tue Dec 12 14:52:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121534 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223419qgn; Tue, 12 Dec 2017 06:55:23 -0800 (PST) X-Google-Smtp-Source: ACJfBoslXm92K+J0/Ikuv71ddZKWpugWJ2wMjp6Bu144CSZOQHi4BEgf2i7TFwg+FsYExemzFclQ X-Received: by 10.98.133.65 with SMTP id u62mr2560859pfd.22.1513090523780; Tue, 12 Dec 2017 06:55:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090523; cv=none; d=google.com; s=arc-20160816; b=eLqXuwc/06+S7jeDvGWXcBkMpExaArohui7um3BVZr13FoC/VrZSY0Ib4i3S2FUBRb a8xzKt8AbrmJKgF+yXCN0pbx6fXH/G427iuqCfCg70HEQ5RTpV5sZUIfXZ+ky50yQKgg /n5PVEFGhYp7VLPkfxNicq85tp8sKsR1qiim6hffdKDdb0ZvVD58iXoeQKAvQUsuuO1G TxgYy5qE3KBELFi9pWW0L8jyaT2U2T8syDhAf5V1ZAYpoaPM98f9RRLvyk/xPG9DW97/ puLMQW31KbTJZAyLtX8Bj8uDE9x0cbCyzYwLul75/J3UOlSohh55727L/MLoai41Ehue cofw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id r82si6861696pfi.277.2017.12.12.06.55.23; Tue, 12 Dec 2017 06:55:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752435AbdLLOzW (ORCPT + 1 other); Tue, 12 Dec 2017 09:55:22 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45144 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752437AbdLLOzQ (ORCPT ); Tue, 12 Dec 2017 09:55:16 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1F7A1529; Tue, 12 Dec 2017 06:55:15 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 58F103F318; Tue, 12 Dec 2017 06:55:13 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/24] staging: ccree: fix cipher func def coding style Date: Tue, 12 Dec 2017 14:52:59 +0000 Message-Id: <1513090395-7938-14-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Fix cipher functions definition indentation according to coding style guide lines for better code readability Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_cipher.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index d7687a4..0b464d8 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -435,14 +435,11 @@ static int cc_cipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, return 0; } -static void -cc_setup_cipher_desc( - struct crypto_tfm *tfm, - struct blkcipher_req_ctx *req_ctx, - unsigned int ivsize, - unsigned int nbytes, - struct cc_hw_desc desc[], - unsigned int *seq_size) +static void cc_setup_cipher_desc(struct crypto_tfm *tfm, + struct blkcipher_req_ctx *req_ctx, + unsigned int ivsize, unsigned int nbytes, + struct cc_hw_desc desc[], + unsigned int *seq_size) { struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); @@ -565,12 +562,10 @@ cc_setup_cipher_desc( } #if SSI_CC_HAS_MULTI2 -static void cc_setup_multi2_desc( - struct crypto_tfm *tfm, - struct blkcipher_req_ctx *req_ctx, - unsigned int ivsize, - struct cc_hw_desc desc[], - unsigned int *seq_size) +static void cc_setup_multi2_desc(struct crypto_tfm *tfm, + struct blkcipher_req_ctx *req_ctx, + unsigned int ivsize, struct cc_hw_desc desc[], + unsigned int *seq_size) { struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); @@ -609,15 +604,12 @@ static void cc_setup_multi2_desc( } #endif /*SSI_CC_HAS_MULTI2*/ -static void -cc_setup_cipher_data( - struct crypto_tfm *tfm, - struct blkcipher_req_ctx *req_ctx, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes, - void *areq, - struct cc_hw_desc desc[], - unsigned int *seq_size) +static void cc_setup_cipher_data(struct crypto_tfm *tfm, + struct blkcipher_req_ctx *req_ctx, + struct scatterlist *dst, + struct scatterlist *src, unsigned int nbytes, + void *areq, struct cc_hw_desc desc[], + unsigned int *seq_size) { struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); From patchwork Tue Dec 12 14:53:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121539 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4224239qgn; Tue, 12 Dec 2017 06:56:03 -0800 (PST) X-Google-Smtp-Source: ACJfBoujHNQk/749qfI/y7lHoEM8WswrpsUbt5i4pnk2Zzi5EBSJi1cyHYJPBOz8W4EZBVRv1tQ3 X-Received: by 10.98.21.17 with SMTP id 17mr2597008pfv.120.1513090563570; Tue, 12 Dec 2017 06:56:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090563; cv=none; d=google.com; s=arc-20160816; b=Jkd9PG7sn3MU16fYIaXLuqllLooSrOJkbItyLbP9Vtjxw4dPBLrYMn36ip5K88QdhB 75XPQa7f5lDT4mpd1tF45NOtWLJV4vOLxqzpYJLZ0hiM4IteHyzwqkh7UsP161SST60T Cf5nnQ1+EqFkyqG6nFvrvJlfqXSjFDbTaH8mTKyxaYiOxasEX8SAqW+Pc6cyX4QiY+Ai oZIsIdOqnYr50zl/DecxUXMR4F302lJsOMybL2Ppp0XF/Dxaoy7I2CeLI+jK0IG7gcLV HupWcHruq4spF0ATZ9AsbP+/568aJ4caK92QrmLLSd3KBT+f6p5X+5Ke9xT3Tk29v8RC GD8g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id a13si11713975pgd.155.2017.12.12.06.56.03; Tue, 12 Dec 2017 06:56:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752945AbdLLO4C (ORCPT + 1 other); Tue, 12 Dec 2017 09:56:02 -0500 Received: from foss.arm.com ([217.140.101.70]:45196 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752942AbdLLOz6 (ORCPT ); Tue, 12 Dec 2017 09:55:58 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6661C1529; Tue, 12 Dec 2017 06:55:58 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 03BFF3F318; Tue, 12 Dec 2017 06:55:54 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/24] staging: ccree: rename all SSI to CC Date: Tue, 12 Dec 2017 14:53:04 +0000 Message-Id: <1513090395-7938-19-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Unify naming convention by renaming all SSI macros to CC. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 26 +++++------ drivers/staging/ccree/ssi_aead.h | 6 +-- drivers/staging/ccree/ssi_buffer_mgr.c | 78 ++++++++++++++++----------------- drivers/staging/ccree/ssi_buffer_mgr.h | 14 +++--- drivers/staging/ccree/ssi_cipher.c | 4 +- drivers/staging/ccree/ssi_cipher.h | 6 +-- drivers/staging/ccree/ssi_config.h | 4 +- drivers/staging/ccree/ssi_driver.c | 26 +++++------ drivers/staging/ccree/ssi_driver.h | 22 +++++----- drivers/staging/ccree/ssi_fips.c | 2 +- drivers/staging/ccree/ssi_fips.h | 6 +-- drivers/staging/ccree/ssi_hash.c | 6 +-- drivers/staging/ccree/ssi_hash.h | 6 +-- drivers/staging/ccree/ssi_ivgen.c | 8 ++-- drivers/staging/ccree/ssi_ivgen.h | 8 ++-- drivers/staging/ccree/ssi_pm.c | 2 +- drivers/staging/ccree/ssi_pm.h | 6 +-- drivers/staging/ccree/ssi_request_mgr.c | 16 +++---- drivers/staging/ccree/ssi_sram_mgr.c | 2 +- drivers/staging/ccree/ssi_sram_mgr.h | 10 ++--- drivers/staging/ccree/ssi_sysfs.h | 6 +-- 21 files changed, 132 insertions(+), 132 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index ac9961c..d07b38d 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -257,7 +257,7 @@ static void cc_aead_complete(struct device *dev, void *ssi_req) cc_copy_sg_portion(dev, areq_ctx->mac_buf, areq_ctx->dst_sgl, skip, (skip + ctx->authsize), - SSI_SG_FROM_BUF); + CC_SG_FROM_BUF); } /* If an IV was generated, copy it back to the user provided @@ -739,7 +739,7 @@ static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode, struct device *dev = drvdata_to_dev(ctx->drvdata); switch (assoc_dma_type) { - case SSI_DMA_BUF_DLLI: + case CC_DMA_BUF_DLLI: dev_dbg(dev, "ASSOC buffer type DLLI\n"); hw_desc_init(&desc[idx]); set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src), @@ -749,7 +749,7 @@ static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode, areq_ctx->cryptlen > 0) set_din_not_last_indication(&desc[idx]); break; - case SSI_DMA_BUF_MLLI: + case CC_DMA_BUF_MLLI: dev_dbg(dev, "ASSOC buffer type MLLI\n"); hw_desc_init(&desc[idx]); set_din_type(&desc[idx], DMA_MLLI, areq_ctx->assoc.sram_addr, @@ -759,7 +759,7 @@ static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode, areq_ctx->cryptlen > 0) set_din_not_last_indication(&desc[idx]); break; - case SSI_DMA_BUF_NULL: + case CC_DMA_BUF_NULL: default: dev_err(dev, "Invalid ASSOC buffer type\n"); } @@ -780,7 +780,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, struct device *dev = drvdata_to_dev(ctx->drvdata); switch (data_dma_type) { - case SSI_DMA_BUF_DLLI: + case CC_DMA_BUF_DLLI: { struct scatterlist *cipher = (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? @@ -797,7 +797,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, set_flow_mode(&desc[idx], flow_mode); break; } - case SSI_DMA_BUF_MLLI: + case CC_DMA_BUF_MLLI: { /* DOUBLE-PASS flow (as default) * assoc. + iv + data -compact in one table @@ -823,7 +823,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, set_flow_mode(&desc[idx], flow_mode); break; } - case SSI_DMA_BUF_NULL: + case CC_DMA_BUF_NULL: default: dev_err(dev, "AUTHENC: Invalid SRC/DST buffer type\n"); } @@ -847,7 +847,7 @@ static void cc_proc_cipher_desc(struct aead_request *areq, return; /*null processing*/ switch (data_dma_type) { - case SSI_DMA_BUF_DLLI: + case CC_DMA_BUF_DLLI: dev_dbg(dev, "CIPHER: SRC/DST buffer type DLLI\n"); hw_desc_init(&desc[idx]); set_din_type(&desc[idx], DMA_DLLI, @@ -860,7 +860,7 @@ static void cc_proc_cipher_desc(struct aead_request *areq, areq_ctx->cryptlen, NS_BIT, 0); set_flow_mode(&desc[idx], flow_mode); break; - case SSI_DMA_BUF_MLLI: + case CC_DMA_BUF_MLLI: dev_dbg(dev, "CIPHER: SRC/DST buffer type MLLI\n"); hw_desc_init(&desc[idx]); set_din_type(&desc[idx], DMA_MLLI, areq_ctx->src.sram_addr, @@ -869,7 +869,7 @@ static void cc_proc_cipher_desc(struct aead_request *areq, areq_ctx->dst.mlli_nents, NS_BIT, 0); set_flow_mode(&desc[idx], flow_mode); break; - case SSI_DMA_BUF_NULL: + case CC_DMA_BUF_NULL: default: dev_err(dev, "CIPHER: Invalid SRC/DST buffer type\n"); } @@ -1171,8 +1171,8 @@ static void cc_mlli_to_sram(struct aead_request *req, struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); - if (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI || - req_ctx->data_buff_type == SSI_DMA_BUF_MLLI || + if (req_ctx->assoc_buff_type == CC_DMA_BUF_MLLI || + req_ctx->data_buff_type == CC_DMA_BUF_MLLI || !req_ctx->is_single_pass) { dev_dbg(dev, "Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n", (unsigned int)ctx->drvdata->mlli_sram_addr, @@ -2670,7 +2670,7 @@ static struct ssi_crypto_alg *cc_create_aead_alg(struct ssi_alg_template *tmpl, snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->driver_name); alg->base.cra_module = THIS_MODULE; - alg->base.cra_priority = SSI_CRA_PRIO; + alg->base.cra_priority = CC_CRA_PRIO; alg->base.cra_ctxsize = sizeof(struct cc_aead_ctx); alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h index 5172241..e41040e 100644 --- a/drivers/staging/ccree/ssi_aead.h +++ b/drivers/staging/ccree/ssi_aead.h @@ -18,8 +18,8 @@ * ARM CryptoCell AEAD Crypto API */ -#ifndef __SSI_AEAD_H__ -#define __SSI_AEAD_H__ +#ifndef __CC_AEAD_H__ +#define __CC_AEAD_H__ #include #include @@ -119,4 +119,4 @@ struct aead_req_ctx { int cc_aead_alloc(struct ssi_drvdata *drvdata); int cc_aead_free(struct ssi_drvdata *drvdata); -#endif /*__SSI_AEAD_H__*/ +#endif /*__CC_AEAD_H__*/ diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index c28ce7c..ee5c086 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -61,11 +61,11 @@ struct buffer_array { static inline char *cc_dma_buf_type(enum ssi_req_dma_buf_type type) { switch (type) { - case SSI_DMA_BUF_NULL: + case CC_DMA_BUF_NULL: return "BUF_NULL"; - case SSI_DMA_BUF_DLLI: + case CC_DMA_BUF_DLLI: return "BUF_DLLI"; - case SSI_DMA_BUF_MLLI: + case CC_DMA_BUF_MLLI: return "BUF_MLLI"; default: return "BUF_INVALID"; @@ -163,7 +163,7 @@ void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg, nents = cc_get_sgl_nents(dev, sg, end, &lbytes, NULL); sg_copy_buffer(sg, nents, (void *)dest, (end - to_skip + 1), to_skip, - (direct == SSI_SG_TO_BUF)); + (direct == CC_SG_TO_BUF)); } static int cc_render_buff_to_mlli(struct device *dev, dma_addr_t buff_dma, @@ -457,7 +457,7 @@ static int ssi_ahash_handle_curr_buf(struct device *dev, &sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg), sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset, areq_ctx->buff_sg->length); - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI; areq_ctx->curr_sg = areq_ctx->buff_sg; areq_ctx->in_nents = 0; /* prepare for case of MLLI */ @@ -481,7 +481,7 @@ void cc_unmap_blkcipher_request(struct device *dev, void *ctx, DMA_TO_DEVICE); } /* Release pool */ - if (req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI) { + if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) { dma_pool_free(req_ctx->mlli_params.curr_pool, req_ctx->mlli_params.mlli_virt_addr, req_ctx->mlli_params.mlli_dma_addr); @@ -510,7 +510,7 @@ int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, int rc = 0; u32 mapped_nents = 0; - req_ctx->dma_buf_type = SSI_DMA_BUF_DLLI; + req_ctx->dma_buf_type = CC_DMA_BUF_DLLI; mlli_params->curr_pool = NULL; sg_data.num_of_buffers = 0; @@ -541,11 +541,11 @@ int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, goto ablkcipher_exit; } if (mapped_nents > 1) - req_ctx->dma_buf_type = SSI_DMA_BUF_MLLI; + req_ctx->dma_buf_type = CC_DMA_BUF_MLLI; if (src == dst) { /* Handle inplace operation */ - if (req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI) { + if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) { req_ctx->out_nents = 0; cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src, nbytes, 0, true, @@ -560,9 +560,9 @@ int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, goto ablkcipher_exit; } if (mapped_nents > 1) - req_ctx->dma_buf_type = SSI_DMA_BUF_MLLI; + req_ctx->dma_buf_type = CC_DMA_BUF_MLLI; - if (req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI) { + if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) { cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src, nbytes, 0, true, &req_ctx->in_mlli_nents); @@ -572,7 +572,7 @@ int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, } } - if (req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI) { + if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) { mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; rc = cc_generate_mlli(dev, &sg_data, mlli_params); if (rc) @@ -679,7 +679,7 @@ void cc_unmap_aead_request(struct device *dev, struct aead_request *req) * data memory overriding that caused by cache coherence * problem. */ - cc_copy_mac(dev, req, SSI_SG_FROM_BUF); + cc_copy_mac(dev, req, CC_SG_FROM_BUF); } } @@ -771,7 +771,7 @@ static int cc_aead_chain_iv(struct ssi_drvdata *drvdata, (areq_ctx->gen_ctx.iv_dma_addr + iv_ofs), iv_size_to_authenc, is_last, &areq_ctx->assoc.mlli_nents); - areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; + areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI; } chain_iv_exit: @@ -801,7 +801,7 @@ static int cc_aead_chain_assoc(struct ssi_drvdata *drvdata, } if (req->assoclen == 0) { - areq_ctx->assoc_buff_type = SSI_DMA_BUF_NULL; + areq_ctx->assoc_buff_type = CC_DMA_BUF_NULL; areq_ctx->assoc.nents = 0; areq_ctx->assoc.mlli_nents = 0; dev_dbg(dev, "Chain assoc of length 0: buff_type=%s nents=%u\n", @@ -851,18 +851,18 @@ static int cc_aead_chain_assoc(struct ssi_drvdata *drvdata, } if (mapped_nents == 1 && areq_ctx->ccm_hdr_size == ccm_header_size_null) - areq_ctx->assoc_buff_type = SSI_DMA_BUF_DLLI; + areq_ctx->assoc_buff_type = CC_DMA_BUF_DLLI; else - areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; + areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI; - if (do_chain || areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) { + if (do_chain || areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) { dev_dbg(dev, "Chain assoc: buff_type=%s nents=%u\n", cc_dma_buf_type(areq_ctx->assoc_buff_type), areq_ctx->assoc.nents); cc_add_sg_entry(dev, sg_data, areq_ctx->assoc.nents, req->src, req->assoclen, 0, is_last, &areq_ctx->assoc.mlli_nents); - areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; + areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI; } chain_assoc_exit: @@ -939,7 +939,7 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, * we must neglect this code. */ if (!drvdata->coherent) - cc_copy_mac(dev, req, SSI_SG_TO_BUF); + cc_copy_mac(dev, req, CC_SG_TO_BUF); areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { @@ -981,7 +981,7 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, * MAC verification upon request completion */ if (areq_ctx->is_icv_fragmented) { - cc_copy_mac(dev, req, SSI_SG_TO_BUF); + cc_copy_mac(dev, req, CC_SG_TO_BUF); areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { /* Contig. ICV */ @@ -1136,12 +1136,12 @@ static int cc_aead_chain_data(struct ssi_drvdata *drvdata, if (src_mapped_nents > 1 || dst_mapped_nents > 1 || do_chain) { - areq_ctx->data_buff_type = SSI_DMA_BUF_MLLI; + areq_ctx->data_buff_type = CC_DMA_BUF_MLLI; rc = cc_prepare_aead_data_mlli(drvdata, req, sg_data, &src_last_bytes, &dst_last_bytes, is_last_table); } else { - areq_ctx->data_buff_type = SSI_DMA_BUF_DLLI; + areq_ctx->data_buff_type = CC_DMA_BUF_DLLI; cc_prepare_aead_data_dlli(req, &src_last_bytes, &dst_last_bytes); } @@ -1156,13 +1156,13 @@ static void cc_update_aead_mlli_nents(struct ssi_drvdata *drvdata, struct aead_req_ctx *areq_ctx = aead_request_ctx(req); u32 curr_mlli_size = 0; - if (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) { + if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) { areq_ctx->assoc.sram_addr = drvdata->mlli_sram_addr; curr_mlli_size = areq_ctx->assoc.mlli_nents * LLI_ENTRY_BYTE_SIZE; } - if (areq_ctx->data_buff_type == SSI_DMA_BUF_MLLI) { + if (areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) { /*Inplace case dst nents equal to src nents*/ if (req->src == req->dst) { areq_ctx->dst.mlli_nents = areq_ctx->src.mlli_nents; @@ -1226,7 +1226,7 @@ int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) if (drvdata->coherent && areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT && req->src == req->dst) - cc_copy_mac(dev, req, SSI_SG_TO_BUF); + cc_copy_mac(dev, req, CC_SG_TO_BUF); /* cacluate the size for cipher remove ICV in decrypt*/ areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type == @@ -1380,8 +1380,8 @@ int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) /* Mlli support -start building the MLLI according to the above * results */ - if (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI || - areq_ctx->data_buff_type == SSI_DMA_BUF_MLLI) { + if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI || + areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) { mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; rc = cc_generate_mlli(dev, &sg_data, mlli_params); if (rc) @@ -1419,7 +1419,7 @@ int cc_map_hash_request_final(struct ssi_drvdata *drvdata, void *ctx, dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X src=%pK curr_index=%u\n", curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index); /* Init the type of the dma buffer */ - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL; mlli_params->curr_pool = NULL; sg_data.num_of_buffers = 0; areq_ctx->in_nents = 0; @@ -1445,19 +1445,19 @@ int cc_map_hash_request_final(struct ssi_drvdata *drvdata, void *ctx, goto unmap_curr_buff; } if (src && mapped_nents == 1 && - areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { + areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) { memcpy(areq_ctx->buff_sg, src, sizeof(struct scatterlist)); areq_ctx->buff_sg->length = nbytes; areq_ctx->curr_sg = areq_ctx->buff_sg; - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI; } else { - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_MLLI; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI; } } /*build mlli */ - if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI) { + if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) { mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; /* add the src data to the sg_data */ cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src, nbytes, @@ -1507,7 +1507,7 @@ int cc_map_hash_request_update(struct ssi_drvdata *drvdata, void *ctx, dev_dbg(dev, " update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X src=%pK curr_index=%u\n", curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index); /* Init the type of the dma buffer */ - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL; mlli_params->curr_pool = NULL; areq_ctx->curr_sg = NULL; sg_data.num_of_buffers = 0; @@ -1539,7 +1539,7 @@ int cc_map_hash_request_update(struct ssi_drvdata *drvdata, void *ctx, *next_buff_cnt); cc_copy_sg_portion(dev, next_buff, src, (update_data_len - *curr_buff_cnt), - nbytes, SSI_SG_TO_BUF); + nbytes, CC_SG_TO_BUF); /* change the buffer index for next operation */ swap_index = 1; } @@ -1561,19 +1561,19 @@ int cc_map_hash_request_update(struct ssi_drvdata *drvdata, void *ctx, goto unmap_curr_buff; } if (mapped_nents == 1 && - areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { + areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) { /* only one entry in the SG and no previous data */ memcpy(areq_ctx->buff_sg, src, sizeof(struct scatterlist)); areq_ctx->buff_sg->length = update_data_len; - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI; areq_ctx->curr_sg = areq_ctx->buff_sg; } else { - areq_ctx->data_dma_buf_type = SSI_DMA_BUF_MLLI; + areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI; } } - if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI) { + if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) { mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; /* add the src data to the sg_data */ cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src, diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h index f6411de..77744a6 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.h +++ b/drivers/staging/ccree/ssi_buffer_mgr.h @@ -18,8 +18,8 @@ * Buffer Manager */ -#ifndef __SSI_BUFFER_MGR_H__ -#define __SSI_BUFFER_MGR_H__ +#ifndef __CC_BUFFER_MGR_H__ +#define __CC_BUFFER_MGR_H__ #include @@ -27,14 +27,14 @@ #include "ssi_driver.h" enum ssi_req_dma_buf_type { - SSI_DMA_BUF_NULL = 0, - SSI_DMA_BUF_DLLI, - SSI_DMA_BUF_MLLI + CC_DMA_BUF_NULL = 0, + CC_DMA_BUF_DLLI, + CC_DMA_BUF_MLLI }; enum ssi_sg_cpy_direct { - SSI_SG_TO_BUF = 0, - SSI_SG_FROM_BUF = 1 + CC_SG_TO_BUF = 0, + CC_SG_FROM_BUF = 1 }; struct ssi_mlli { diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index 299e73a..c437a79 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -541,7 +541,7 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, return; } /* Process */ - if (req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI) { + if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) { dev_dbg(dev, " data params addr %pad length 0x%X\n", &sg_dma_address(src), nbytes); dev_dbg(dev, " data params addr %pad length 0x%X\n", @@ -1091,7 +1091,7 @@ struct ssi_crypto_alg *cc_cipher_create_alg(struct ssi_alg_template *template, snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", template->driver_name); alg->cra_module = THIS_MODULE; - alg->cra_priority = SSI_CRA_PRIO; + alg->cra_priority = CC_CRA_PRIO; alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct cc_cipher_ctx); diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index ef6d6e9..977b543 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -18,8 +18,8 @@ * ARM CryptoCell Cipher Crypto API */ -#ifndef __SSI_CIPHER_H__ -#define __SSI_CIPHER_H__ +#ifndef __CC_CIPHER_H__ +#define __CC_CIPHER_H__ #include #include @@ -84,4 +84,4 @@ static inline bool cc_is_hw_key(struct crypto_tfm *tfm) #endif /* CRYPTO_TFM_REQ_HW_KEY */ -#endif /*__SSI_CIPHER_H__*/ +#endif /*__CC_CIPHER_H__*/ diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index ea74845..e97bc68 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -18,8 +18,8 @@ * Definitions for ARM CryptoCell Linux Crypto Driver */ -#ifndef __SSI_CONFIG_H__ -#define __SSI_CONFIG_H__ +#ifndef __CC_CONFIG_H__ +#define __CC_CONFIG_H__ #include diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index f4164eb..dce12e1 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -110,27 +110,27 @@ static irqreturn_t cc_isr(int irq, void *dev_id) drvdata->irq = irr; /* Completion interrupt - most probable */ - if (irr & SSI_COMP_IRQ_MASK) { + if (irr & CC_COMP_IRQ_MASK) { /* Mask AXI completion interrupt - will be unmasked in * Deferred service handler */ - cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_COMP_IRQ_MASK); - irr &= ~SSI_COMP_IRQ_MASK; + cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_COMP_IRQ_MASK); + irr &= ~CC_COMP_IRQ_MASK; complete_request(drvdata); } #ifdef CC_SUPPORT_FIPS /* TEE FIPS interrupt */ - if (irr & SSI_GPR0_IRQ_MASK) { + if (irr & CC_GPR0_IRQ_MASK) { /* Mask interrupt - will be unmasked in Deferred service * handler */ - cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_GPR0_IRQ_MASK); - irr &= ~SSI_GPR0_IRQ_MASK; + cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK); + irr &= ~CC_GPR0_IRQ_MASK; fips_handler(drvdata); } #endif /* AXI error interrupt */ - if (irr & SSI_AXI_ERR_IRQ_MASK) { + if (irr & CC_AXI_ERR_IRQ_MASK) { u32 axi_err; /* Read the AXI error ID */ @@ -138,7 +138,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id) dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", axi_err); - irr &= ~SSI_AXI_ERR_IRQ_MASK; + irr &= ~CC_AXI_ERR_IRQ_MASK; } if (irr) { @@ -157,7 +157,7 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) /* Unmask all AXI interrupt sources AXI_CFG1 register */ val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); - cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK); + cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); dev_dbg(dev, "AXIM_CFG=0x%08X\n", cc_ioread(drvdata, CC_REG(AXIM_CFG))); @@ -167,8 +167,8 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) cc_iowrite(drvdata, CC_REG(HOST_ICR), val); /* Unmask relevant interrupt cause */ - val = (unsigned int)(~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK | - SSI_GPR0_IRQ_MASK)); + val = (unsigned int)(~(CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK | + CC_GPR0_IRQ_MASK)); cc_iowrite(drvdata, CC_REG(HOST_IMR), val); #ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET @@ -289,7 +289,7 @@ static int init_cc_resources(struct platform_device *plat_dev) /* Display HW versions */ dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", - SSI_DEV_NAME_STR, + CC_DEV_NAME_STR, cc_ioread(new_drvdata, CC_REG(HOST_VERSION)), DRV_MODULE_VERSION); @@ -309,7 +309,7 @@ static int init_cc_resources(struct platform_device *plat_dev) rc = ssi_fips_init(new_drvdata); if (rc) { - dev_err(dev, "SSI_FIPS_INIT failed 0x%x\n", rc); + dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc); goto post_sysfs_err; } rc = ssi_sram_mgr_init(new_drvdata); diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index c9fdb89..3d4513b 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -18,8 +18,8 @@ * ARM CryptoCell Linux Crypto Driver */ -#ifndef __SSI_DRIVER_H__ -#define __SSI_DRIVER_H__ +#ifndef __CC_DRIVER_H__ +#define __CC_DRIVER_H__ #include "ssi_config.h" #ifdef COMP_IN_WQ @@ -51,17 +51,17 @@ #define DRV_MODULE_VERSION "3.0" -#define SSI_DEV_NAME_STR "cc715ree" +#define CC_DEV_NAME_STR "cc715ree" #define CC_COHERENT_CACHE_PARAMS 0xEEE -#define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ +#define CC_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT)) -#define SSI_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) +#define CC_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) -#define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) +#define CC_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ @@ -71,9 +71,9 @@ #define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET /* TEE FIPS status interrupt */ -#define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT) +#define CC_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT) -#define SSI_CRA_PRIO 3000 +#define CC_CRA_PRIO 3000 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */ @@ -88,11 +88,11 @@ * field in the HW descriptor. The DMA engine +8 that value. */ -#define SSI_MAX_IVGEN_DMA_ADDRESSES 3 +#define CC_MAX_IVGEN_DMA_ADDRESSES 3 struct ssi_crypto_req { void (*user_cb)(struct device *dev, void *req); void *user_arg; - dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; + dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES]; /* For the first 'ivgen_dma_addr_len' addresses of this array, * generated IV would be placed in it by send_request(). * Same generated IV for all addresses! @@ -192,5 +192,5 @@ static inline u32 cc_ioread(struct ssi_drvdata *drvdata, u32 reg) return ioread32(drvdata->cc_base + reg); } -#endif /*__SSI_DRIVER_H__*/ +#endif /*__CC_DRIVER_H__*/ diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c index 4aea99f..273b414 100644 --- a/drivers/staging/ccree/ssi_fips.c +++ b/drivers/staging/ccree/ssi_fips.c @@ -88,7 +88,7 @@ static void fips_dsr(unsigned long devarg) struct device *dev = drvdata_to_dev(drvdata); u32 irq, state, val; - irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK)); + irq = (drvdata->irq & (CC_GPR0_IRQ_MASK)); if (irq) { state = cc_ioread(drvdata, CC_REG(GPR_HOST)); diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h index 8cb1893..1889c74 100644 --- a/drivers/staging/ccree/ssi_fips.h +++ b/drivers/staging/ccree/ssi_fips.h @@ -14,8 +14,8 @@ * along with this program; if not, see . */ -#ifndef __SSI_FIPS_H__ -#define __SSI_FIPS_H__ +#ifndef __CC_FIPS_H__ +#define __CC_FIPS_H__ #ifdef CONFIG_CRYPTO_FIPS @@ -46,5 +46,5 @@ static inline void fips_handler(struct ssi_drvdata *drvdata) {} #endif /* CONFIG_CRYPTO_FIPS */ -#endif /*__SSI_FIPS_H__*/ +#endif /*__CC_FIPS_H__*/ diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 10c73ef..7458c24 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -1988,7 +1988,7 @@ static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template, } alg->cra_module = THIS_MODULE; alg->cra_ctxsize = sizeof(struct cc_hash_ctx); - alg->cra_priority = SSI_CRA_PRIO; + alg->cra_priority = CC_CRA_PRIO; alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_exit = cc_cra_exit; @@ -2345,7 +2345,7 @@ static void cc_set_desc(struct ahash_req_ctx *areq_ctx, unsigned int idx = *seq_size; struct device *dev = drvdata_to_dev(ctx->drvdata); - if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_DLLI) { + if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_DLLI) { hw_desc_init(&desc[idx]); set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq_ctx->curr_sg), @@ -2353,7 +2353,7 @@ static void cc_set_desc(struct ahash_req_ctx *areq_ctx, set_flow_mode(&desc[idx], flow_mode); idx++; } else { - if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { + if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) { dev_dbg(dev, " NULL mode\n"); /* nothing to build */ return; diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index ade4119..19fc4cf 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -18,8 +18,8 @@ * ARM CryptoCell Hash Crypto API */ -#ifndef __SSI_HASH_H__ -#define __SSI_HASH_H__ +#ifndef __CC_HASH_H__ +#define __CC_HASH_H__ #include "ssi_buffer_mgr.h" @@ -103,5 +103,5 @@ cc_digest_len_addr(void *drvdata, u32 mode); */ ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode); -#endif /*__SSI_HASH_H__*/ +#endif /*__CC_HASH_H__*/ diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index c499361..d362bf6 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -62,7 +62,7 @@ static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx, { unsigned int idx = *iv_seq_len; - if ((*iv_seq_len + CC_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) { + if ((*iv_seq_len + CC_IVPOOL_GEN_SEQ_LEN) > CC_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } @@ -119,7 +119,7 @@ static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx, int cc_init_iv_sram(struct ssi_drvdata *drvdata) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; - struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; + struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN]; unsigned int iv_seq_len = 0; int rc; @@ -247,7 +247,7 @@ int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], iv_out_size != CTR_RFC3686_IV_SIZE) { return -EINVAL; } - if ((iv_out_dma_len + 1) > SSI_IVPOOL_SEQ_LEN) { + if ((iv_out_dma_len + 1) > CC_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } @@ -255,7 +255,7 @@ int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], /* check that number of generated IV is limited to max dma address * iv buffer size */ - if (iv_out_dma_len > SSI_MAX_IVGEN_DMA_ADDRESSES) { + if (iv_out_dma_len > CC_MAX_IVGEN_DMA_ADDRESSES) { /* The sequence will be longer than allowed */ return -EINVAL; } diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h index bbd0245..9890f62 100644 --- a/drivers/staging/ccree/ssi_ivgen.h +++ b/drivers/staging/ccree/ssi_ivgen.h @@ -14,12 +14,12 @@ * along with this program; if not, see . */ -#ifndef __SSI_IVGEN_H__ -#define __SSI_IVGEN_H__ +#ifndef __CC_IVGEN_H__ +#define __CC_IVGEN_H__ #include "cc_hw_queue_defs.h" -#define SSI_IVPOOL_SEQ_LEN 8 +#define CC_IVPOOL_SEQ_LEN 8 /*! * Allocates iv-pool and maps resources. @@ -65,4 +65,4 @@ int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len); -#endif /*__SSI_IVGEN_H__*/ +#endif /*__CC_IVGEN_H__*/ diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c index f0e3baf..e387d46 100644 --- a/drivers/staging/ccree/ssi_pm.c +++ b/drivers/staging/ccree/ssi_pm.c @@ -123,7 +123,7 @@ int cc_pm_init(struct ssi_drvdata *drvdata) struct device *dev = drvdata_to_dev(drvdata); /* must be before the enabling to avoid resdundent suspending */ - pm_runtime_set_autosuspend_delay(dev, SSI_SUSPEND_TIMEOUT); + pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT); pm_runtime_use_autosuspend(dev); /* activate the PM module */ rc = pm_runtime_set_active(dev); diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h index 50bcf03..940ef2d 100644 --- a/drivers/staging/ccree/ssi_pm.h +++ b/drivers/staging/ccree/ssi_pm.h @@ -17,13 +17,13 @@ /* \file ssi_pm.h */ -#ifndef __SSI_POWER_MGR_H__ -#define __SSI_POWER_MGR_H__ +#ifndef __CC_POWER_MGR_H__ +#define __CC_POWER_MGR_H__ #include "ssi_config.h" #include "ssi_driver.h" -#define SSI_SUSPEND_TIMEOUT 3000 +#define CC_SUSPEND_TIMEOUT 3000 int cc_pm_init(struct ssi_drvdata *drvdata); diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 3d25b72..436e035 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -31,7 +31,7 @@ #include "ssi_ivgen.h" #include "ssi_pm.h" -#define SSI_MAX_POLL_ITER 10 +#define CC_MAX_POLL_ITER 10 struct cc_req_mgr_handle { /* Request manager resources */ @@ -223,7 +223,7 @@ static int cc_queues_status(struct ssi_drvdata *drvdata, return 0; /* Wait for space in HW queue. Poll constant num of iterations. */ - for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) { + for (poll_queue = 0; poll_queue < CC_MAX_POLL_ITER ; poll_queue++) { req_mgr_h->q_free_slots = cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); if (req_mgr_h->q_free_slots < req_mgr_h->min_free_hw_slots) @@ -265,13 +265,13 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, unsigned int used_sw_slots; unsigned int iv_seq_len = 0; unsigned int total_seq_len = len; /*initial sequence length*/ - struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; + struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN]; struct device *dev = drvdata_to_dev(drvdata); int rc; unsigned int max_required_seq_len = (total_seq_len + ((ssi_req->ivgen_dma_addr_len == 0) ? 0 : - SSI_IVPOOL_SEQ_LEN) + (!is_dout ? 1 : 0)); + CC_IVPOOL_SEQ_LEN) + (!is_dout ? 1 : 0)); #if defined(CONFIG_PM) rc = cc_pm_get(dev); @@ -541,13 +541,13 @@ static void comp_handler(unsigned long devarg) u32 irq; - irq = (drvdata->irq & SSI_COMP_IRQ_MASK); + irq = (drvdata->irq & CC_COMP_IRQ_MASK); - if (irq & SSI_COMP_IRQ_MASK) { + if (irq & CC_COMP_IRQ_MASK) { /* To avoid the interrupt from firing as we unmask it, * we clear it now */ - cc_iowrite(drvdata, CC_REG(HOST_ICR), SSI_COMP_IRQ_MASK); + cc_iowrite(drvdata, CC_REG(HOST_ICR), CC_COMP_IRQ_MASK); /* Avoid race with above clear: Test completion counter * once more @@ -566,7 +566,7 @@ static void comp_handler(unsigned long devarg) } while (request_mgr_handle->axi_completed > 0); cc_iowrite(drvdata, CC_REG(HOST_ICR), - SSI_COMP_IRQ_MASK); + CC_COMP_IRQ_MASK); request_mgr_handle->axi_completed += cc_axi_comp_count(drvdata); diff --git a/drivers/staging/ccree/ssi_sram_mgr.c b/drivers/staging/ccree/ssi_sram_mgr.c index 0704031..cbe5e3b 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.c +++ b/drivers/staging/ccree/ssi_sram_mgr.c @@ -80,7 +80,7 @@ ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size) size); return NULL_SRAM_ADDR; } - if (size > (SSI_CC_SRAM_SIZE - smgr_ctx->sram_free_offset)) { + if (size > (CC_CC_SRAM_SIZE - smgr_ctx->sram_free_offset)) { dev_err(dev, "Not enough space to allocate %u B (at offset %llu)\n", size, smgr_ctx->sram_free_offset); return NULL_SRAM_ADDR; diff --git a/drivers/staging/ccree/ssi_sram_mgr.h b/drivers/staging/ccree/ssi_sram_mgr.h index 76719ec..fdd325b 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.h +++ b/drivers/staging/ccree/ssi_sram_mgr.h @@ -14,11 +14,11 @@ * along with this program; if not, see . */ -#ifndef __SSI_SRAM_MGR_H__ -#define __SSI_SRAM_MGR_H__ +#ifndef __CC_SRAM_MGR_H__ +#define __CC_SRAM_MGR_H__ -#ifndef SSI_CC_SRAM_SIZE -#define SSI_CC_SRAM_SIZE 4096 +#ifndef CC_CC_SRAM_SIZE +#define CC_CC_SRAM_SIZE 4096 #endif struct ssi_drvdata; @@ -75,4 +75,4 @@ void cc_set_sram_desc(const u32 *src, ssi_sram_addr_t dst, unsigned int nelement, struct cc_hw_desc *seq, unsigned int *seq_len); -#endif /*__SSI_SRAM_MGR_H__*/ +#endif /*__CC_SRAM_MGR_H__*/ diff --git a/drivers/staging/ccree/ssi_sysfs.h b/drivers/staging/ccree/ssi_sysfs.h index 5124528..de68bc6 100644 --- a/drivers/staging/ccree/ssi_sysfs.h +++ b/drivers/staging/ccree/ssi_sysfs.h @@ -18,8 +18,8 @@ * ARM CryptoCell sysfs APIs */ -#ifndef __SSI_SYSFS_H__ -#define __SSI_SYSFS_H__ +#ifndef __CC_SYSFS_H__ +#define __CC_SYSFS_H__ #include @@ -29,4 +29,4 @@ struct ssi_drvdata; int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata); void ssi_sysfs_fini(void); -#endif /*__SSI_SYSFS_H__*/ +#endif /*__CC_SYSFS_H__*/ From patchwork Tue Dec 12 14:53:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121540 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4224424qgn; Tue, 12 Dec 2017 06:56:13 -0800 (PST) X-Google-Smtp-Source: ACJfBov79WWcMIext302h/lGfn0q3s8UgW5myXWdn2sxmBYkeROmLR6+NWB1V0jszkcOdY8IVrNu X-Received: by 10.84.246.21 with SMTP id k21mr2471336pll.256.1513090573513; Tue, 12 Dec 2017 06:56:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090573; cv=none; d=google.com; s=arc-20160816; b=XTmUtWM/ChnTgt5iElIvxAcw5KGW2tg3T9pNyprDckzmoOT6LiYIcqrzWIOXwiLmWh SID4rNRIaSQFIEZgAzsHO5oCkjZMGMSpLfYIq7aeaniBluTI/+A+1Df+alvonXk2i/rJ fxWUg+Rmb6511eWnlfn8fYiPSZRhBM3QiD+u9Zy6N8wIacp1ErFzIXOc/4SpEb455xZJ d/IEQf+46b7Jmzp7jywM/f3vQQrHPZQ2q0NmmipmnlYNVReb9OcEL1iloKDT/Ttto9e/ GnzY4yHU+wFvbpg89U5OmwHCJOgZtHAL6jldnYxV3JhM8V/Ts1YeKyJYnVqUVsyMpvfc suwQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id j33si11834403pld.699.2017.12.12.06.56.13; Tue, 12 Dec 2017 06:56:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752379AbdLLO4M (ORCPT + 1 other); Tue, 12 Dec 2017 09:56:12 -0500 Received: from foss.arm.com ([217.140.101.70]:45208 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752942AbdLLO4H (ORCPT ); Tue, 12 Dec 2017 09:56:07 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98CAC1529; Tue, 12 Dec 2017 06:56:06 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 986CB3F318; Tue, 12 Dec 2017 06:56:03 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/24] staging: ccree: rename all DX to CC Date: Tue, 12 Dec 2017 14:53:05 +0000 Message-Id: <1513090395-7938-20-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Unify naming convention by renaming all DX macros to CC. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_hw_queue_defs.h | 4 +- drivers/staging/ccree/cc_lli_defs.h | 2 +- drivers/staging/ccree/dx_crys_kernel.h | 314 +++++++++++++++---------------- drivers/staging/ccree/dx_host.h | 262 +++++++++++++------------- drivers/staging/ccree/dx_reg_common.h | 10 +- drivers/staging/ccree/ssi_config.h | 8 +- drivers/staging/ccree/ssi_driver.c | 18 +- drivers/staging/ccree/ssi_driver.h | 26 +-- drivers/staging/ccree/ssi_hash.c | 18 +- drivers/staging/ccree/ssi_hash.h | 2 +- drivers/staging/ccree/ssi_request_mgr.c | 2 +- drivers/staging/ccree/ssi_sysfs.c | 10 +- 12 files changed, 338 insertions(+), 338 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index 3ca548d..7c25a4f 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -31,11 +31,11 @@ #define HW_QUEUE_SLOTS_MAX 15 #define CC_REG_LOW(word, name) \ - (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) + (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) #define CC_REG_HIGH(word, name) \ (CC_REG_LOW(word, name) + \ - DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) + CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) #define CC_GENMASK(word, name) \ GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) diff --git a/drivers/staging/ccree/cc_lli_defs.h b/drivers/staging/ccree/cc_lli_defs.h index a9c417b..861634a 100644 --- a/drivers/staging/ccree/cc_lli_defs.h +++ b/drivers/staging/ccree/cc_lli_defs.h @@ -20,7 +20,7 @@ #include /* Max DLLI size - * AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE + * AKA CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE */ #define DLLI_SIZE_BIT_SIZE 0x18 diff --git a/drivers/staging/ccree/dx_crys_kernel.h b/drivers/staging/ccree/dx_crys_kernel.h index 2196030..30719f4 100644 --- a/drivers/staging/ccree/dx_crys_kernel.h +++ b/drivers/staging/ccree/dx_crys_kernel.h @@ -14,167 +14,167 @@ * along with this program; if not, see . */ -#ifndef __DX_CRYS_KERNEL_H__ -#define __DX_CRYS_KERNEL_H__ +#ifndef __CC_CRYS_KERNEL_H__ +#define __CC_CRYS_KERNEL_H__ // -------------------------------------- // BLOCK: DSCRPTR // -------------------------------------- -#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL -#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL -#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL -#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL -#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL -#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL -#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL -#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL -#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL -#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL -#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL -#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL -#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL -#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL -#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL -#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL -#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL -#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL -#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL -#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL -#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL -#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL -#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL -#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL -#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL -#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL -#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL -#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL -#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL -#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL +#define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL +#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL +#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL +#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL +#define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL +#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL +#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL +#define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL +#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL +#define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL +#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL +#define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL +#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL +#define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL +#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL +#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL +#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL +#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL +#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL +#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL +#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL +#define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL +#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL +#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL +#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL +#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL +#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL +#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL +#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL +#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL +#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL +#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL +#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL +#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL +#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL +#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL +#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL +#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL +#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL +#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL +#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL +#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL +#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL +#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL +#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL +#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL +#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL +#define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL +#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL +#define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL +#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL +#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL // -------------------------------------- // BLOCK: AXI_P // -------------------------------------- -#define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL -#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL -#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL -#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL -#define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL -#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL -#define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL -#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL -#define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL -#define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL -#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL -#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL -#define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL -#define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL -#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL -#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL -#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL -#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL -#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL -#define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL -#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL -#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL -#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL -#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL -#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL -#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL -#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL -#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL -#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL -#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL -#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL -#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL -#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL -#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL -#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL -#endif // __DX_CRYS_KERNEL_H__ +#define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL +#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL +#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL +#define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL +#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL +#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL +#define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL +#define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL +#define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL +#define CC_AXIM_MON_ERR_REG_OFFSET 0xBC4UL +#define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL +#define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL +#define CC_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL +#define CC_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL +#define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL +#define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL +#define CC_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL +#define CC_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL +#define CC_AXIM_CFG_REG_OFFSET 0xBE8UL +#define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL +#define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL +#define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL +#define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL +#define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL +#define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL +#define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL +#define CC_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL +#define CC_AXIM_ACE_CONST_REG_OFFSET 0xBECUL +#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL +#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL +#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL +#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL +#define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL +#define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL +#define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL +#define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL +#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL +#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL +#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL +#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL +#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL +#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL +#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL +#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL +#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL +#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL +#define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL +#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL +#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL +#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL +#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL +#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL +#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL +#endif // __CC_CRYS_KERNEL_H__ diff --git a/drivers/staging/ccree/dx_host.h b/drivers/staging/ccree/dx_host.h index 863c267..e90afbc 100644 --- a/drivers/staging/ccree/dx_host.h +++ b/drivers/staging/ccree/dx_host.h @@ -14,142 +14,142 @@ * along with this program; if not, see . */ -#ifndef __DX_HOST_H__ -#define __DX_HOST_H__ +#ifndef __CC_HOST_H__ +#define __CC_HOST_H__ // -------------------------------------- // BLOCK: HOST_P // -------------------------------------- -#define DX_HOST_IRR_REG_OFFSET 0xA00UL -#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL -#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL -#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_GPR0_BIT_SHIFT 0xBUL -#define DX_HOST_IRR_GPR0_BIT_SIZE 0x1UL -#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL -#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL -#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL -#define DX_HOST_IMR_REG_OFFSET 0xA04UL -#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL -#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL -#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL -#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_GPR0_BIT_SHIFT 0xBUL -#define DX_HOST_IMR_GPR0_BIT_SIZE 0x1UL -#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL -#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL -#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL -#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL -#define DX_HOST_ICR_REG_OFFSET 0xA08UL -#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL -#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL -#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL -#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL -#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL -#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL -#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL -#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_BOOT_REG_OFFSET 0xA28UL -#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL -#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL -#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL -#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL -#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL -#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL -#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL -#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL -#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL -#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL -#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL -#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL -#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL -#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL -#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL -#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL -#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL -#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL -#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL -#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL -#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL -#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL -#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL -#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL -#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL -#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL -#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL -#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL -#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL -#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_VERSION_REG_OFFSET 0xA40UL -#define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL -#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL -#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL -#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL -#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_GPR0_REG_OFFSET 0xA70UL -#define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL -#define DX_GPR_HOST_REG_OFFSET 0xA74UL -#define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL -#define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL -#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL +#define CC_HOST_IRR_REG_OFFSET 0xA00UL +#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL +#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL +#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL +#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL +#define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL +#define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL +#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL +#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL +#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL +#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL +#define CC_HOST_IMR_REG_OFFSET 0xA04UL +#define CC_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL +#define CC_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL +#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL +#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL +#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL +#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL +#define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL +#define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL +#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL +#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL +#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL +#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL +#define CC_HOST_ICR_REG_OFFSET 0xA08UL +#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL +#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL +#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL +#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL +#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL +#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL +#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL +#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL +#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL +#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL +#define CC_HOST_SIGNATURE_REG_OFFSET 0xA24UL +#define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL +#define CC_HOST_BOOT_REG_OFFSET 0xA28UL +#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL +#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL +#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL +#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL +#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL +#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL +#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL +#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL +#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL +#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL +#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL +#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL +#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL +#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL +#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL +#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL +#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL +#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL +#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL +#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL +#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL +#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL +#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL +#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL +#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL +#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL +#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL +#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL +#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL +#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define CC_HOST_VERSION_REG_OFFSET 0xA40UL +#define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL +#define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL +#define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL +#define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL +#define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL +#define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL +#define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL +#define CC_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL +#define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL +#define CC_HOST_GPR0_REG_OFFSET 0xA70UL +#define CC_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_GPR0_VALUE_BIT_SIZE 0x20UL +#define CC_GPR_HOST_REG_OFFSET 0xA74UL +#define CC_GPR_HOST_VALUE_BIT_SHIFT 0x0UL +#define CC_GPR_HOST_VALUE_BIT_SIZE 0x20UL +#define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL +#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL +#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL // -------------------------------------- // BLOCK: HOST_SRAM // -------------------------------------- -#define DX_SRAM_DATA_REG_OFFSET 0xF00UL -#define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL -#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL -#define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL -#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL -#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL +#define CC_SRAM_DATA_REG_OFFSET 0xF00UL +#define CC_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL +#define CC_SRAM_DATA_VALUE_BIT_SIZE 0x20UL +#define CC_SRAM_ADDR_REG_OFFSET 0xF04UL +#define CC_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL +#define CC_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL +#define CC_SRAM_DATA_READY_REG_OFFSET 0xF08UL +#define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL +#define CC_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL -#endif //__DX_HOST_H__ +#endif //__CC_HOST_H__ diff --git a/drivers/staging/ccree/dx_reg_common.h b/drivers/staging/ccree/dx_reg_common.h index d5132ff..8334d9f 100644 --- a/drivers/staging/ccree/dx_reg_common.h +++ b/drivers/staging/ccree/dx_reg_common.h @@ -14,13 +14,13 @@ * along with this program; if not, see . */ -#ifndef __DX_REG_COMMON_H__ -#define __DX_REG_COMMON_H__ +#ifndef __CC_REG_COMMON_H__ +#define __CC_REG_COMMON_H__ -#define DX_DEV_SIGNATURE 0xDCC71200UL +#define CC_DEV_SIGNATURE 0xDCC71200UL #define CC_HW_VERSION 0xef840015UL -#define DX_DEV_SHA_MAX 512 +#define CC_DEV_SHA_MAX 512 -#endif /*__DX_REG_COMMON_H__*/ +#endif /*__CC_REG_COMMON_H__*/ diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index e97bc68..ee2d310 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -25,14 +25,14 @@ //#define FLUSH_CACHE_ALL //#define COMPLETION_DELAY -//#define DX_DUMP_DESCS -// #define DX_DUMP_BYTES +//#define CC_DUMP_DESCS +// #define CC_DUMP_BYTES // #define CC_DEBUG /* Enable sysfs interface for debugging REE driver */ #define ENABLE_CC_SYSFS -//#define DX_IRQ_DELAY 100000 +//#define CC_IRQ_DELAY 100000 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */ #define DMA_BIT_MASK_LEN 48 -#endif /*__DX_CONFIG_H__*/ +#endif /*__CC_CONFIG_H__*/ diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index dce12e1..078d146 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -72,7 +72,7 @@ #include "ssi_pm.h" #include "ssi_fips.h" -#ifdef DX_DUMP_BYTES +#ifdef CC_DUMP_BYTES void dump_byte_array(const char *name, const u8 *buf, size_t len) { char prefix[NAME_LEN]; @@ -171,10 +171,10 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) CC_GPR0_IRQ_MASK)); cc_iowrite(drvdata, CC_REG(HOST_IMR), val); -#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET -#ifdef DX_IRQ_DELAY +#ifdef CC_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET +#ifdef CC_IRQ_DELAY /* Set CC IRQ delay */ - cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), DX_IRQ_DELAY); + cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), CC_IRQ_DELAY); #endif if (cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) { dev_dbg(dev, "irq_delay=%d CC cycles\n", @@ -279,9 +279,9 @@ static int init_cc_resources(struct platform_device *plat_dev) /* Verify correct mapping */ signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE)); - if (signature_val != DX_DEV_SIGNATURE) { + if (signature_val != CC_DEV_SIGNATURE) { dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", - signature_val, (u32)DX_DEV_SIGNATURE); + signature_val, (u32)CC_DEV_SIGNATURE); rc = -EINVAL; goto post_clk_err; } @@ -507,9 +507,9 @@ static const struct dev_pm_ops arm_cc7x_driver_pm = { #endif #if defined(CONFIG_PM) -#define DX_DRIVER_RUNTIME_PM (&arm_cc7x_driver_pm) +#define CC_DRIVER_RUNTIME_PM (&arm_cc7x_driver_pm) #else -#define DX_DRIVER_RUNTIME_PM NULL +#define CC_DRIVER_RUNTIME_PM NULL #endif #ifdef CONFIG_OF @@ -526,7 +526,7 @@ static struct platform_driver cc7x_driver = { #ifdef CONFIG_OF .of_match_table = arm_cc7x_dev_of_match, #endif - .pm = DX_DRIVER_RUNTIME_PM, + .pm = CC_DRIVER_RUNTIME_PM, }, .probe = cc7x_probe, .remove = cc7x_remove, diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index 3d4513b..4d94a06 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -42,7 +42,7 @@ /* Registers definitions from shared/hw/ree_include */ #include "dx_host.h" #include "dx_reg_common.h" -#define CC_SUPPORT_SHA DX_DEV_SHA_MAX +#define CC_SUPPORT_SHA CC_DEV_SHA_MAX #include "cc_crypto_ctx.h" #include "ssi_sysfs.h" #include "hash_defs.h" @@ -54,24 +54,24 @@ #define CC_DEV_NAME_STR "cc715ree" #define CC_COHERENT_CACHE_PARAMS 0xEEE -#define CC_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ - (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ - (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ - (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT)) +#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ + (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ + (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ + (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT)) -#define CC_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) +#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) -#define CC_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) +#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) -#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ - DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ - DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) +#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \ + CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ + CC_AXIM_MON_COMP_VALUE_BIT_SHIFT) /* Register name mangling macro */ -#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET +#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET /* TEE FIPS status interrupt */ -#define CC_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT) +#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT) #define CC_CRA_PRIO 3000 @@ -169,7 +169,7 @@ static inline struct device *drvdata_to_dev(struct ssi_drvdata *drvdata) return &drvdata->plat_dev->dev; } -#ifdef DX_DUMP_BYTES +#ifdef CC_DUMP_BYTES void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); #else diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 7458c24..5a041bb 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -53,7 +53,7 @@ static const u32 sha224_init[] = { static const u32 sha256_init[] = { SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4, SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 }; -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) static const u32 digest_len_sha512_init[] = { 0x00000080, 0x00000000, 0x00000000, 0x00000000 }; static const u64 sha384_init[] = { @@ -209,7 +209,7 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state, } else { /*sha*/ memcpy(state->digest_buff, ctx->digest_buff, ctx->inter_digestsize); -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) if (ctx->hash_mode == DRV_HASH_SHA512 || ctx->hash_mode == DRV_HASH_SHA384) memcpy(state->digest_bytes_len, @@ -1839,7 +1839,7 @@ static struct cc_hash_template driver_hash[] = { .hw_mode = DRV_HASH_HW_SHA256, .inter_digestsize = SHA256_DIGEST_SIZE, }, -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) { .name = "sha384", .driver_name = "sha384-dx", @@ -2013,7 +2013,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata) struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; struct device *dev = drvdata_to_dev(drvdata); int rc = 0; -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) int i; #endif @@ -2028,7 +2028,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata) sram_buff_ofs += sizeof(digest_len_init); larval_seq_len = 0; -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) /* Copy-to-sram digest-len for sha384/512 */ cc_set_sram_desc(digest_len_sha512_init, sram_buff_ofs, ARRAY_SIZE(digest_len_sha512_init), @@ -2081,7 +2081,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata) sram_buff_ofs += sizeof(sha256_init); larval_seq_len = 0; -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) /* We are forced to swap each double-word larval before copying to * sram */ @@ -2142,7 +2142,7 @@ int cc_hash_alloc(struct ssi_drvdata *drvdata) drvdata->hash_handle = hash_handle; sram_size_to_alloc = sizeof(digest_len_init) + -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) sizeof(digest_len_sha512_init) + sizeof(sha384_init) + sizeof(sha512_init) + @@ -2413,7 +2413,7 @@ ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) sizeof(md5_init) + sizeof(sha1_init) + sizeof(sha224_init)); -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) case DRV_HASH_SHA384: return (hash_handle->larval_digest_sram_addr + sizeof(md5_init) + @@ -2449,7 +2449,7 @@ cc_digest_len_addr(void *drvdata, u32 mode) case DRV_HASH_SHA256: case DRV_HASH_MD5: return digest_len_addr; -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) case DRV_HASH_SHA384: case DRV_HASH_SHA512: return digest_len_addr + sizeof(digest_len_init); diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index 19fc4cf..9d1af96 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -25,7 +25,7 @@ #define HMAC_IPAD_CONST 0x36363636 #define HMAC_OPAD_CONST 0x5C5C5C5C -#if (DX_DEV_SHA_MAX > 256) +#if (CC_DEV_SHA_MAX > 256) #define HASH_LEN_SIZE 16 #define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 436e035..f1356d1 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -179,7 +179,7 @@ static void enqueue_seq(void __iomem *cc_base, struct cc_hw_desc seq[], for (i = 0; i < seq_len; i++) { for (w = 0; w <= 5; w++) writel_relaxed(seq[i].word[w], reg); -#ifdef DX_DUMP_DESCS +#ifdef CC_DUMP_DESCS dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", i, seq[i].word[0], seq[i].word[1], seq[i].word[2], seq[i].word[3], seq[i].word[4], seq[i].word[5]); diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c index 08858a4..6b11a72 100644 --- a/drivers/staging/ccree/ssi_sysfs.c +++ b/drivers/staging/ccree/ssi_sysfs.c @@ -34,23 +34,23 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj, register_value = cc_ioread(drvdata, CC_REG(HOST_SIGNATURE)); offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_SIGNATURE ", - DX_HOST_SIGNATURE_REG_OFFSET, register_value); + CC_HOST_SIGNATURE_REG_OFFSET, register_value); register_value = cc_ioread(drvdata, CC_REG(HOST_IRR)); offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_IRR ", - DX_HOST_IRR_REG_OFFSET, register_value); + CC_HOST_IRR_REG_OFFSET, register_value); register_value = cc_ioread(drvdata, CC_REG(HOST_POWER_DOWN_EN)); offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_POWER_DOWN_EN ", - DX_HOST_POWER_DOWN_EN_REG_OFFSET, register_value); + CC_HOST_POWER_DOWN_EN_REG_OFFSET, register_value); register_value = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "AXIM_MON_ERR ", - DX_AXIM_MON_ERR_REG_OFFSET, register_value); + CC_AXIM_MON_ERR_REG_OFFSET, register_value); register_value = cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "DSCRPTR_QUEUE_CONTENT", - DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET, + CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET, register_value); return offset; } From patchwork Tue Dec 12 14:53:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121541 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4224768qgn; Tue, 12 Dec 2017 06:56:30 -0800 (PST) X-Google-Smtp-Source: ACJfBouUFCOCLe3mKe+qgRCRfoUAZv+BPkDAhmLxzlenK+MkOTYqkGXSHkYFS25Mf794asa/uuZ2 X-Received: by 10.98.8.67 with SMTP id c64mr2603357pfd.50.1513090590844; Tue, 12 Dec 2017 06:56:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090590; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id u190si11570761pgb.657.2017.12.12.06.56.30; Tue, 12 Dec 2017 06:56:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753049AbdLLO43 (ORCPT + 1 other); Tue, 12 Dec 2017 09:56:29 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45236 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753038AbdLLO4Y (ORCPT ); Tue, 12 Dec 2017 09:56:24 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 64C551529; Tue, 12 Dec 2017 06:56:24 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5BE23F318; Tue, 12 Dec 2017 06:56:21 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 21/24] staging: ccree: fix buf mgr naming convention Date: Tue, 12 Dec 2017 14:53:07 +0000 Message-Id: <1513090395-7938-22-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The buffer manager files were using a func naming convention which was inconsistent (ssi vs. cc) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_buffer_mgr.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 8649bcb..6846d93 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -413,11 +413,9 @@ static int cc_map_sg(struct device *dev, struct scatterlist *sg, } static int -ssi_aead_handle_config_buf(struct device *dev, - struct aead_req_ctx *areq_ctx, - u8 *config_data, - struct buffer_array *sg_data, - unsigned int assoclen) +cc_set_aead_conf_buf(struct device *dev, struct aead_req_ctx *areq_ctx, + u8 *config_data, struct buffer_array *sg_data, + unsigned int assoclen) { dev_dbg(dev, " handle additional data config set to DLLI\n"); /* create sg for the current buffer */ @@ -441,10 +439,9 @@ ssi_aead_handle_config_buf(struct device *dev, return 0; } -static int ssi_ahash_handle_curr_buf(struct device *dev, - struct ahash_req_ctx *areq_ctx, - u8 *curr_buff, u32 curr_buff_cnt, - struct buffer_array *sg_data) +static int cc_set_hash_buf(struct device *dev, struct ahash_req_ctx *areq_ctx, + u8 *curr_buff, u32 curr_buff_cnt, + struct buffer_array *sg_data) { dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt); /* create sg for the current buffer */ @@ -1259,9 +1256,8 @@ int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req) } areq_ctx->ccm_iv0_dma_addr = dma_addr; - if (ssi_aead_handle_config_buf(dev, areq_ctx, - areq_ctx->ccm_config, &sg_data, - req->assoclen)) { + if (cc_set_aead_conf_buf(dev, areq_ctx, areq_ctx->ccm_config, + &sg_data, req->assoclen)) { rc = -ENOMEM; goto aead_map_failure; } @@ -1432,8 +1428,8 @@ int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx, /*TODO: copy data in case that buffer is enough for operation */ /* map the previous buffer */ if (*curr_buff_cnt) { - if (ssi_ahash_handle_curr_buf(dev, areq_ctx, curr_buff, - *curr_buff_cnt, &sg_data)) { + if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt, + &sg_data)) { return -ENOMEM; } } @@ -1545,8 +1541,8 @@ int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx, } if (*curr_buff_cnt) { - if (ssi_ahash_handle_curr_buf(dev, areq_ctx, curr_buff, - *curr_buff_cnt, &sg_data)) { + if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt, + &sg_data)) { return -ENOMEM; } /* change the buffer index for next operation */ From patchwork Tue Dec 12 14:53:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121544 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4225895qgn; Tue, 12 Dec 2017 06:57:31 -0800 (PST) X-Google-Smtp-Source: ACJfBovL4TI+1o/7YJOmYq6MUaYjQSXmTuLfbG/+A+2akj69wMy3PNmHfollG+hbZh08AjCA7sdo X-Received: by 10.101.101.131 with SMTP id u3mr2281290pgv.76.1513090651512; Tue, 12 Dec 2017 06:57:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090651; cv=none; d=google.com; s=arc-20160816; b=edFIFmbweEcPzKY7eElBzxpIJCgUTSk18zQrjDJ52ctdYl6hrBW0R7RTVpZSgg57Z0 /kxxEIsH3DT3pzzqWkItuWrYQyYePZfLCLtDa7wc3SbKE/BQJD8jZsc+Rx8but6H0HDk Cv22w6oH/2LWX5MFB/UJuEkO9tw4CyFp6X2L+F3cu2Wj2QTH8OP/Dlxlay1Up3zgD4ku GVsNT0NMr10vv9KMgt5C1x6foS2xPxVjftbCRFHzcfcOElM4LZo2WwXVzd1mAI2wKAEp BGl0PGPB6v1IJgZ2ZN2dBimbd3MxwkNi+z6ceJQw6JppfuJ4NKSFRHig6S3SZiSrRqDS P1Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=fES40cvTeUnox1470To/Q41Pf+UuW0dZXvuxlqFClPI=; b=hW71feSADEToLbLwlGk9quMW2uu18SgcYMGm7HrnbpKRkgaxxchSOtw+hp/APzIVKn t2L6dBmhJtCqAYwIXBHWmaPXknXuWnYdWnNvhSe0Ig8PfG+KUCZhkU/aDbXqm7dG4nHk zrmm+FKcBJvm+w7sn3+Bcn5pIst/iHK6vNRGcBm0xBL+vwkJh8M2Xyqje37rCXITAtTt HgzECqyy2IdUvIl7Nqkl6+klaJQkGE9n/dwnflyQqRV4lyBGMnUO+FcMLq5OKUWnu58U lm+HKvnKiEEOTngDpzu13PjOG1vFQmQngCYK4xb05qUOwHAK3Fzy2hwsHqNEHkbsW6HS +6ow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si12955139pfe.339.2017.12.12.06.57.31; Tue, 12 Dec 2017 06:57:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752486AbdLLO53 (ORCPT + 1 other); Tue, 12 Dec 2017 09:57:29 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45246 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752745AbdLLO4d (ORCPT ); Tue, 12 Dec 2017 09:56:33 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19E101529; Tue, 12 Dec 2017 06:56:33 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C1F93F318; Tue, 12 Dec 2017 06:56:30 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 22/24] staging: ccree: fix sram mgr naming convention Date: Tue, 12 Dec 2017 14:53:08 +0000 Message-Id: <1513090395-7938-23-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The SRAM manager files were using a naming convention which was inconsistent (ssi vs. cc) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_driver.c | 8 ++++---- drivers/staging/ccree/ssi_sram_mgr.c | 18 +++++++++--------- drivers/staging/ccree/ssi_sram_mgr.h | 4 ++-- 3 files changed, 15 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 3f02ceb..6e7a396 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -312,9 +312,9 @@ static int init_cc_resources(struct platform_device *plat_dev) dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc); goto post_sysfs_err; } - rc = ssi_sram_mgr_init(new_drvdata); + rc = cc_sram_mgr_init(new_drvdata); if (rc) { - dev_err(dev, "ssi_sram_mgr_init failed\n"); + dev_err(dev, "cc_sram_mgr_init failed\n"); goto post_fips_init_err; } @@ -391,7 +391,7 @@ static int init_cc_resources(struct platform_device *plat_dev) post_req_mgr_err: cc_req_mgr_fini(new_drvdata); post_sram_mgr_err: - ssi_sram_mgr_fini(new_drvdata); + cc_sram_mgr_fini(new_drvdata); post_fips_init_err: ssi_fips_fini(new_drvdata); post_sysfs_err: @@ -423,7 +423,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) cc_pm_fini(drvdata); cc_buffer_mgr_fini(drvdata); cc_req_mgr_fini(drvdata); - ssi_sram_mgr_fini(drvdata); + cc_sram_mgr_fini(drvdata); ssi_fips_fini(drvdata); #ifdef ENABLE_CC_SYSFS ssi_sysfs_fini(); diff --git a/drivers/staging/ccree/ssi_sram_mgr.c b/drivers/staging/ccree/ssi_sram_mgr.c index 5d83af5..b664e9b 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.c +++ b/drivers/staging/ccree/ssi_sram_mgr.c @@ -18,37 +18,37 @@ #include "ssi_sram_mgr.h" /** - * struct ssi_sram_mgr_ctx -Internal RAM context manager + * struct cc_sram_ctx -Internal RAM context manager * @sram_free_offset: the offset to the non-allocated area */ -struct ssi_sram_mgr_ctx { +struct cc_sram_ctx { cc_sram_addr_t sram_free_offset; }; /** - * ssi_sram_mgr_fini() - Cleanup SRAM pool. + * cc_sram_mgr_fini() - Cleanup SRAM pool. * * @drvdata: Associated device driver context */ -void ssi_sram_mgr_fini(struct cc_drvdata *drvdata) +void cc_sram_mgr_fini(struct cc_drvdata *drvdata) { - struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; + struct cc_sram_ctx *smgr_ctx = drvdata->sram_mgr_handle; /* Free "this" context */ if (smgr_ctx) { - memset(smgr_ctx, 0, sizeof(struct ssi_sram_mgr_ctx)); + memset(smgr_ctx, 0, sizeof(struct cc_sram_ctx)); kfree(smgr_ctx); } } /** - * ssi_sram_mgr_init() - Initializes SRAM pool. + * cc_sram_mgr_init() - Initializes SRAM pool. * The pool starts right at the beginning of SRAM. * Returns zero for success, negative value otherwise. * * @drvdata: Associated device driver context */ -int ssi_sram_mgr_init(struct cc_drvdata *drvdata) +int cc_sram_mgr_init(struct cc_drvdata *drvdata) { /* Allocate "this" context */ drvdata->sram_mgr_handle = kzalloc(sizeof(*drvdata->sram_mgr_handle), @@ -71,7 +71,7 @@ int ssi_sram_mgr_init(struct cc_drvdata *drvdata) */ cc_sram_addr_t cc_sram_alloc(struct cc_drvdata *drvdata, u32 size) { - struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; + struct cc_sram_ctx *smgr_ctx = drvdata->sram_mgr_handle; struct device *dev = drvdata_to_dev(drvdata); cc_sram_addr_t p; diff --git a/drivers/staging/ccree/ssi_sram_mgr.h b/drivers/staging/ccree/ssi_sram_mgr.h index 52f5288..181968a 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.h +++ b/drivers/staging/ccree/ssi_sram_mgr.h @@ -40,14 +40,14 @@ typedef u64 cc_sram_addr_t; * * \return int Zero for success, negative value otherwise. */ -int ssi_sram_mgr_init(struct cc_drvdata *drvdata); +int cc_sram_mgr_init(struct cc_drvdata *drvdata); /*! * Uninits SRAM pool. * * \param drvdata */ -void ssi_sram_mgr_fini(struct cc_drvdata *drvdata); +void cc_sram_mgr_fini(struct cc_drvdata *drvdata); /*! * Allocated buffer from SRAM pool. From patchwork Tue Dec 12 14:53:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121543 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4225208qgn; Tue, 12 Dec 2017 06:56:52 -0800 (PST) X-Google-Smtp-Source: ACJfBos1A2AJ5hlcf+jMExY+kJY9H8L/x/zsgegB7X196udQpucJqqKNZXfkOSfqNOJyTw8VqiiJ X-Received: by 10.84.241.15 with SMTP id a15mr2589255pll.103.1513090612462; Tue, 12 Dec 2017 06:56:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090612; cv=none; d=google.com; s=arc-20160816; b=o6Hm7rMfFhlCpuw/FD/D24IvcP8P1ZyZiJSg7nmPNwkqSpfKdgI35msYh+nS89baWA KB/OIIrU+6yZA9n9ox/COb2P+0hJuh2eMeq3XAhatzanYoKv+goari42/TAMO8AEyJky qnpGVzPWhKUXFbYrtKYfr6jdD6ZzNCWEgrzhxKeCSGopdUhb0Dsu0aDQl6qtHYflKxy5 zcpdVJP+ichp9LCW+E3SDM/JqUoQN+YWW4YNVA1zsq+liGU/lp/iVu/kfFPuF+sOgMrO 0rr72RgoNWep8P8FKajkusjO4MSvweNx8ShGECtZPw3Tt89QqHryXUoj7ZWTL98D05pC HL7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=NFhnh2E1A/dZu3Yx7neVzozuk1cRQxcmsmk2CF+YJ4k=; b=qqQIN9hekTNu9mXUHoFiawvLkdUjDts+K9zZBjIfGjT4NxTppQWeCdFN8iiO809Iwa 8anOHI36fnlfj+bklRYGtXwjNlcCPt/T55wskuHMCq0Zt1EZB9LhG6Hfi6Ju8gGSjBPF m5C5WTDquD0lkgXbz9tnIgwAF9OOm/LfMY26vTWjYDkGGHCS1gf4E2T8CpgcuddarCAi 7wlSMaS2eblNyJ3b/sIfxig4dq9gEmXZgWCvrY/TqfIYvFUCTESPE+MMzkQdrtWJENtX iB2NcaGYU92IG2lqcwfYA0N8HjDrH8fsxE4DDBPFZ9uBMtVArVuL5AIQ+BdEcnrND1Wp tRgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d3si11534267pgq.709.2017.12.12.06.56.52; Tue, 12 Dec 2017 06:56:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752711AbdLLO4u (ORCPT + 1 other); Tue, 12 Dec 2017 09:56:50 -0500 Received: from foss.arm.com ([217.140.101.70]:45266 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752306AbdLLO4s (ORCPT ); Tue, 12 Dec 2017 09:56:48 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93DA51529; Tue, 12 Dec 2017 06:56:48 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E04043F318; Tue, 12 Dec 2017 06:56:45 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 24/24] staging: ccree: fix FIPS mgr naming convention Date: Tue, 12 Dec 2017 14:53:10 +0000 Message-Id: <1513090395-7938-25-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The FIPS manager files were using a naming convention which was inconsistent (ssi vs. cc) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_driver.c | 6 +++--- drivers/staging/ccree/ssi_fips.c | 4 ++-- drivers/staging/ccree/ssi_fips.h | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 6e7a396..28cfbb4 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -307,7 +307,7 @@ static int init_cc_resources(struct platform_device *plat_dev) } #endif - rc = ssi_fips_init(new_drvdata); + rc = cc_fips_init(new_drvdata); if (rc) { dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc); goto post_sysfs_err; @@ -393,7 +393,7 @@ static int init_cc_resources(struct platform_device *plat_dev) post_sram_mgr_err: cc_sram_mgr_fini(new_drvdata); post_fips_init_err: - ssi_fips_fini(new_drvdata); + cc_fips_fini(new_drvdata); post_sysfs_err: #ifdef ENABLE_CC_SYSFS ssi_sysfs_fini(); @@ -424,7 +424,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) cc_buffer_mgr_fini(drvdata); cc_req_mgr_fini(drvdata); cc_sram_mgr_fini(drvdata); - ssi_fips_fini(drvdata); + cc_fips_fini(drvdata); #ifdef ENABLE_CC_SYSFS ssi_sysfs_fini(); #endif diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c index 036215f..a1d7782 100644 --- a/drivers/staging/ccree/ssi_fips.c +++ b/drivers/staging/ccree/ssi_fips.c @@ -51,7 +51,7 @@ void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool status) cc_iowrite(drvdata, CC_REG(HOST_GPR0), val); } -void ssi_fips_fini(struct cc_drvdata *drvdata) +void cc_fips_fini(struct cc_drvdata *drvdata) { struct cc_fips_handle *fips_h = drvdata->fips_handle; @@ -105,7 +105,7 @@ static void fips_dsr(unsigned long devarg) } /* The function called once at driver entry point .*/ -int ssi_fips_init(struct cc_drvdata *p_drvdata) +int cc_fips_init(struct cc_drvdata *p_drvdata) { struct cc_fips_handle *fips_h; struct device *dev = drvdata_to_dev(p_drvdata); diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h index 5eed9f6..8321dde 100644 --- a/drivers/staging/ccree/ssi_fips.h +++ b/drivers/staging/ccree/ssi_fips.h @@ -27,19 +27,19 @@ enum cc_fips_status { CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX }; -int ssi_fips_init(struct cc_drvdata *p_drvdata); -void ssi_fips_fini(struct cc_drvdata *drvdata); +int cc_fips_init(struct cc_drvdata *p_drvdata); +void cc_fips_fini(struct cc_drvdata *drvdata); void fips_handler(struct cc_drvdata *drvdata); void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool ok); #else /* CONFIG_CRYPTO_FIPS */ -static inline int ssi_fips_init(struct cc_drvdata *p_drvdata) +static inline int cc_fips_init(struct cc_drvdata *p_drvdata) { return 0; } -static inline void ssi_fips_fini(struct cc_drvdata *drvdata) {} +static inline void cc_fips_fini(struct cc_drvdata *drvdata) {} static inline void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool ok) {} static inline void fips_handler(struct cc_drvdata *drvdata) {}