From patchwork Mon Dec 11 12:46:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 121390 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2744117qgn; Mon, 11 Dec 2017 04:47:01 -0800 (PST) X-Google-Smtp-Source: ACJfBotmCgy/ULS23siAhGgP+TcU42TSjevgga5ylznj5m+7SkUmRzWFuESK+lUdDubNmmhNJPbn X-Received: by 10.98.67.150 with SMTP id l22mr296345pfi.32.1512996421589; Mon, 11 Dec 2017 04:47:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512996421; cv=none; d=google.com; s=arc-20160816; b=0koNLWkqDR+oBk/oXhlqpss9JWP9Aul5jpl4mbLcWt2OmahhaZmJLHd6q3gzuNRJiq Z+F/OuyZJUt4DIKi9W769cRB24d5vWC5MQaTafFX77vnDU7+5zPOE02moTJV9d2Nz431 JuNnvSU5Z9jXYXeTMVoVKf7QFAfOpOCkWCbvwqxWVrXhTJ0otvxPKVyRIM3K7unkDOZ9 1NQFdlge2jED/w20urFTWIOazRDF3DTLC9WjlTyGnj4nLAbnEVVJsStqE4fZDMkxKy+2 RAEXVU/LtjY/jwl6/SwXbzPLCKxLU8UQymX3S+2LQGRVyjk1o1jKT68qU6CztfeB6SaZ Xjig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=8N+sBzOvj01P23QLIYWZbYy31O/DzaedQGATXWisLtg=; b=RWRi7fccAfH4AurZkOmyQJyvnsMriIQFdu8tmJdt6DdImrH1JpJvxPRNPFYO5oFqX2 C39NsCHJbNmiU0lLhZ72cUKvYHN6pARLStEgcBIlIcqq6Vw/mOvfkQa1q6x8UWuzFkv9 8moEEHXFfo1dbRTtKJC/HZP8W3O+Hhj9CCXYzUZT+eqKrnYGYE3xDCOQA1ud3551L0bt 7Cbzu9ir+pHhkPbpib0qiFd21mBA25V6C79hRYs3gAoh8hSsHyKFm+/yzdI2mZkBzSBU GteXzN7DrVLvyHVovoSz7BckEfdcJNwbcr6CgEC+4IQR0o0NEvkNysgUcSoR5TFce39z oMjQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o3si9891056pld.65.2017.12.11.04.47.01; Mon, 11 Dec 2017 04:47:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752836AbdLKMrA (ORCPT + 24 others); Mon, 11 Dec 2017 07:47:00 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:65475 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751347AbdLKMq6 (ORCPT ); Mon, 11 Dec 2017 07:46:58 -0500 Received: from wuerfel.lan ([149.172.96.106]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.129]) with ESMTPA (Nemesis) id 0Lawnp-1emwmr2JMP-00kfPi; Mon, 11 Dec 2017 13:46:44 +0100 From: Arnd Bergmann To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie Cc: Arnd Bergmann , Chris Wilson , =?utf-8?q?Ville_Syrj=C3=A4l?= =?utf-8?b?w6Q=?= , Imre Deak , Lionel Landwerlin , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] [v2] drm/i915: use static const array for PICK macro Date: Mon, 11 Dec 2017 13:46:22 +0100 Message-Id: <20171211124640.1010542-1-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 X-Provags-ID: V03:K0:pnv78sIB6QAnlBgITnBaeAe1N4jZX/7NxZCxZNyxm1joTz8Kn/v LSPrAMXLOg3YRME2w8NlhDzXAw0il8i9N5TdOsVhd40/Hb0wf7TEvB94y6wmZax5cUwYoHg ncVK60KO2KGpOg/NK+UM2K7pn0hFUOpqfKft69iq/jwdj3w2TIpNzFqm2G1j7dVnMMStij1 lGqAhg3DJdx3a9oQuZoAw== X-UI-Out-Filterresults: notjunk:1; V01:K0:i8y8OF2yMJk=:jLDe+5CsQsK21sLrBgXeXI jCfuZiBAk43VKjH5vjy6pFH/nO3XW6NrjH74txpVZQyuYFC3oo0ChdIqsRg7mOQ4xs4qXXW6m 5l29XIZdrJg93YEHmGg+OywHF7MAM4nGPDFDlz76AvvUveWUtyjxff8QjPoZ9MQ+XfpKgxiFS 7oVaa3UjcBPphJHhk7DI5MVUIQDP+ufakuFR+YsuX6e1tQIRrrG1/mYErxgsj5XfcWZzUH5nX MTE/vTm0ypJ+iMe4ZupMLYQElZ7k2fh5dSYys7iUh+BH3UdCbeo8goPiaznJJUIL7IcFdGOuY b6REsIM6Z99s+KfhH2l/8MdnqfIBSTN9ACpb5kGWMS8oqtQ2UhLw1o3e+EYWle8P4wbBF0j4+ QaEiJk1wF7Drn8htWEHOxC5Ot9perVW9IW7oI6i+5CYpTRqLOhWBfZQUzPX2MY5wN+pl8IfaU ORaT7jIC26Mlgrnv0P/3px+67Fmw/ZTmLpol4Z7uszO6Ffp52ohGg4TfBXORa9igHY21E+JEW hq1tc1g7D+QP/bpwIlGWEZRgtTi/pDQTBCtGuW7dgjLUQ4nx/+9rg3CWDEQe+AXQpyFPOBhZK SoYtAfnUmDvjEOQ3ewUFRhRxjjpl+5/67/vLvEp/8Xl05xldcOGaHOvTfBYOx6P0xA4uTdyke EkXmT0CcffD9k9GQQt7VV1zCdDi8gk5p6fRova1Ci8dua1S6o/PPl8hJs2WDFgsQzAUxUbQWc /7Zt2pRfqg/t2EYGF1Fw+B596SJtf4uVQ8HUJw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The varargs macro trick in _PIPE3/_PHY3/_PORT3 was meant as an optimization to shrink the i915 kernel module by around 1000 bytes. However, the downside is a size regression with CONFIG_KASAN, as I found from stack size warnings with gcc-7.0.1: before: drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_get_hw_state': drivers/gpu/drm/i915/intel_dpll_mgr.c:1644:1: error: the frame size of 176 bytes is larger than 100 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_enable': drivers/gpu/drm/i915/intel_dpll_mgr.c:1548:1: error: the frame size of 224 bytes is larger than 100 bytes [-Werror=frame-larger-than=] after: drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_get_hw_state': drivers/gpu/drm/i915/intel_dpll_mgr.c:1644:1: error: the frame size of 1016 bytes is larger than 1000 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_enable': drivers/gpu/drm/i915/intel_dpll_mgr.c:1548:1: error: the frame size of 1960 bytes is larger than 1000 bytes [-Werror=frame-larger-than=] I also checked the module sizes and got with gcc-7.0.1 original: text data bss dec hex filename 2380830 1155436 4448 3540714 3606ea drivers/gpu/drm/i915/i915-kasan.o 1298054 543692 2884 1844630 1c2596 drivers/gpu/drm/i915/i915-nokasan.o after ce64645d86ac: text data bss dec hex filename 2389515 1154476 4448 3548439 362517 drivers/gpu/drm/i915/i915-kasan.o 1299639 543692 2884 1846215 1c2bc7 drivers/gpu/drm/i915/i915-nokasan.o with this patch: text data bss dec hex filename 2381275 1163884 4448 3549607 3629a7 drivers/gpu/drm/i915/i915-kasan.o 1296038 543692 2884 1842614 1c1db6 drivers/gpu/drm/i915/i915-nokasan.o Actually showing a code size growth in .text both with and without kasan, and my version gets most of it back at the expense of larger .data when kasan is enabled. Fixes: ce64645d86ac ("drm/i915: use variadic macros and arrays to choose port/pipe based registers") Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80114 Link: https://lkml.org/lkml/2017/3/20/1022 Cc: Jani Nikula Signed-off-by: Arnd Bergmann --- v2: rebased after a1986f4174a4 ("drm/i915: Remove unnecessary PORT3 definition.") --- drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 2.9.0 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bf043c1c2e..36f4408503e1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -139,7 +139,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); } -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) +#define _PICK(__index, ...) ({static const u32 __arr[] = { __VA_ARGS__ }; __arr[__index];}) #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) @@ -3097,10 +3097,10 @@ enum i915_power_well_id { /* * Clock control & power management */ -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) +#define _DPLL_A 0x6014 +#define _DPLL_B 0x6018 +#define _CHV_DPLL_C 0x6030 +#define DPLL(pipe) _MMIO(dev_priv->info.display_mmio_offset + _PICK((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)) #define VGA0 _MMIO(0x6000) #define VGA1 _MMIO(0x6004) @@ -3196,10 +3196,10 @@ enum i915_power_well_id { #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) +#define _DPLL_A_MD 0x601c +#define _DPLL_B_MD 0x6020 +#define _CHV_DPLL_C_MD 0x603c +#define DPLL_MD(pipe) _MMIO(dev_priv->info.display_mmio_offset + _PICK((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)) /* * UDI pixel divider, controlling how many pixels are stuffed into a packet.