From patchwork Fri Dec 8 11:32:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121150 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp539289qgn; Fri, 8 Dec 2017 03:33:15 -0800 (PST) X-Google-Smtp-Source: AGs4zMYPyu90Htd7nbCyeFq5RVw83xgPgO3i5ba1+lAaMJbTkgR6KhEA66N165mYYuSdmB8RoaW7 X-Received: by 10.99.49.81 with SMTP id x78mr30137907pgx.35.1512732795060; Fri, 08 Dec 2017 03:33:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512732795; cv=none; d=google.com; s=arc-20160816; b=LObxwct+0AH8pFo1uJ5j5rGzuVK+HydkiDU2mumkO8b4mTG6dZWlJkrqxJaLO1Y1z+ AM5ZEQAk6usSsxBhV0u2LPz6RX4xOQTEQ+Aw3+vIspqY42cS66Qtd8YKEMQoQrTjqKwo TZfPAbZi0dPcsGnA0NfyVpnmPwGIKSl3t0k3UmT7ccJ0jwTMHTa+zp+56bW/BGmJm4vn /jYMEYnLTor9b6cHGo9xlVUBCAi0MuAYvRTTsDBvzSCK5fLwvS5lZUm70yuo2STL0MYU 4+gSj3fgtCWUeGQNwUeNt9kHrSLdePS/cK033mIo29vq6LXLdYiIZ+13yO1XDDiVyxwy e18A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4a2plB5Rk5rrQEGbVZXlJhM6CFtoUqcODETsJT3XjQo=; b=JSVftx74cZeKzNKBaOJGEkheOddhKdzH8ZP1e7V939P+GUSJ8p3IpBiwhKm6JKHUwS MKMiIDXUpK7ij5ZtoHexnag3dhZbNElVaOmcyX3yZFB3nFAvU41mRrhtLvVgzeKH2DTt yjo/k8EXaDa+PUGuU4Q9Kn/0ftIZdqckOjKG75NfijNri5laHlDBHTrJjcLbJZ52d0/z XHLa9SOCfUbg40wlMIMyMLYYCS1gCFAv3xmmAQP1AUTcOObd9B3UIOFarhYv4fd48Ur0 Snw1JJNBNGMeKwR2gZuqNOHUdgQ0pBYkLIqc8OT90YicVrgRbZonGRaM8MJue8n73AEO CPPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dc9NBsY7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si5387943plg.3.2017.12.08.03.33.14; Fri, 08 Dec 2017 03:33:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dc9NBsY7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753382AbdLHLdK (ORCPT + 11 others); Fri, 8 Dec 2017 06:33:10 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35515 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753155AbdLHLdE (ORCPT ); Fri, 8 Dec 2017 06:33:04 -0500 Received: by mail-wm0-f65.google.com with SMTP id f9so2758474wmh.0 for ; Fri, 08 Dec 2017 03:33:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4a2plB5Rk5rrQEGbVZXlJhM6CFtoUqcODETsJT3XjQo=; b=Dc9NBsY7dG3/fv5b5cJf/P0kwRO8SLTTaYvYV5GZ4pVYztO1V53fKgqTF3fi/P+hYT OGs8aYGZpGz1Tp8bw7PfXLjtiv2tINhFLpzu4AEhNR+RopkqMHUISwD+QKMrHD8vNePl Ko//xJ9N+bl1fjssmTHmh0xCmmh9cSMyEjI/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4a2plB5Rk5rrQEGbVZXlJhM6CFtoUqcODETsJT3XjQo=; b=clVi09EEs9nKtgyQbY5LwgqF5wQfwilrQyARhPruc+ZYF5AaKvVydaLB5fgw9GfNm6 AU4IJg4YV4WQWq2DQ3shJ8JDBUCvkrEH1I/9/4Ova6lOKo2uWfhwonXCspRr/BrA1TNI IEWB9mCpb8BBBSe867oA5YPjRvKqt4KQ23Fz1ZHUijlCEjGi94TvwBV5m1C8fplK+a7c GTspzBO0bVNPnPEbeuQc0KagcrKqH+gbvmqli9OtFj7Hs5FfVykvnKHa8H6uy2ykqrmz sxKEHRu3HYePLJIOoT5aR4vOmX0hf1g0UChKHbgsf+H2FnS8hXPK5HU5sB8oG6ZFwJT+ x9jA== X-Gm-Message-State: AKGB3mJAF552bD/iGObB40kZMOdsmMAivRX9xXwQcfeRAvjzbBYFmDqT Vdx+uitzefofsRPevW1qGD8JNQ== X-Received: by 10.28.0.199 with SMTP id 190mr3853088wma.143.1512732782501; Fri, 08 Dec 2017 03:33:02 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.32.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:01 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 1/6] clocksource: stm32: convert driver to timer_of Date: Fri, 8 Dec 2017 12:32:45 +0100 Message-Id: <20171208113250.359-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard Convert driver to use timer_of helpers. This allow to remove custom proprietary structure. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 160 ++++++++++++++------------------------ 2 files changed, 58 insertions(+), 103 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c729a88007d0..28bc55951512 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -269,6 +269,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f2423789ba9..fc61fd18a182 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -17,6 +17,8 @@ #include #include +#include "timer-of.h" + #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 @@ -34,117 +36,84 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, base + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static int __init stm32_clockevent_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); + unsigned long max_delta; + int ret, bits, prescaler = 1; + struct timer_of *to; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; + to->clkevt.rating = 200; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; + + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; bits = 32; @@ -152,38 +121,23 @@ static int __init stm32_clockevent_init(struct device_node *np) prescaler = 1024; bits = 16; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_period(to), 0x1, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + node, bits); - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: +err: + kfree(to); return ret; } From patchwork Fri Dec 8 11:32:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121155 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp540459qgn; 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[209.132.180.67]) by mx.google.com with ESMTP id n10si4371376plp.158.2017.12.08.03.34.36; Fri, 08 Dec 2017 03:34:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZvLMQoqg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753843AbdLHLee (ORCPT + 11 others); Fri, 8 Dec 2017 06:34:34 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44061 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753141AbdLHLdG (ORCPT ); Fri, 8 Dec 2017 06:33:06 -0500 Received: by mail-wr0-f193.google.com with SMTP id l22so10511119wrc.11 for ; Fri, 08 Dec 2017 03:33:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KtaVjK3CJoXbgV1EFwf6ucQlBfpEMhp8d8d2kBoDcKg=; b=ZvLMQoqgcu2j40a3r5+xcWhqJyPN/jiHLhp9ogxxTjiitnXp2U565bU/j4q86V8nVt H07pRYS3HGtNJaT0ds238a9dR6yj0G7+CB0abT+EbLnfFSaX+lqwrk+r89A1lX4WS5mq HLjJ8UcsTSOcxSPJVz++SwG0KTkyWhln8kGG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KtaVjK3CJoXbgV1EFwf6ucQlBfpEMhp8d8d2kBoDcKg=; b=gEdywgVmXs98tfwX+uCbBAFrk0bY1VyAE2N9afgG6kJbyMGHk3MPxMOEbrII/3mhJM MzVHUBbUQS038ME5SQEOm0URo44eQ0d7EP9T7UuKJtnuIHILK3wUCyT8H8tTKtnkJv3v Hh5sZ+kLe9uTW7JKbwXsKQ6+MhG76Rlx1JdbZV5KFeKw0xjGUnVxPyKvPryhX86Wh89x 1fOHAWQAYqHZFNe+sZyXKNW9QfeL4ld/0sU+ZD8QM6IwBDHFNwOR5uRC+11IE6IpUPTG 1cW6kEdkHfYoZjsG88lf32JGjFBHUl3hXmBukiL+kvHzCT6//f5935tePL74NSrcDZtM 9G3A== X-Gm-Message-State: AJaThX76/BBuNGQNkI91pV3yhnuhiOThZuYgzFK5yCKRotSmC/QM8Fh7 cun/kCyKAKddeN2nG4piWcX4DQ== X-Received: by 10.223.201.138 with SMTP id f10mr27338458wrh.9.1512732785491; Fri, 08 Dec 2017 03:33:05 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:04 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 2/6] clocksource: stm32: increase min delta value Date: Fri, 8 Dec 2017 12:32:46 +0100 Message-Id: <20171208113250.359-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The CPU is a CortexM4 @ 200MHZ and the clocks driving the timers are at 90MHZ with a min delta at 1 you could have an interrupt each 0.01 ms which is really to much. By increase it to 0x60 it give more time (around 1 ms) to CPU to handle the interrupt. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index fc61fd18a182..a45f1f1cd040 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -36,6 +36,12 @@ #define TIM_EGR_UG BIT(0) +/* + * The clock driving the hardware is at 90MHZ with a MIN_DELTA + * at 0x60 it gives around 1 ms to the CPU to handle the interrupt + */ +#define MIN_DELTA 0x60 + static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); @@ -129,7 +135,8 @@ static int __init stm32_clockevent_init(struct device_node *node) writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x1, max_delta); + timer_of_period(to), + MIN_DELTA, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", node, bits); From patchwork Fri Dec 8 11:32:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121152 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp539443qgn; Fri, 8 Dec 2017 03:33:27 -0800 (PST) X-Google-Smtp-Source: AGs4zMYyAHarqJ94F/43OGpLc6aPOA0kyhD7zAg92J/cdILCNTwetpD/Var5CkZ2j91f2yUXChpN X-Received: by 10.101.101.216 with SMTP id y24mr30468263pgv.236.1512732807129; Fri, 08 Dec 2017 03:33:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512732807; cv=none; d=google.com; s=arc-20160816; b=VNxbwxRyxuFizW9vucaPKjfxCrcDmpzIARdIFpPQ6bsOSmGRbeH/lyanAT8PwJxA5r zFZeKRs2AN3WLAXLRKEklkeA3md49jTUmkzDjndxkyUWTzdWVjLymnUnRdH2M1YAXP0S mMpQFsARCWMYd+w/4CjCglwm/OCM/8quv0nL9n3BKxR7IduQhI9DtbSznH8bRMVONJ42 ekKMhfjo7X/SAVO0fI351FbkGT6D6/IqdtUhlKjxhtbKCAxNptyP7d17ZJUvMpws4gML MEHJ1/q6JiCEgC/KMhdYMVqTgKXJ+fPvL16tQ6SvQTd52MjSA31LgXNE5czDwwbR5OUP uPuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=sKZm9pfhB+h3nM3y1l/M76biPNjJ7fAUHeUwj+MDg7ayYQGcBzRpTjVSkT/Q9RbJlf 7j4wJekl94O5n6SpivXsoD2wy16lmYg7vjEOl4hEUAk8Gtpqr5O0XbRviEKKbaRbUTKc z4qsAKN8pCXXffyAmr9aYCVl1MmiFKuzUYVa5OqJ55YlAH7EYlqWxizi0aMjMVKn55sf tQ6fvjwWA6xdvHdkZwBGFkqVpNV6ibneEHSlympQbatCZ6p9Qis6ALbCKeTBVkNzRLru er89JBtgDbJ1gW++mGGUBhNFu3+5wObrUPH8yuPzl5cwOGF+QJklR/OoM2JQN3GqpdfM EDHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gmUiiUeH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si5387943plg.3.2017.12.08.03.33.26; Fri, 08 Dec 2017 03:33:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gmUiiUeH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753550AbdLHLdW (ORCPT + 11 others); Fri, 8 Dec 2017 06:33:22 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34308 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753414AbdLHLdM (ORCPT ); Fri, 8 Dec 2017 06:33:12 -0500 Received: by mail-wr0-f195.google.com with SMTP id y21so10535896wrc.1 for ; Fri, 08 Dec 2017 03:33:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=gmUiiUeHGlqBippk7MhztImH39/I5Ji+9CcLwJ2uWIeGBOEqoNG6Bu/VtJIiQkpG75 jgRkfKNaDr/FW5q0pQaAS50hVW00f4KhvBMc3wYv+Ke/b6TphmQGGukHLGovxjKtOEfu f8hXipOYqljtnY4ZMs+9HSQzsyn8YD2t93/0E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=ngLxkCKPCpF+h4cvkSHG2r+V0WaL9J4KRuhYkuGMUILMy2ofEfsvvOG9B+7tjBQZJF FxR1J8OYJtaHH2aISJ/WtRXVIFc6dJPEf3F34n3+8M9ikQ62Ewwi+kakleu+QOR2wpES WSNYli6Ut8ILe4B8z8PCtoZ4BV2Dge8p09CVb+vI0Lmnh2Cp5H8fTK2qEaGA5lKm4bJC VtRTdnIDA0Lm7CF9OvNEV4MIdMphYjNCLwIxxFn6g7BmAlpwaAW2wvvrW/V1aRIzG4sB HU9FpQPXcVUdCTmlsb+RpvR0nb+eF3lVEqFiCe+vfqWMA/8uQz0fCIIoIsT1HDFWzGp+ W5hw== X-Gm-Message-State: AJaThX7nysee5JknLZSZyrqCTcO9yXhtRGUibgXgVUUpghNAYbc17IGO wbtRb6k4FiHkHYF3Ew36aU9pvw== X-Received: by 10.223.155.131 with SMTP id d3mr28783951wrc.29.1512732791395; Fri, 08 Dec 2017 03:33:11 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:10 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard , Benjamin Gaignard Subject: [PATCH v9 4/6] clocksource: stm32: add clocksource support Date: Fri, 8 Dec 2017 12:32:48 +0100 Message-Id: <20171208113250.359-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The stm32 timer hardware is currently only used as a clock event device, but it can be utilized as a clocksource as well. Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 707808d91bf0..c9aed2314194 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -46,28 +48,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; + + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -79,6 +97,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; @@ -89,7 +112,48 @@ static bool stm32_timer_is_32bits(struct timer_of *to) return readl_relaxed(timer_of_base(to) + TIM_ARR) == ~0UL; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), MIN_DELTA, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; struct timer_of *to; @@ -100,12 +164,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -128,16 +193,11 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), - MIN_DELTA, ~0U); + stm32_clockevent_init(to); return 0; @@ -148,4 +208,4 @@ static int __init stm32_clockevent_init(struct device_node *node) return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Fri Dec 8 11:32:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121154 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp540154qgn; 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Fri, 08 Dec 2017 03:33:15 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:14 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 5/6] clocksource: stm32: Update license and copyright Date: Fri, 8 Dec 2017 12:32:49 +0100 Message-Id: <20171208113250.359-6-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adopt SPDX License Identifier and add STMicroelectronics copyright Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index c9aed2314194..21479c3cfcb9 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -1,7 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) Maxime Coquelin 2015 + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Maxime Coquelin - * License terms: GNU General Public License (GPL), version 2 + * Author: Benjamin Gaignard for STMicroelectronics. * * Inspired by time-efm32.c from Uwe Kleine-Koenig */ From patchwork Fri Dec 8 11:32:50 2017 Content-Type: text/plain; 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Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.15.0 diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 10099df8b73e..b507e04a52c6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -107,14 +107,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -136,14 +128,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -193,14 +177,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -217,14 +193,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5f66d151eedb..bb3e262bd456 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -103,14 +103,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -132,14 +124,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -189,14 +173,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -213,14 +189,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>;