From patchwork Thu Mar 9 07:57:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95087 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp247346qgd; Thu, 9 Mar 2017 00:06:25 -0800 (PST) X-Received: by 10.84.205.70 with SMTP id o6mr15330258plh.176.1489046785350; Thu, 09 Mar 2017 00:06:25 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3si5739621plx.9.2017.03.09.00.06.25; Thu, 09 Mar 2017 00:06:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753670AbdCIIGM (ORCPT + 4 others); Thu, 9 Mar 2017 03:06:12 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:43527 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752575AbdCIH67 (ORCPT ); Thu, 9 Mar 2017 02:58:59 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v297w1Nr000832; Thu, 9 Mar 2017 01:58:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489046281; bh=lGOprQB69gbhYcDuFoHnIvnAtly0AN4JpA9ltUf/+YI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WeQ4p9f4UM3XHYEkRwfJQttR2y/ezLwg6u1lPiz3V9Wg7wivUdy7aybL+b3bla6tQ P+cs4MbU6Uwtw+JyJ7le8DvNlDfrDg0GMt9uDJgRSw2f9MbsFJ4JvbhAWI0XqTwVpU teFdj3KFCr62Ry0yARpvIVX59Sak1j+4bh4UMpgE= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297w14F019902; Thu, 9 Mar 2017 01:58:01 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Thu, 9 Mar 2017 01:58:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297vZP4014250; Thu, 9 Mar 2017 01:57:57 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v3 06/23] Documentation: PCI: Add specification for the *pci test* function device Date: Thu, 9 Mar 2017 13:27:17 +0530 Message-ID: <1489046254-19919-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489046254-19919-1-git-send-email-kishon@ti.com> References: <1489046254-19919-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add specification for the *pci test* virtual function device. The endpoint function driver and the host pci driver should be created based on this specification. Signed-off-by: Kishon Vijay Abraham I --- Documentation/PCI/00-INDEX | 2 + Documentation/PCI/endpoint/pci-test-function.txt | 66 ++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index f84a23c..4e5a283 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -16,3 +16,5 @@ endpoint/pci-endpoint.txt - guide to add endpoint controller driver and endpoint function driver. endpoint/pci-endpoint-cfs.txt - guide to use configfs to configure the pci endpoint function. +endpoint/pci-test-function.txt + - specification of *pci test* function device. diff --git a/Documentation/PCI/endpoint/pci-test-function.txt b/Documentation/PCI/endpoint/pci-test-function.txt new file mode 100644 index 0000000..1324376 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-test-function.txt @@ -0,0 +1,66 @@ + PCI TEST + Kishon Vijay Abraham I + +Traditionally PCI RC has always been validated by using standard +PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. +However with the addition of EP-core in linux kernel, it is possible +to configure a PCI controller that can operate in EP mode to work as +a test device. + +The PCI endpoint test device is a virtual device (defined in software) +used to test the endpoint functionality and serve as a sample driver +for other PCI endpoint devices (to use the EP framework). + +The PCI endpoint test device has the following registers: + + 1) PCI_ENDPOINT_TEST_MAGIC + 2) PCI_ENDPOINT_TEST_COMMAND + 3) PCI_ENDPOINT_TEST_STATUS + 4) PCI_ENDPOINT_TEST_SRC_ADDR + 5) PCI_ENDPOINT_TEST_DST_ADDR + 6) PCI_ENDPOINT_TEST_SIZE + 7) PCI_ENDPOINT_TEST_CHECKSUM + +*) PCI_ENDPOINT_TEST_MAGIC + +This register will be used to test BAR0. A known pattern will be written +and read back from MAGIC register to verify BAR0. + +*) PCI_ENDPOINT_TEST_COMMAND: + +This register will be used by the host driver to indicate the function +that the endpoint device must perform. + +Bitfield Description: + Bit 0 : raise legacy irq + Bit 1 : raise MSI irq + Bit 2 - 7 : MSI interrupt number + Bit 8 : read command (read data from RC buffer) + Bit 9 : write command (write data to RC buffer) + Bit 10 : copy command (copy data from one RC buffer to another + RC buffer) + +*) PCI_ENDPOINT_TEST_STATUS + +This register reflects the status of the PCI endpoint device. + +Bitfield Description: + Bit 0 : read success + Bit 1 : read fail + Bit 2 : write success + Bit 3 : write fail + Bit 4 : copy success + Bit 5 : copy fail + Bit 6 : irq raised + Bit 7 : source address is invalid + Bit 8 : destination address is invalid + +*) PCI_ENDPOINT_TEST_SRC_ADDR + +This register contains the source address (RC buffer address) for the +COPY/READ command. + +*) PCI_ENDPOINT_TEST_DST_ADDR + +This register contains the destination address (RC buffer address) for +the COPY/WRITE command. From patchwork Thu Mar 9 07:57:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95079 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp246566qgd; Thu, 9 Mar 2017 00:03:46 -0800 (PST) X-Received: by 10.98.220.200 with SMTP id c69mr12493626pfl.60.1489046626720; Thu, 09 Mar 2017 00:03:46 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v35si5705187pgn.161.2017.03.09.00.03.46; Thu, 09 Mar 2017 00:03:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752797AbdCIIDZ (ORCPT + 4 others); Thu, 9 Mar 2017 03:03:25 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:59339 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753702AbdCIIBE (ORCPT ); Thu, 9 Mar 2017 03:01:04 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v297wYRT024441; Thu, 9 Mar 2017 01:58:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489046314; bh=HPX/3ulFYXFkhfgQjLMgom1g9y96DiCwjgAO1DaZhNs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L12XkP70DK0IhYfDfgIqAOmfzHL0Nvij1qlNUn1Vqbt4L5nlXSHhd5Ads2d6/zZfX 2lFxDBfx+HekQuYxZTE6bf2WbJyrIX2kHRSVe3R55eivbYdkeZA1L1mdSya5bBDBMF ahOq9tKNbPUTZfULMiyn69p63Ho+TdWPbx1YJxeg= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297wTNG020260; Thu, 9 Mar 2017 01:58:29 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Thu, 9 Mar 2017 01:58:28 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297vZPC014250; Thu, 9 Mar 2017 01:58:26 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v3 14/23] PCI: dwc: dra7xx: Workaround for errata id i870 Date: Thu, 9 Mar 2017 13:27:25 +0530 Message-ID: <1489046254-19919-15-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489046254-19919-1-git-send-email-kishon@ti.com> References: <1489046254-19919-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 53 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 1cd5c2b..71783a6 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "pcie-designware.h" @@ -528,6 +530,51 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) {}, }; +/* + * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 + * @dra7xx: the dra7xx device where the workaround should be applied + * + * Access to the PCIe slave port that are not 32-bit aligned will result + * in incorrect mapping to TLP Address and Byte enable fields. Therefore, + * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or + * 0x3. + * + * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. + */ +static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) +{ + int ret; + struct device_node *np = dev->of_node; + struct regmap *regmap; + unsigned int reg; + unsigned int field; + + regmap = syscon_regmap_lookup_by_phandle(np, + "ti,syscon-unaligned-access"); + if (IS_ERR(regmap)) { + dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1, + ®)) { + dev_err(dev, "couldn't get legacy mode register offset\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2, + &field)) { + dev_err(dev, "can't get bit field for setting legacy mode\n"); + return -EINVAL; + } + + ret = regmap_update_bits(regmap, reg, field, field); + if (ret) + dev_err(dev, "failed to enable unaligned access\n"); + + return ret; +} + static int __init dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; @@ -637,6 +684,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) case DW_PCIE_RC_TYPE: dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_RC); + ret = dra7xx_add_pcie_port(dra7xx, pdev); if (ret < 0) goto err_gpio; @@ -644,6 +692,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) case DW_PCIE_EP_TYPE: dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP); + + ret = dra7xx_pcie_ep_unaligned_memaccess(dev); + if (ret) + goto err_gpio; + ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio; From patchwork Thu Mar 9 07:57:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95093 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp279787qgd; Thu, 9 Mar 2017 01:50:36 -0800 (PST) X-Received: by 10.84.233.194 with SMTP id m2mr16063430pln.126.1489053036226; Thu, 09 Mar 2017 01:50:36 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 60si5956999plb.324.2017.03.09.01.50.35; Thu, 09 Mar 2017 01:50:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754360AbdCIJud (ORCPT + 4 others); Thu, 9 Mar 2017 04:50:33 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:17934 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754081AbdCIJub (ORCPT ); Thu, 9 Mar 2017 04:50:31 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v297waf1001798; Thu, 9 Mar 2017 01:58:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489046316; bh=8znzxAYTsf2RIZRNai06IafFzURV2w8sFnLjjcgNN/A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vz2IEFKVY1RzLWuIh8DnuqhWlyNm9xEMSjh7gZ6aQqTW6kH6+ahCRUMjH3IdoxNTm 0mYAKbtjnHuPrhfD+CtfnubiCW5RBoh2adkynQx+5P5soYamt8MigwUV+buKUH2h4E reDlz+N98DHalFspWHGel1uOlMQou+asaXtw5LcI= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297waWb031349; Thu, 9 Mar 2017 01:58:36 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Thu, 9 Mar 2017 01:58:35 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297vZPE014250; Thu, 9 Mar 2017 01:58:33 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v3 16/23] PCI: Add device IDs for DRA74x and DRA72x Date: Thu, 9 Mar 2017 13:27:27 +0530 Message-ID: <1489046254-19919-17-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489046254-19919-1-git-send-email-kishon@ti.com> References: <1489046254-19919-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add device IDs for DRA74x and DRA72x devices. These devices have configurable PCI endpoint. Signed-off-by: Kishon Vijay Abraham I --- include/linux/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a4f77fe..5f6b71d 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -862,6 +862,8 @@ #define PCI_DEVICE_ID_TI_X620 0xac8d #define PCI_DEVICE_ID_TI_X420 0xac8e #define PCI_DEVICE_ID_TI_XX20_FM 0xac8f +#define PCI_DEVICE_ID_TI_DRA74x 0xb500 +#define PCI_DEVICE_ID_TI_DRA72x 0xb501 #define PCI_VENDOR_ID_SONY 0x104d From patchwork Thu Mar 9 07:57:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95077 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp246135qgd; Thu, 9 Mar 2017 00:02:27 -0800 (PST) X-Received: by 10.98.139.78 with SMTP id j75mr12552553pfe.122.1489046547610; Thu, 09 Mar 2017 00:02:27 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i9si5686418pli.318.2017.03.09.00.02.27; Thu, 09 Mar 2017 00:02:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753158AbdCIICP (ORCPT + 4 others); Thu, 9 Mar 2017 03:02:15 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:59356 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753707AbdCIIBE (ORCPT ); Thu, 9 Mar 2017 03:01:04 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v297wtxW024478; Thu, 9 Mar 2017 01:58:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489046335; bh=482qetwkLTIgm0CgKlQfR8wqE+rFrg4fxmDCkiQmACQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uo4F/no8kOuG9xy0ILjpUBbi4G73gCxpuumq2M5NDtzX/K4/3vZh3iKEvltb+f20T rZJHfS8eu5Tl6NFOlizL7201JKXy6gxWrXGQNQcXtc4AwhSG1mTcJyNwS/JN+7YVnI DzJqCTQPyC/O0kTM5MKjrZZYfxvhm5MJLE/w7bXQ= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297woDe031500; Thu, 9 Mar 2017 01:58:50 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Thu, 9 Mar 2017 01:58:50 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v297vZPI014250; Thu, 9 Mar 2017 01:58:47 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v3 20/23] tools: PCI: Add sample test script to invoke pcitest Date: Thu, 9 Mar 2017 13:27:31 +0530 Message-ID: <1489046254-19919-21-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489046254-19919-1-git-send-email-kishon@ti.com> References: <1489046254-19919-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add a simple test script that invokes the pcitest userspace tool to perform all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write tests and copy tests). Signed-off-by: Kishon Vijay Abraham I --- tools/pci/pcitest.sh | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 tools/pci/pcitest.sh -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh new file mode 100644 index 0000000..5442bbe --- /dev/null +++ b/tools/pci/pcitest.sh @@ -0,0 +1,56 @@ +#!/bin/sh + +echo "BAR tests" +echo + +bar=0 + +while [ $bar -lt 6 ] +do + pcitest -b $bar + bar=`expr $bar + 1` +done +echo + +echo "Interrupt tests" +echo + +pcitest -l +msi=1 + +while [ $msi -lt 33 ] +do + pcitest -m $msi + msi=`expr $msi + 1` +done +echo + +echo "Read Tests" +echo + +pcitest -r -s 1 +pcitest -r -s 1024 +pcitest -r -s 1025 +pcitest -r -s 1024000 +pcitest -r -s 1024001 +echo + +echo "Write Tests" +echo + +pcitest -w -s 1 +pcitest -w -s 1024 +pcitest -w -s 1025 +pcitest -w -s 1024000 +pcitest -w -s 1024001 +echo + +echo "Copy Tests" +echo + +pcitest -c -s 1 +pcitest -c -s 1024 +pcitest -c -s 1025 +pcitest -c -s 1024000 +pcitest -c -s 1024001 +echo