From patchwork Wed Mar 8 10:47:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95029 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2292791qgd; Wed, 8 Mar 2017 02:55:41 -0800 (PST) X-Received: by 10.99.157.2 with SMTP id i2mr6072934pgd.139.1488970540967; Wed, 08 Mar 2017 02:55:40 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x188si2942986pgb.6.2017.03.08.02.55.40; Wed, 08 Mar 2017 02:55:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752619AbdCHKzk (ORCPT + 25 others); Wed, 8 Mar 2017 05:55:40 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:56921 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751465AbdCHKzf (ORCPT ); Wed, 8 Mar 2017 05:55:35 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28AlfXM021960; Wed, 8 Mar 2017 04:47:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970061; bh=MIvJxFveBjyM1P4EpIB5B3299rQ/2NwNwUWVvMp9RAc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OMcJp2ZednhhAGCcTJwNWW8hX3NdbJ0E5Pf71+TJGGJNXDwT/OdfncerEF6Dxecm2 pTpnmyjNe8232eBsUUhH/3G5oZWaQV4M1zR0XS7MSqBWFGN7962BHbCFw3T6/LJfjZ InUYqRZQCKlrgaL/Ixm4i3s89J5NVIVukbk0+Nfo= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlfxY032318; Wed, 8 Mar 2017 04:47:41 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:47:40 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ29000570; Wed, 8 Mar 2017 04:47:34 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Date: Wed, 8 Mar 2017 16:17:12 +0530 Message-ID: <1488970037-17740-3-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 0984baf..07c45ec 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -88,6 +88,11 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, writel(value, pcie->base + offset); } +static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr) +{ + return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; +} + static int dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); @@ -152,11 +157,6 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); - pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; - dw_pcie_setup_rc(pp); dra7xx_pcie_establish_link(dra7xx); @@ -329,6 +329,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, } static const struct dw_pcie_ops dw_pcie_ops = { + .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, .link_up = dra7xx_pcie_link_up, }; From patchwork Wed Mar 8 10:47:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95031 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2292954qgd; Wed, 8 Mar 2017 02:56:08 -0800 (PST) X-Received: by 10.84.234.8 with SMTP id m8mr7749957plk.25.1488970568158; Wed, 08 Mar 2017 02:56:08 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si2935915plk.81.2017.03.08.02.56.07; Wed, 08 Mar 2017 02:56:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752670AbdCHK4G (ORCPT + 25 others); Wed, 8 Mar 2017 05:56:06 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:26791 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752548AbdCHKzi (ORCPT ); Wed, 8 Mar 2017 05:55:38 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28Allk7001731; Wed, 8 Mar 2017 04:47:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970067; bh=oSAQ1IRDX69XXCvI0rvvKrOJzbzU9W8ohNwsXKaow/A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L0x5tfS0R2GfuLuzrC5qeWFAoUhA47vHPGB63dns0CuGGocaIw6EpbKS5SWPVAnRk 0W6XhCREZMLOClb92NhFjdelUKLutl9cJBWjf2FrLceEo+0o4++3MeVpxIYIWXUkWU 9EwvstVVZS0AYa/lVly97y+wbGaTo/ku4i0cZsr4= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AllGv032389; Wed, 8 Mar 2017 04:47:47 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:47:46 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2A000570; Wed, 8 Mar 2017 04:47:41 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I , Niklas Cassel Subject: [PATCH v3 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops Date: Wed, 8 Mar 2017 16:17:13 +0530 Message-ID: <1488970037-17740-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Cc: Niklas Cassel Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-artpec6.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index fcd3ef8..5b3b3af 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -78,6 +78,11 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u regmap_write(artpec6_pcie->regmap, offset, val); } +static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr) +{ + return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR; +} + static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) { struct dw_pcie *pci = artpec6_pcie->pci; @@ -142,11 +147,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) */ dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); - pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR; - /* setup root complex */ dw_pcie_setup_rc(pp); @@ -234,6 +234,10 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie, return 0; } +static const struct dw_pcie_ops dw_pcie_ops = { + .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup, +}; + static int artpec6_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev) return -ENOMEM; pci->dev = dev; + pci->ops = &dw_pcie_ops; artpec6_pcie->pci = pci; From patchwork Wed Mar 8 10:47:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95030 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2292829qgd; Wed, 8 Mar 2017 02:55:49 -0800 (PST) X-Received: by 10.84.176.100 with SMTP id u91mr7886938plb.112.1488970549459; Wed, 08 Mar 2017 02:55:49 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si2935915plk.81.2017.03.08.02.55.49; Wed, 08 Mar 2017 02:55:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752652AbdCHKzn (ORCPT + 25 others); Wed, 8 Mar 2017 05:55:43 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:26791 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751465AbdCHKzk (ORCPT ); Wed, 8 Mar 2017 05:55:40 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28Alv8u001740; Wed, 8 Mar 2017 04:47:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970077; bh=oMm2x/sxrg4uoV1HaARTb7CF+NrPkt52bIxN0YhGxBw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V7rVEBb43idjeDlf/vvprtc9CsLhButYCESOq4ixXGRlnW3cT83l+XT+PM5SkeBA7 tz7R5aKKzjXPp1yh21o10K5+9uD+PaC0tvMTkSDFawUZnjSrfUbLUZdigHstXHIUks ji+tMjA98c5GI1f7syYmlJSNXTw9eReocbqnmnG4= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28Alv0f032512; Wed, 8 Mar 2017 04:47:57 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:47:56 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2B000570; Wed, 8 Mar 2017 04:47:47 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I , Jingoo Han , Richard Zhu , Lucas Stach , Murali Karicheri , Thomas Petazzoni , Niklas Cassel , Jesper Nilsson , Zhou Wang , Gabriele Paoloni Subject: [PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Date: Wed, 8 Mar 2017 16:17:14 +0530 Message-ID: <1488970037-17740-5-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Cc: Jingoo Han Cc: Richard Zhu Cc: Lucas Stach Cc: Murali Karicheri Cc: Thomas Petazzoni Cc: Niklas Cassel Cc: Jesper Nilsson Cc: Joao Pinto Cc: Zhou Wang Cc: Gabriele Paoloni Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 10 +++-- drivers/pci/dwc/pci-exynos.c | 10 +++-- drivers/pci/dwc/pci-imx6.c | 62 +++++++++++++++----------- drivers/pci/dwc/pci-keystone-dw.c | 15 ++++--- drivers/pci/dwc/pcie-armada8k.c | 39 +++++++++------- drivers/pci/dwc/pcie-artpec6.c | 7 +-- drivers/pci/dwc/pcie-designware-host.c | 20 +++++---- drivers/pci/dwc/pcie-designware.c | 76 ++++++++++++++++++-------------- drivers/pci/dwc/pcie-designware.h | 10 +++-- drivers/pci/dwc/pcie-hisi.c | 17 ++++--- 10 files changed, 152 insertions(+), 114 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 07c45ec..3708bd6 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -495,12 +495,13 @@ static int dra7xx_pcie_suspend(struct device *dev) { struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); struct dw_pcie *pci = dra7xx->pci; + void __iomem *base = pci->dbi_base; u32 val; /* clear MSE */ - val = dw_pcie_readl_dbi(pci, PCI_COMMAND); + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); val &= ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); return 0; } @@ -509,12 +510,13 @@ static int dra7xx_pcie_resume(struct device *dev) { struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); struct dw_pcie *pci = dra7xx->pci; + void __iomem *base = pci->dbi_base; u32 val; /* set MSE */ - val = dw_pcie_readl_dbi(pci, PCI_COMMAND); + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); val |= PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); return 0; } diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c index 993b650..a0d40f7 100644 --- a/drivers/pci/dwc/pci-exynos.c +++ b/drivers/pci/dwc/pci-exynos.c @@ -521,23 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep) exynos_pcie_msi_init(ep); } -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) +static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg) { struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val; exynos_pcie_sideband_dbi_r_mode(ep, true); - val = readl(pci->dbi_base + reg); + val = readl(base + reg); exynos_pcie_sideband_dbi_r_mode(ep, false); return val; } -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) +static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, u32 val) { struct exynos_pcie *ep = to_exynos_pcie(pci); exynos_pcie_sideband_dbi_w_mode(ep, true); - writel(val, pci->dbi_base + reg); + writel(val, base + reg); exynos_pcie_sideband_dbi_w_mode(ep, false); } diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 801e46c..85dd901 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -98,12 +98,13 @@ struct imx6_pcie { static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; u32 val; u32 max_iterations = 10; u32 wait_counter = 0; do { - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT); val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; wait_counter++; @@ -119,21 +120,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; u32 val; int ret; val = addr << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) return ret; val = addr << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); return pcie_phy_poll_ack(imx6_pcie, 0); } @@ -142,6 +144,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; u32 val, phy_ctl; int ret; @@ -151,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) /* assert Read signal */ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) return ret; - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT); *data = val & 0xffff; /* deassert Read signal */ - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00); return pcie_phy_poll_ack(imx6_pcie, 0); } @@ -169,6 +172,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; u32 var; int ret; @@ -179,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) return ret; var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); /* capture data */ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) @@ -191,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* deassert cap data */ var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ ret = pcie_phy_poll_ack(imx6_pcie, 0); @@ -200,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* assert wr signal */ var = 0x1 << PCIE_PHY_CTRL_WR_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); /* wait for ack */ ret = pcie_phy_poll_ack(imx6_pcie, 1); @@ -209,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* deassert wr signal */ var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ ret = pcie_phy_poll_ack(imx6_pcie, 0); if (ret) return ret; - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0); return 0; } @@ -411,6 +415,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; struct device *dev = pci->dev; /* check if the link is up or not */ @@ -418,20 +423,22 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) return 0; dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); return -ETIMEDOUT; } static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; struct device *dev = pci->dev; u32 tmp; unsigned int retries; for (retries = 0; retries < 200; retries++) { - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp = dw_pcie_readl_dbi(pci, base, + PCIE_LINK_WIDTH_SPEED_CONTROL); /* Test if the speed change finished. */ if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) return 0; @@ -454,6 +461,7 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; + void __iomem *base = pci->dbi_base; struct device *dev = pci->dev; u32 tmp; int ret; @@ -463,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR); tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp); /* Start LTSSM. */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -478,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) if (imx6_pcie->link_gen == 2) { /* Allow Gen2 mode after the link is up. */ - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR); tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp); } else { dev_info(dev, "Link: Gen2 disabled\n"); } @@ -490,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) * Start Directed Speed Change so the best possible speed both link * partners support can be negotiated. */ - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL); tmp |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); ret = imx6_pcie_wait_for_speed_change(imx6_pcie); if (ret) { @@ -507,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) goto err_reset_phy; } - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR); dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); return 0; err_reset_phy: dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); imx6_pcie_reset_phy(imx6_pcie); return ret; } @@ -536,7 +544,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp) static int imx6_pcie_link_up(struct dw_pcie *pci) { - return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) & + void __iomem *base = pci->dbi_base; + + return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; } diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c index 6b396f6..7220c04 100644 --- a/drivers/pci/dwc/pci-keystone-dw.c +++ b/drivers/pci/dwc/pci-keystone-dw.c @@ -378,6 +378,7 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; + void __iomem *base = pci->dbi_base; struct pcie_port *pp = &pci->pp; u32 start = pp->mem->start, end = pp->mem->end; int i, tr_size; @@ -385,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) /* Disable BARs for inbound access */ ks_dw_pcie_set_dbi_mode(ks_pcie); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0); ks_dw_pcie_clear_dbi_mode(ks_pcie); /* Set outbound translation size per window division */ @@ -482,14 +483,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + void __iomem *base = pci->dbi_base; struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); /* Configure and set up BAR0 */ ks_dw_pcie_set_dbi_mode(ks_pcie); /* Enable BAR0 */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1); ks_dw_pcie_clear_dbi_mode(ks_pcie); @@ -497,7 +499,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) * For BAR0, just setting bus address for inbound writes (MSI) should * be sufficient. Use physical address to avoid any conflicts. */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start); } /** @@ -506,8 +508,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) int ks_dw_pcie_link_up(struct dw_pcie *pci) { u32 val; + void __iomem *base = pci->dbi_base; - val = dw_pcie_readl_dbi(pci, DEBUG0); + val = dw_pcie_readl_dbi(pci, base, DEBUG0); return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c index f110e3b..b2328df 100644 --- a/drivers/pci/dwc/pcie-armada8k.c +++ b/drivers/pci/dwc/pcie-armada8k.c @@ -73,8 +73,9 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) { u32 reg; u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; + void __iomem *base = pci->dbi_base; - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG); if ((reg & mask) == mask) return 1; @@ -86,47 +87,50 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) { struct dw_pcie *pci = pcie->pci; + void __iomem *base = pci->dbi_base; u32 reg; if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); reg &= ~(PCIE_APP_LTSSM_EN); - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); } /* Set the device to root complex mode */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); /* Set the PCIe master AxCache attributes */ - dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); - dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG, + ARCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG, + AWCACHE_DEFAULT_VALUE); /* Set the PCIe master AxDomain attributes */ - reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg); - reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg); /* Enable INT A-D interrupts */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG); reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg); if (!dw_pcie_link_up(pci)) { /* Configuration done. Start LTSSM */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); reg |= PCIE_APP_LTSSM_EN; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); } /* Wait until the link becomes active again */ @@ -147,6 +151,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) { struct armada8k_pcie *pcie = arg; struct dw_pcie *pci = pcie->pci; + void __iomem *base = pci->dbi_base; u32 val; /* @@ -154,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) * PCI device. However, they are also latched into the PCIe * controller, so we simply discard them. */ - val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG); + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val); return IRQ_HANDLED; } diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index 5b3b3af..e3ba11c 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -86,6 +86,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr) static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) { struct dw_pcie *pci = artpec6_pcie->pci; + void __iomem *base = pci->dbi_base; struct pcie_port *pp = &pci->pp; u32 val; unsigned int retries; @@ -145,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) * Enable writing to config regs. This is required as the Synopsys * driver changes the class code. That register needs DBI write enable. */ - dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); + dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); /* setup root complex */ dw_pcie_setup_rc(pp); @@ -160,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) return 0; dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); return -ETIMEDOUT; } diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 5ba3349..9df620d 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -566,8 +566,9 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) { u32 val; + void __iomem *base = pci->dbi_base; - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT); if (val == 0xffffffff) return 1; @@ -578,31 +579,32 @@ void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + void __iomem *base = pci->dbi_base; dw_pcie_setup(pci); /* setup RC BARs */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004); + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000); /* setup interrupt pins */ - val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); + val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val); /* setup bus numbers */ - val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); + val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS); val &= 0xff000000; val |= 0x00010100; - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); + dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val); /* setup command register */ - val = dw_pcie_readl_dbi(pci, PCI_COMMAND); + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); /* * If the platform provides ->rd_other_conf, it means the platform diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 14ee7a3..f8eaeea 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -61,75 +61,82 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg) { if (pci->ops->readl_dbi) - return pci->ops->readl_dbi(pci, reg); + return pci->ops->readl_dbi(pci, base, reg); - return readl(pci->dbi_base + reg); + return readl(base + reg); } -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + u32 val) { if (pci->ops->writel_dbi) - pci->ops->writel_dbi(pci, reg, val); + pci->ops->writel_dbi(pci, base, reg, val); else - writel(val, pci->dbi_base + reg); + writel(val, base + reg); } -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg) +static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - return dw_pcie_readl_dbi(pci, offset + reg); + return dw_pcie_readl_dbi(pci, base, offset + reg); } -static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg, - u32 val) +static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - dw_pcie_writel_dbi(pci, offset + reg, val); + dw_pcie_writel_dbi(pci, base, offset + reg, val); } void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size) { u32 retries, val; + void __iomem *base = pci->dbi_base; - if (pp->ops->cpu_addr_fixup) - cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); + if (pci->ops->cpu_addr_fixup) + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); if (pci->iatu_unroll_enabled) { - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT, + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, + dw_pcie_writel_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, + dw_pcie_writel_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, + dw_pcie_writel_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL1, type); - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + dw_pcie_writel_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE); } else { - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index); - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE, lower_32_bits(cpu_addr)); - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE, upper_32_bits(cpu_addr)); - dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT, lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET, lower_32_bits(pci_addr)); - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET, upper_32_bits(pci_addr)); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type); + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE); } /* @@ -138,10 +145,10 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { if (pci->iatu_unroll_enabled) - val = dw_pcie_readl_unroll(pci, index, + val = dw_pcie_readl_unroll(pci, base, index, PCIE_ATU_UNR_REGION_CTRL2); else - val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2); if (val == PCIE_ATU_ENABLE) return; @@ -188,13 +195,14 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 lanes; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + void __iomem *base = pci->dbi_base; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) lanes = 0; /* set the number of lanes */ - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; switch (lanes) { case 1: @@ -213,10 +221,10 @@ void dw_pcie_setup(struct dw_pcie *pci) dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); return; } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val); /* set link width speed control register */ - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_LINK_WIDTH_MASK; switch (lanes) { case 1: @@ -232,5 +240,5 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LOGIC_LINK_WIDTH_8_LANES; break; } - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val); } diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index 8f3dcb2..fe93f7f 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -144,8 +144,9 @@ struct pcie_port { struct dw_pcie_ops { u64 (*cpu_addr_fixup)(u64 cpu_addr); - u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); - void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); + u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg); + void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + u32 val); int (*link_up)(struct dw_pcie *pcie); }; @@ -163,8 +164,9 @@ struct dw_pcie { int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg); -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val); +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg); +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c index fd66a31..409b54b 100644 --- a/drivers/pci/dwc/pcie-hisi.c +++ b/drivers/pci/dwc/pcie-hisi.c @@ -152,10 +152,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, u32 reg_val; void *walker = ®_val; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + void __iomem *base = pci->dbi_base; walker += (where & 0x3); reg = where & ~0x3; - reg_val = dw_pcie_readl_dbi(pci, reg); + reg_val = dw_pcie_readl_dbi(pci, base, reg); if (size == 1) *val = *(u8 __force *) walker; @@ -177,19 +178,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size, u32 reg; void *walker = ®_val; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + void __iomem *base = pci->dbi_base; walker += (where & 0x3); reg = where & ~0x3; if (size == 4) - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_writel_dbi(pci, base, reg, val); else if (size == 2) { - reg_val = dw_pcie_readl_dbi(pci, reg); + reg_val = dw_pcie_readl_dbi(pci, base, reg); *(u16 __force *) walker = val; - dw_pcie_writel_dbi(pci, reg, reg_val); + dw_pcie_writel_dbi(pci, base, reg, reg_val); } else if (size == 1) { - reg_val = dw_pcie_readl_dbi(pci, reg); + reg_val = dw_pcie_readl_dbi(pci, base, reg); *(u8 __force *) walker = val; - dw_pcie_writel_dbi(pci, reg, reg_val); + dw_pcie_writel_dbi(pci, base, reg, reg_val); } else return PCIBIOS_BAD_REGISTER_NUMBER; @@ -209,9 +211,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie) static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) { struct dw_pcie *pci = hisi_pcie->pci; + void __iomem *base = pci->dbi_base; u32 val; - val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4); + val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4); return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); } From patchwork Wed Mar 8 10:47:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95032 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2293260qgd; Wed, 8 Mar 2017 02:57:05 -0800 (PST) X-Received: by 10.98.64.129 with SMTP id f1mr6202201pfd.123.1488970625801; Wed, 08 Mar 2017 02:57:05 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si2919545pgs.213.2017.03.08.02.57.05; Wed, 08 Mar 2017 02:57:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752736AbdCHK4y (ORCPT + 25 others); Wed, 8 Mar 2017 05:56:54 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:56921 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752095AbdCHKzh (ORCPT ); Wed, 8 Mar 2017 05:55:37 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28Am4ds022000; Wed, 8 Mar 2017 04:48:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970084; bh=nt0m6gmK90wKzQBrqVnWScaZNhlb7KMxcCoUUQeRlqE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qu9nkqxGxkJsiop+P4z1qLjZvJxOOQLq0FWllVcqOGWh53tlvrSAgmhlv1aAvMluW ufEHUXbFMlT4Xus7zt16v5Pg9PwXrSN0F9BxXyz7PmWrgQnA+AE7SabKziULjWdfzQ Ed8jdoSgG8IFKODcFdxEpKjh7enGmr7HNsNIExEg= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28Am3PT019963; Wed, 8 Mar 2017 04:48:03 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:48:02 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2C000570; Wed, 8 Mar 2017 04:47:57 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I , Jingoo Han , Richard Zhu , Lucas Stach , Murali Karicheri , Thomas Petazzoni , Niklas Cassel , Jesper Nilsson , Zhou Wang , Gabriele Paoloni Subject: [PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Date: Wed, 8 Mar 2017 16:17:15 +0530 Message-ID: <1488970037-17740-6-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Cc: Jingoo Han Cc: Richard Zhu Cc: Lucas Stach Cc: Murali Karicheri Cc: Thomas Petazzoni Cc: Niklas Cassel Cc: Jesper Nilsson Cc: Joao Pinto Cc: Zhou Wang Cc: Gabriele Paoloni Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 8 ++-- drivers/pci/dwc/pci-exynos.c | 16 +++---- drivers/pci/dwc/pci-imx6.c | 54 +++++++++++----------- drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- drivers/pci/dwc/pcie-armada8k.c | 38 ++++++++-------- drivers/pci/dwc/pcie-artpec6.c | 6 +-- drivers/pci/dwc/pcie-designware-host.c | 18 ++++---- drivers/pci/dwc/pcie-designware.c | 77 +++++++++++++++++++------------- drivers/pci/dwc/pcie-designware.h | 14 +++--- drivers/pci/dwc/pcie-hisi.c | 14 +++--- 10 files changed, 138 insertions(+), 120 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 3708bd6..c6fef0a 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -499,9 +499,9 @@ static int dra7xx_pcie_suspend(struct device *dev) u32 val; /* clear MSE */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4); val &= ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val); return 0; } @@ -514,9 +514,9 @@ static int dra7xx_pcie_resume(struct device *dev) u32 val; /* set MSE */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4); val |= PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val); return 0; } diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c index a0d40f7..37d6d2b 100644 --- a/drivers/pci/dwc/pci-exynos.c +++ b/drivers/pci/dwc/pci-exynos.c @@ -521,25 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep) exynos_pcie_msi_init(ep); } -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, - u32 reg) +static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) { struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val; exynos_pcie_sideband_dbi_r_mode(ep, true); - val = readl(base + reg); + dw_pcie_read(base + reg, size, &val); exynos_pcie_sideband_dbi_r_mode(ep, false); return val; } -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, - u32 reg, u32 val) +static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) { struct exynos_pcie *ep = to_exynos_pcie(pci); exynos_pcie_sideband_dbi_w_mode(ep, true); - writel(val, base + reg); + dw_pcie_write(base + reg, size, val); exynos_pcie_sideband_dbi_w_mode(ep, false); } @@ -646,8 +646,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep, } static const struct dw_pcie_ops dw_pcie_ops = { - .readl_dbi = exynos_pcie_readl_dbi, - .writel_dbi = exynos_pcie_writel_dbi, + .read_dbi = exynos_pcie_read_dbi, + .write_dbi = exynos_pcie_write_dbi, .link_up = exynos_pcie_link_up, }; diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 85dd901..e58ca7a 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -104,7 +104,7 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) u32 wait_counter = 0; do { - val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT); + val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4); val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; wait_counter++; @@ -125,17 +125,17 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) int ret; val = addr << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val); val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) return ret; val = addr << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val); return pcie_phy_poll_ack(imx6_pcie, 0); } @@ -154,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) /* assert Read signal */ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, phy_ctl); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) return ret; - val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT); + val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4); *data = val & 0xffff; /* deassert Read signal */ - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x00); return pcie_phy_poll_ack(imx6_pcie, 0); } @@ -183,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) return ret; var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var); /* capture data */ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var); ret = pcie_phy_poll_ack(imx6_pcie, 1); if (ret) @@ -195,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* deassert cap data */ var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var); /* wait for ack de-assertion */ ret = pcie_phy_poll_ack(imx6_pcie, 0); @@ -204,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* assert wr signal */ var = 0x1 << PCIE_PHY_CTRL_WR_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var); /* wait for ack */ ret = pcie_phy_poll_ack(imx6_pcie, 1); @@ -213,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) /* deassert wr signal */ var = data << PCIE_PHY_CTRL_DATA_LOC; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var); /* wait for ack de-assertion */ ret = pcie_phy_poll_ack(imx6_pcie, 0); if (ret) return ret; - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0); + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x0); return 0; } @@ -423,8 +423,8 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) return 0; dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4), + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4)); return -ETIMEDOUT; } @@ -437,8 +437,8 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) unsigned int retries; for (retries = 0; retries < 200; retries++) { - tmp = dw_pcie_readl_dbi(pci, base, - PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp = dw_pcie_read_dbi(pci, base, + PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4); /* Test if the speed change finished. */ if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) return 0; @@ -471,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR); + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4); tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; - dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp); + dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp); /* Start LTSSM. */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -486,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) if (imx6_pcie->link_gen == 2) { /* Allow Gen2 mode after the link is up. */ - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR); + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4); tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; - dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp); + dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp); } else { dev_info(dev, "Link: Gen2 disabled\n"); } @@ -498,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) * Start Directed Speed Change so the best possible speed both link * partners support can be negotiated. */ - tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4); tmp |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, tmp); ret = imx6_pcie_wait_for_speed_change(imx6_pcie); if (ret) { @@ -515,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) goto err_reset_phy; } - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR); + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCSR, 0x4); dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); return 0; err_reset_phy: dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4), + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4)); imx6_pcie_reset_phy(imx6_pcie); return ret; } @@ -546,7 +546,7 @@ static int imx6_pcie_link_up(struct dw_pcie *pci) { void __iomem *base = pci->dbi_base; - return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) & + return dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4) & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; } diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c index 7220c04..8318efe 100644 --- a/drivers/pci/dwc/pci-keystone-dw.c +++ b/drivers/pci/dwc/pci-keystone-dw.c @@ -386,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) /* Disable BARs for inbound access */ ks_dw_pcie_set_dbi_mode(ks_pcie); - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0); - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0); ks_dw_pcie_clear_dbi_mode(ks_pcie); /* Set outbound translation size per window division */ @@ -490,8 +490,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) ks_dw_pcie_set_dbi_mode(ks_pcie); /* Enable BAR0 */ - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1); - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 1); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, SZ_4K - 1); ks_dw_pcie_clear_dbi_mode(ks_pcie); @@ -499,7 +499,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) * For BAR0, just setting bus address for inbound writes (MSI) should * be sufficient. Use physical address to avoid any conflicts. */ - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, + ks_pcie->app.start); } /** @@ -510,7 +511,7 @@ int ks_dw_pcie_link_up(struct dw_pcie *pci) u32 val; void __iomem *base = pci->dbi_base; - val = dw_pcie_readl_dbi(pci, base, DEBUG0); + val = dw_pcie_read_dbi(pci, base, DEBUG0, 0x4); return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c index b2328df..447d178 100644 --- a/drivers/pci/dwc/pcie-armada8k.c +++ b/drivers/pci/dwc/pcie-armada8k.c @@ -75,7 +75,7 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; void __iomem *base = pci->dbi_base; - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_STATUS_REG, 0x4); if ((reg & mask) == mask) return 1; @@ -92,45 +92,45 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4); reg &= ~(PCIE_APP_LTSSM_EN); - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg); } /* Set the device to root complex mode */ - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4); reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg); /* Set the PCIe master AxCache attributes */ - dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG, - ARCACHE_DEFAULT_VALUE); - dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG, - AWCACHE_DEFAULT_VALUE); + dw_pcie_write_dbi(pci, base, PCIE_ARCACHE_TRC_REG, 0x4, + ARCACHE_DEFAULT_VALUE); + dw_pcie_write_dbi(pci, base, PCIE_AWCACHE_TRC_REG, 0x4, + AWCACHE_DEFAULT_VALUE); /* Set the PCIe master AxDomain attributes */ - reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_ARUSER_REG, 0x4); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_ARUSER_REG, 0x4, reg); - reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_AWUSER_REG, 0x4); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_AWUSER_REG, 0x4, reg); /* Enable INT A-D interrupts */ - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4); reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4, reg); if (!dw_pcie_link_up(pci)) { /* Configuration done. Start LTSSM */ - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4); reg |= PCIE_APP_LTSSM_EN; - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg); } /* Wait until the link becomes active again */ @@ -159,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) * PCI device. However, they are also latched into the PCIe * controller, so we simply discard them. */ - val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG); - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val); + val = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4); + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4, val); return IRQ_HANDLED; } diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index e3ba11c..0829de4 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -146,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) * Enable writing to config regs. This is required as the Synopsys * driver changes the class code. That register needs DBI write enable. */ - dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); + dw_pcie_write_dbi(pci, base, MISC_CONTROL_1_OFF, 0x4, DBI_RO_WR_EN); /* setup root complex */ dw_pcie_setup_rc(pp); @@ -161,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) return 0; dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1)); + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4), + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4)); return -ETIMEDOUT; } diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 9df620d..3150d33 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -568,7 +568,7 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) u32 val; void __iomem *base = pci->dbi_base; - val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT); + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4); if (val == 0xffffffff) return 1; @@ -584,27 +584,27 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); /* setup RC BARs */ - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004); - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0x00000004); + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0x00000000); /* setup interrupt pins */ - val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE); + val = dw_pcie_read_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4); val &= 0xffff00ff; val |= 0x00000100; - dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val); + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, val); /* setup bus numbers */ - val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS); + val = dw_pcie_read_dbi(pci, base, PCI_PRIMARY_BUS, 0x4); val &= 0xff000000; val |= 0x00010100; - dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val); + dw_pcie_write_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, val); /* setup command register */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val); /* * If the platform provides ->rd_other_conf, it means the platform diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index f8eaeea..557ee53 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg) +u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size) { - if (pci->ops->readl_dbi) - return pci->ops->readl_dbi(pci, base, reg); + int ret; + u32 val; + + if (pci->ops->read_dbi) + return pci->ops->read_dbi(pci, base, reg, size); - return readl(base + reg); + ret = dw_pcie_read(base + reg, size, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); + + return val; } -void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - u32 val) +void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val) { - if (pci->ops->writel_dbi) - pci->ops->writel_dbi(pci, base, reg, val); - else - writel(val, base + reg); + int ret; + + if (pci->ops->write_dbi) { + pci->ops->write_dbi(pci, base, reg, size, val); + return; + } + + ret = dw_pcie_write(base + reg, size, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); } static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, @@ -83,7 +97,7 @@ static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - return dw_pcie_readl_dbi(pci, base, offset + reg); + return dw_pcie_read_dbi(pci, base, offset + reg, 0x4); } static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, @@ -91,7 +105,7 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - dw_pcie_writel_dbi(pci, base, offset + reg, val); + dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val); } void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, @@ -123,20 +137,21 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE); } else { - dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT, - PCIE_ATU_REGION_OUTBOUND | index); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE, - lower_32_bits(cpu_addr)); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE, - upper_32_bits(cpu_addr)); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET, - upper_32_bits(pci_addr)); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type); - dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE); + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, + PCIE_ATU_REGION_OUTBOUND | index); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4, + lower_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4, + upper_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4, + lower_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4, + upper_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, + PCIE_ATU_ENABLE); } /* @@ -148,7 +163,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, val = dw_pcie_readl_unroll(pci, base, index, PCIE_ATU_UNR_REGION_CTRL2); else - val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2); + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4); if (val == PCIE_ATU_ENABLE) return; @@ -202,7 +217,7 @@ void dw_pcie_setup(struct dw_pcie *pci) lanes = 0; /* set the number of lanes */ - val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL); + val = dw_pcie_read_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4); val &= ~PORT_LINK_MODE_MASK; switch (lanes) { case 1: @@ -221,10 +236,10 @@ void dw_pcie_setup(struct dw_pcie *pci) dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); return; } - dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_write_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, val); /* set link width speed control register */ - val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL); + val = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4); val &= ~PORT_LOGIC_LINK_WIDTH_MASK; switch (lanes) { case 1: @@ -240,5 +255,5 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LOGIC_LINK_WIDTH_8_LANES; break; } - dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, val); } diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index fe93f7f..74df063 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -144,9 +144,10 @@ struct pcie_port { struct dw_pcie_ops { u64 (*cpu_addr_fixup)(u64 cpu_addr); - u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg); - void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, - u32 val); + u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size); + void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); }; @@ -164,9 +165,10 @@ struct dw_pcie { int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg); -void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - u32 val); +u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size); +void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c index 409b54b..cc04381 100644 --- a/drivers/pci/dwc/pcie-hisi.c +++ b/drivers/pci/dwc/pcie-hisi.c @@ -156,7 +156,7 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, walker += (where & 0x3); reg = where & ~0x3; - reg_val = dw_pcie_readl_dbi(pci, base, reg); + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4); if (size == 1) *val = *(u8 __force *) walker; @@ -183,15 +183,15 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size, walker += (where & 0x3); reg = where & ~0x3; if (size == 4) - dw_pcie_writel_dbi(pci, base, reg, val); + dw_pcie_write_dbi(pci, base, reg, 0x4, val); else if (size == 2) { - reg_val = dw_pcie_readl_dbi(pci, base, reg); + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4); *(u16 __force *) walker = val; - dw_pcie_writel_dbi(pci, base, reg, reg_val); + dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val); } else if (size == 1) { - reg_val = dw_pcie_readl_dbi(pci, base, reg); + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4); *(u8 __force *) walker = val; - dw_pcie_writel_dbi(pci, base, reg, reg_val); + dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val); } else return PCIBIOS_BAD_REGISTER_NUMBER; @@ -214,7 +214,7 @@ static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) void __iomem *base = pci->dbi_base; u32 val; - val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4); + val = dw_pcie_read_dbi(pci, base, PCIE_SYS_STATE4, 0x4); return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); } From patchwork Wed Mar 8 10:47:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95033 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2293385qgd; Wed, 8 Mar 2017 02:57:40 -0800 (PST) X-Received: by 10.99.154.9 with SMTP id o9mr6193283pge.69.1488970660225; Wed, 08 Mar 2017 02:57:40 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si2923150plz.212.2017.03.08.02.57.39; Wed, 08 Mar 2017 02:57:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752755AbdCHK5M (ORCPT + 25 others); Wed, 8 Mar 2017 05:57:12 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:26791 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752110AbdCHKzh (ORCPT ); Wed, 8 Mar 2017 05:55:37 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28Am7oC001775; Wed, 8 Mar 2017 04:48:07 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970087; bh=UVlaOSv9tqVdYi5RNfERXy64rAHbzGSj1uo0KbJIMU8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yGpjXfJMpMe2MZKX4K4cL5L45s2ovwxGK4yktOtEhUyagnPIBuxD5iibrcBFbnJl9 /CBmbBa7CzNvv7i2lPGFaUrWKggtA8jcf5uVBzg2OmLboe+RyrhIKtpeyisaaCttUs j9h6++s7YyLloLErEA9h6JbkTlBp7DDQoNphK0dQ= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28Am6Nx020060; Wed, 8 Mar 2017 04:48:06 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:48:06 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2D000570; Wed, 8 Mar 2017 04:48:03 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Date: Wed, 8 Mar 2017 16:17:16 +0530 Message-ID: <1488970037-17740-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 112 ++++++++++++++++++++++--------------- 1 file changed, 67 insertions(+), 45 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 557ee53..6657a84 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -92,22 +92,64 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "write DBI address failed\n"); } -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg) +static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); return dw_pcie_read_dbi(pci, base, offset + reg, 0x4); } -static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg, u32 val) +static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val); } +void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type, + u64 cpu_addr, u64 pci_addr, u32 size) +{ + u32 retries, val; + void __iomem *base = pci->dbi_base; + + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { + val = dw_pcie_readl_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return; + + usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + } + dev_err(pci->dev, "outbound iATU is not being enabled\n"); +} + void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size) { @@ -118,59 +160,39 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); if (pci->iatu_unroll_enabled) { - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE, - lower_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE, - upper_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_UPPER_TARGET, - upper_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL1, - type); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2, - PCIE_ATU_ENABLE); - } else { - dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, - PCIE_ATU_REGION_OUTBOUND | index); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4, - lower_32_bits(cpu_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4, - upper_32_bits(cpu_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4, - lower_32_bits(pci_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4, - upper_32_bits(pci_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type); - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, - PCIE_ATU_ENABLE); + dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr, + pci_addr, size); + return; } + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, + PCIE_ATU_REGION_OUTBOUND | index); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4, + lower_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4, + upper_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4, + lower_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4, + upper_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, + PCIE_ATU_ENABLE); + /* * Make sure ATU enable takes effect before any subsequent config * and I/O accesses. */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { - if (pci->iatu_unroll_enabled) - val = dw_pcie_readl_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2); - else - val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4); - + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4); if (val == PCIE_ATU_ENABLE) return; usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "iATU is not being enabled\n"); + dev_err(pci->dev, "outbound iATU is not being enabled\n"); } int dw_pcie_wait_for_link(struct dw_pcie *pci) From patchwork Wed Mar 8 10:47:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95028 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2292784qgd; Wed, 8 Mar 2017 02:55:39 -0800 (PST) X-Received: by 10.99.163.2 with SMTP id s2mr6129306pge.43.1488970539602; Wed, 08 Mar 2017 02:55:39 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x188si2942986pgb.6.2017.03.08.02.55.39; Wed, 08 Mar 2017 02:55:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752547AbdCHKzh (ORCPT + 25 others); Wed, 8 Mar 2017 05:55:37 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:26791 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750853AbdCHKzf (ORCPT ); Wed, 8 Mar 2017 05:55:35 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28AmA20001783; Wed, 8 Mar 2017 04:48:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970090; bh=O+r8pdXsXOGR539QsAympqzE8fVVwpHe0UV1kbUGX/k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JPXC6ghGilWMp2Rx7d9iW2aQrygleBXyX+GadNtZKOOA02bcolPEvRnK9aC/NZzye ceO83Dh3bC4MgEJDjQFNedgR4fgK4g0bPEdtb7YKt8V3Ibse/UtVM3mQjFJVzLIG2+ anLT/PGZRBDcrFQUjuiFIyxxVC4X+EKD0jDsplNg= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AmAx9020156; Wed, 8 Mar 2017 04:48:10 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:48:09 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2E000570; Wed, 8 Mar 2017 04:48:07 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Keerthy , Kishon Vijay Abraham I Subject: [PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Date: Wed, 8 Mar 2017 16:17:17 +0530 Message-ID: <1488970037-17740-8-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Keerthy Currently devm_request_irq is being called before base, pci fields of dra7xx_pcie structure are populated. It is called even before pm_runtime_enable and pm_runtime_get_sync are called. This will lead to exceptions if in case an interrupt is triggered before the all of the above are done. Hence push the devm_request_irq call to the end of the probe. Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index c6fef0a..8c53233 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -410,13 +410,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) return -EINVAL; } - ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, - IRQF_SHARED, "dra7xx-pcie-main", dra7xx); - if (ret) { - dev_err(dev, "failed to request irq\n"); - return ret; - } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) @@ -478,6 +471,13 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_gpio; + ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, + IRQF_SHARED, "dra7xx-pcie-main", dra7xx); + if (ret) { + dev_err(dev, "failed to request irq\n"); + goto err_gpio; + } + return 0; err_gpio: