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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o5si25713579plh.477.2017.11.28.05.28.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 05:28:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=I4HaQ296; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1678D2034A78E; Tue, 28 Nov 2017 05:23:57 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 151B32034A76E for ; Tue, 28 Nov 2017 05:23:55 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id b189so1882555wmd.5 for ; Tue, 28 Nov 2017 05:28:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=afuCnpIYhM0CGZgkD6Cpoc+QlOJwS+9/5tG7XonmIZg=; b=I4HaQ296bXnm3OCx//xdOmbMz780bLBafqkgC+XUEd8T64JeDt6CF65uHqlbQtfQim OZPYw8/3BtU6KVe8DQlABeqaDOyDnHQuEltiUBcjD/uoH6FvRyt9eJ7jHWhanTj/11Ly nGuiWdreINmgzu3bqkNSxMVTxyJZ+2Z/QZWnk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=afuCnpIYhM0CGZgkD6Cpoc+QlOJwS+9/5tG7XonmIZg=; b=ic/aUDjdGIvaUP2FPJGfVVEZFL8kr75ZWJ2bgt26QutVu0mGM0SbJLAOOfP5iPnpVk dYN7v+ySuAqdQ7GFLk6s50OhdcHM6QyYnULxPtjTwVQ43K4uE0a2YpShiHs2a5No+L7N 6fo1txSNhY3y6gP8favu1tTD5RP6RCcbBaOJRiltLpW4wKR+UsT/dgVhxJiv5Da84FEb 4JBJPrueMPUlxWmQWO41Idu10O/3LxXiET7kDvKG57H8vaEJB/QZE6QXzXvv+3PEAYqu r621LAqNkxm1wGpic51YWvwH4t4fa44RnYzO5uCnO3RJ0qtTyJCQEBjRNtoy333Aj3TK oYGg== X-Gm-Message-State: AJaThX6Thmj3GlIRiUhdQ9BsdXgPvIFPyWqn69CFrojpM3sJNlOSrHWj axiITJigGAn0CNruN65VjaDKhEhA2eHOyw== X-Received: by 10.28.9.195 with SMTP id 186mr18924849wmj.122.1511875697214; Tue, 28 Nov 2017 05:28:17 -0800 (PST) Received: from localhost.localdomain ([105.133.187.232]) by smtp.gmail.com with ESMTPSA id x52sm26473685wrb.25.2017.11.28.05.28.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 05:28:15 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Tue, 28 Nov 2017 13:28:07 +0000 Message-Id: <20171128132807.16701-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@socionext.com, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As it turns out, it is surprisingly easy to configure both the NETSEC and eMMC devices as cache coherent for DMA, given that they are both behind the same SMMU which is already configured in passthrough mode. So update the static SMMU configuration to make memory accesses performed by these devices inner shareable, inner/outer writeback cacheable, which makes them cache coherent with the CPUs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ 6 files changed, 34 insertions(+), 2 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 7245240012bc..dd4a7f9baf69 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -597,7 +597,7 @@ [Components.common] NetworkPkg/HttpBootDxe/HttpBootDxe.inf Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf } # diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 7c791de213c7..c9fee5d1f350 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -456,6 +456,7 @@ max-speed = <1000>; max-frame-size = <9000>; phy-handle = <ðphy0>; + dma-coherent; #address-cells = <1>; #size-cells = <0>; @@ -557,6 +558,7 @@ fujitsu,cmd-dat-delay-select; clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; + dma-coherent; status = "disabled"; }; }; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c index 9b1957e99907..1c38b3706f9d 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -185,7 +185,7 @@ RegisterEmmc ( Status = RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, - NonDiscoverableDeviceDmaTypeNonCoherent, + NonDiscoverableDeviceDmaTypeCoherent, NULL, &mSdMmcControllerHandle, 1, diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index b28d05650bb5..acb3e0272d3f 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -181,6 +181,27 @@ I2cEnumerate ( return EFI_SUCCESS; } +#define SMMU_SCR0 0x0 +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22) +#define SMMU_SCR0_MTCFG (0x1 << 20) +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16) + +STATIC +VOID +SmmuEnableCoherentDma ( + VOID + ) +{ + // + // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and + // is configured in passthrough mode by default. Let's set the global memory + // type override as well, so that all memory accesses by these devices are + // inner shareable inner/outer writeback cacheable. + // + MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0, + SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB); +} + STATIC EFI_STATUS EFIAPI @@ -272,5 +293,7 @@ PlatformDxeEntryPoint ( NULL); ASSERT_EFI_ERROR (Status); + SmmuEnableCoherentDma (); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index 3c7bd58866cc..f43adcc8607f 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -65,4 +65,8 @@ #define SYNQUACER_PCIE_BASE 0x58200000 #define SYNQUACER_PCIE_SIZE 0x00200000 +// SCB SMMU +#define SYNQUACER_SCB_SMMU_BASE 0x52E00000 +#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB + #endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index a640b3e0c0d1..1402ecafce4a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)), ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase), FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)), + + // NETSEC/eMMC SMMU + ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE), }; STATIC