From patchwork Fri Nov 17 09:27:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu YiPing X-Patchwork-Id: 119134 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp288351qgn; Fri, 17 Nov 2017 01:28:33 -0800 (PST) X-Google-Smtp-Source: AGs4zMbtPnZi0Msswajt2O70Z++NmTaQIsV3UkYUwE6FZth9sN6fVcbAdVOgJ3cBeoG+K6lrxR6P X-Received: by 10.99.65.131 with SMTP id o125mr4415700pga.83.1510910913529; Fri, 17 Nov 2017 01:28:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510910913; cv=none; d=google.com; s=arc-20160816; b=byNtfG2VWME0He1uYocVN/ButoJWCTnl6/mJs35JHLzuWxwFzt5Q0/6ayZygYKk1v5 iKk8+BsFlIyPCzW7cHF6AKH0hpoW2K0Pfji74NNiwSKda5NGtnCUzkRtMvpcPEFklZA/ 1I0Bmg+G0AmgH22iKGbERU9dJNcoGEbgRnMpog2/+jLxDhphkANiG79NL2YGBMrwEufo oIu1A7bVaPU9rP6ibpmKmNrCfKEcqG4JF45RThyYaH2b3Xu7VYWc6MOJpGrlge6K0IRF DLMYzZ/DvkYZpAZ4zrC2w143MryG7FGqiG/pAaEpkvD/c2uTQqIczH8SKbhdgPwZRKbU OQmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=pdqxj82AgRtx5KJ4MkFbhucw6zWap/ZpeBaktFZyZqI=; b=gylKPRzMukbLzrhwJYF3iyl1jB08Ou7DcUZHWsTAYnNqN4RMhjh5/wExYFE7XV5XLD oEUOMdRq5DEEiGHx87VKt/UBPg7VotT25rHwkYazpZxyePAAXRfnu6jvFRTWi2Y5dfOL AliLi2oAGuCgZ6HYDlUY+Mzb++UIoCs9WwsbWaSVQmCNrt5cDMjmkvzGjt+8bQlMpmmK usDYxDMkLOgJCQHeqc/TIVa2SvHjoPwRpM4nh17W21p3j0U2u4MR0itn/JH8gJJXY0od 8t8/zt3DlPp4wqSESLI1OHlfuj/Jeg60Pfz9wmmJT1VETjQJa8qfSKCrQqdQ6KFcEvLB HJvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f18si2443174pge.329.2017.11.17.01.28.33; Fri, 17 Nov 2017 01:28:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965814AbdKQJ20 (ORCPT + 6 others); Fri, 17 Nov 2017 04:28:26 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11003 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757452AbdKQJ2R (ORCPT ); Fri, 17 Nov 2017 04:28:17 -0500 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLD25367; Fri, 17 Nov 2017 17:28:08 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:27:33 +0800 From: Xu YiPing To: , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 1/3] dt-bindings: clk: Hi3660: Document stub clock Date: Fri, 17 Nov 2017 17:27:30 +0800 Message-ID: <1510910852-2175-2-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> References: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5A0EABA8.0114, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6227f0693cf0d97bad3766b09806765f Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Leo Yan Document the DT binding for stub clock which is used for CPU, GPU and DDR frequency scaling. Acked-by: Rob Herring Signed-off-by: Leo Yan --- Documentation/devicetree/bindings/clock/hi3660-clock.txt | 6 ++++++ include/dt-bindings/clock/hi3660-clock.h | 7 +++++++ 2 files changed, 13 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt index 0035a7e..946da7c 100644 --- a/Documentation/devicetree/bindings/clock/hi3660-clock.txt +++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt @@ -13,12 +13,18 @@ Required Properties: - "hisilicon,hi3660-pmuctrl" - "hisilicon,hi3660-sctrl" - "hisilicon,hi3660-iomcu" + - "hisilicon,hi3660-stub-clk" - reg: physical base address of the controller and length of memory mapped region. - #clock-cells: should be 1. +Optional Properties: + +- mboxes: Phandle to the mailbox for sending message to MCU. + (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info) + Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h index adb768d..75d583e 100644 --- a/include/dt-bindings/clock/hi3660-clock.h +++ b/include/dt-bindings/clock/hi3660-clock.h @@ -208,4 +208,11 @@ #define HI3660_CLK_I2C6_IOMCU 3 #define HI3660_CLK_IOMCU_PERI0 4 +/* clk in stub clock */ +#define HI3660_CLK_STUB_CLUSTER0 0 +#define HI3660_CLK_STUB_CLUSTER1 1 +#define HI3660_CLK_STUB_GPU 2 +#define HI3660_CLK_STUB_DDR 3 +#define HI3660_CLK_STUB_NUM 4 + #endif /* __DTS_HI3660_CLOCK_H */ From patchwork Fri Nov 17 09:27:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu YiPing X-Patchwork-Id: 119135 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp288844qgn; Fri, 17 Nov 2017 01:29:12 -0800 (PST) X-Google-Smtp-Source: AGs4zMbnWvtbacWPaaZsreS5jnLCqYozfvOnS9mnsJ53+EDOrsKGv4OM1zeso4vXdbPfnrdCcP9r X-Received: by 10.101.77.202 with SMTP id q10mr4382370pgt.95.1510910951929; Fri, 17 Nov 2017 01:29:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510910951; cv=none; d=google.com; s=arc-20160816; b=i2uVjS7yT/IenTckhcK4MHJpJiy9YqY/sfeDf8hNo1vs9oncEhrWLDmHHfyzkl9eNa DS2GqaAridE8Pi1MqKsnqIF/6Cy1Epo1B1/iB+lB0H31hXe2JHqEoOMuDc4w7DIea/OL GxT90raXcKU6i6vhLQTcLzRb1Y0321VP6cOpUP+1LQbccqQ6lpWx9oPPqNU/8lV2zYN6 m8DBYWxQKNE5rAlV4u/0jkZr7kqY2k8wxSTsZh+tS3tpA0MfUNHt7feIe3aLoivoUicc NyBO29L503XpBksvEqKD3qWMcLWbz1WdSy2UUhdgnFh9lre/Hyiq3vu1oQ3IhIWHAPAl zszQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rTS3uWf208Ca7V3gv6VV3VLppU0xabZC39xQ3jrVxRY=; b=QYjaOAXj95QKtsyMGe7Whm6SU4MQb6G4kV4LQWNPOtlR0Zj55jLXKpFyGUSHXFNrEg cpHflDCxLdf+wLARaq3xO/oZu/RZo1piGUax5t/AiDBy/eqYPdK1ehIfaKUR3E/18L7P +8SEReRnAeGYYDWZWcbbjpAjybcA5zXwUhYG9ZNWWrhQ9ROspRPm+VqciAAKEFU4ntPz rB7vm2EQSQpiPnn5oRmIzCgMzjYOg4avIBfdLN1iwnEQFOhu/j07iaXyYjwBBg5nhISA PZLnVNPkg/OJfpS736oUQK+/JVSAtRjMo709I6yYQpSEPVv9aIaishlJGWU9t4AqTzZB qwbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a13si2499050pls.824.2017.11.17.01.29.11; Fri, 17 Nov 2017 01:29:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965842AbdKQJ2d (ORCPT + 6 others); Fri, 17 Nov 2017 04:28:33 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11006 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757455AbdKQJ2R (ORCPT ); Fri, 17 Nov 2017 04:28:17 -0500 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLD25366; Fri, 17 Nov 2017 17:28:08 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:27:34 +0800 From: Xu YiPing To: , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks Date: Fri, 17 Nov 2017 17:27:31 +0800 Message-ID: <1510910852-2175-3-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> References: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.5A0EABA8.00F8, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 90b06425e4802363091d330bd64cd396 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kaihua Zhong Hi3660 has four stub clocks, which are big and LITTLE cluster clocks, GPU clock and DDR clock. These clocks ask MCU for frequency scaling by sending message through mailbox. This commit adds support for stub clocks, it requests the dedicated mailbox channel at initialization; then later uses this channel to send message to MCU to execute frequency scaling. The four stub clocks share the same mailbox channel, but every stub clock has its own command id so MCU can distinguish the requirement coming for which clock. A shared memory is used to present effective frequency value, so the clock driver uses I/O mapping for the memory and reads back rate value. Reviewed-by: Leo Yan Signed-off-by: Kai Zhao Signed-off-by: Tao Wang Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- drivers/clk/hisilicon/Kconfig | 6 ++ drivers/clk/hisilicon/Makefile | 1 + drivers/clk/hisilicon/clk-hi3660-stub.c | 186 ++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/clk/hisilicon/clk-hi3660-stub.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index 7098bfd..1bd4355 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -49,3 +49,9 @@ config STUB_CLK_HI6220 default ARCH_HISI help Build the Hisilicon Hi6220 stub clock driver. + +config STUB_CLK_HI3660 + bool "Hi3660 Stub Clock Driver" + depends on COMMON_CLK_HI3660 && MAILBOX + help + Build the Hisilicon Hi3660 stub clock driver. diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 1e4c3dd..0a5b499 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o +obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o diff --git a/drivers/clk/hisilicon/clk-hi3660-stub.c b/drivers/clk/hisilicon/clk-hi3660-stub.c new file mode 100644 index 0000000..607efa4 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3660-stub.c @@ -0,0 +1,186 @@ +/* + * Hisilicon clock driver + * + * Copyright (c) 2013-2017 Hisilicon Limited. + * Copyright (c) 2017 Linaro Limited. + * + * Author: Kai Zhao + * Tao Wang + * Leo Yan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HI3660_STUB_CLOCK_DATA (0x70) +#define MHZ (1000 * 1000) + +#define DEFINE_CLK_STUB(_id, _cmd, _name) \ + { \ + .id = (_id), \ + .cmd = (_cmd), \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &hi3660_stub_clk_ops, \ + .num_parents = 0, \ + .flags = CLK_GET_RATE_NOCACHE, \ + }, \ + }, + +#define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw) + +struct hi3660_stub_clk_chan { + struct mbox_client cl; + struct mbox_chan *mbox; +}; + +struct hi3660_stub_clk { + unsigned int id; + struct clk_hw hw; + unsigned int cmd; + unsigned int msg[8]; + unsigned int rate; +}; + +static void __iomem *freq_reg; +static struct hi3660_stub_clk_chan stub_clk_chan; + +static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct hi3660_stub_clk *stub_clk = to_stub_clk(hw); + + /* + * LPM3 writes back the CPU frequency in shared SRAM so read + * back the frequency. + */ + stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; + return stub_clk->rate; +} + +static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + /* + * LPM3 handles rate rounding so just return whatever + * rate is requested. + */ + return rate; +} + +static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct hi3660_stub_clk *stub_clk = to_stub_clk(hw); + + stub_clk->msg[0] = stub_clk->cmd; + stub_clk->msg[1] = rate / MHZ; + + dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n", + stub_clk->msg[0], stub_clk->msg[1]); + + mbox_send_message(stub_clk_chan.mbox, stub_clk->msg); + mbox_client_txdone(stub_clk_chan.mbox, 0); + + stub_clk->rate = rate; + return 0; +} + +static const struct clk_ops hi3660_stub_clk_ops = { + .recalc_rate = hi3660_stub_clk_recalc_rate, + .round_rate = hi3660_stub_clk_round_rate, + .set_rate = hi3660_stub_clk_set_rate, +}; + +static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = { + DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0") + DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1") + DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d") + DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc") +}; + +static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int idx = clkspec->args[0]; + + if (idx > HI3660_CLK_STUB_NUM) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return &hi3660_stub_clks[idx].hw; +} + +static int hi3660_stub_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + unsigned int i; + int ret; + + /* Use mailbox client without blocking */ + stub_clk_chan.cl.dev = dev; + stub_clk_chan.cl.tx_done = NULL; + stub_clk_chan.cl.tx_block = false; + stub_clk_chan.cl.knows_txdone = false; + + /* Allocate mailbox channel */ + stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0); + if (IS_ERR(stub_clk_chan.mbox)) + return PTR_ERR(stub_clk_chan.mbox); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + freq_reg = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(freq_reg)) + return -ENOMEM; + + freq_reg += HI3660_STUB_CLOCK_DATA; + + for (i = 0; i < HI3660_CLK_STUB_NUM; i++) { + ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw); + if (ret) + return ret; + } + + ret = of_clk_add_hw_provider(pdev->dev.of_node, hi3660_stub_clk_hw_get, + hi3660_stub_clks); + return ret; +} + +static const struct of_device_id hi3660_stub_clk_of_match[] = { + { .compatible = "hisilicon,hi3660-stub-clk", }, + {} +}; + +static struct platform_driver hi3660_stub_clk_driver = { + .probe = hi3660_stub_clk_probe, + .driver = { + .name = "hi3660-stub-clk", + .of_match_table = hi3660_stub_clk_of_match, + }, +}; + +static int __init hi3660_stub_clk_init(void) +{ + return platform_driver_register(&hi3660_stub_clk_driver); +} +subsys_initcall(hi3660_stub_clk_init); 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[209.132.180.67]) by mx.google.com with ESMTP id f18si2443174pge.329.2017.11.17.01.28.32; Fri, 17 Nov 2017 01:28:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965733AbdKQJ2X (ORCPT + 6 others); Fri, 17 Nov 2017 04:28:23 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11004 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757450AbdKQJ2Q (ORCPT ); Fri, 17 Nov 2017 04:28:16 -0500 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLD25368; Fri, 17 Nov 2017 17:28:08 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:27:35 +0800 From: Xu YiPing To: , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 3/3] arm64: dts: Hi3660: Add binding for stub clock Date: Fri, 17 Nov 2017 17:27:32 +0800 Message-ID: <1510910852-2175-4-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> References: <1510910852-2175-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.5A0EABA9.0027, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9933138e73cd16c2f571cb8928cd165a Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kaihua Zhong Add DT binding for Hi3660 stub clock driver. Reviewed-by: Leo Yan Signed-off-by: Kai Zhao Signed-off-by: Tao Wang Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 451b6bf..cbbc7f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -293,6 +293,13 @@ #mbox-cells = <3>; }; + stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; + }; + dual_timer0: timer@fff14000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfff14000 0x0 0x1000>;