From patchwork Wed Apr 29 18:28:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 283775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FE11C83004 for ; Wed, 29 Apr 2020 18:42:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 704DA2083B for ; Wed, 29 Apr 2020 18:42:03 +0000 (UTC) Authentication-Results: mail.kernel.org; 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d="scan'208";a="137935133" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 02:37:05 +0800 IronPort-SDR: a9ynhORNhhTXgl9LKkbsu5JDIfzD+Vt7JpQnY5k6liVQQV5SMK3cuMbpTcg59z7EkGyPa41BCh 5va+J+QRezdZ2zDJ00fpym3/EvH5mgPMA= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 11:27:09 -0700 IronPort-SDR: CcUvOX2SecHENtwkcMGXJ1efoTTs/22a46qxexE1kGCh2W2cR8lifkPlrOSsbe7DMW4HtYiAKm x+QeJZdweUXw== WDCIronportException: Internal Received: from cnf007834.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.253]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 11:37:03 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine Date: Wed, 29 Apr 2020 11:28:45 -0700 Message-Id: <20200429182856.2588202-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com> [ Changed by AF: - Use the SoC's serial property to pass the info to the SoC - Fixup commit title - Rebase on file restructuring ] Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 20 ++++++++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9bfd16d2bb..eb0abcae89 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -34,6 +34,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" @@ -326,6 +327,8 @@ static void sifive_u_machine_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC, &error_abort, NULL); + object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", + &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); @@ -417,6 +420,18 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error * s->start_in_flash = value; } +static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + +static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + static void sifive_u_machine_instance_init(Object *obj) { SiFiveUState *s = RISCV_U_MACHINE(obj); @@ -428,6 +443,11 @@ static void sifive_u_machine_instance_init(Object *obj) "Set on to tell QEMU's ROM to jump to " \ "flash. Otherwise QEMU will jump to DRAM", NULL); + + s->serial = OTP_SERIAL; + object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial, + sifive_u_machine_set_serial, NULL, &s->serial, NULL); + object_property_set_description(obj, "serial", "Board serial number", NULL); } diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a2baa1de5f..16c297ec5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -61,6 +61,7 @@ typedef struct SiFiveUState { int fdt_size; bool start_in_flash; + uint32_t serial; } SiFiveUState; enum { From patchwork Wed Apr 29 18:28:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 283774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFAB0C83000 for ; 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29 Apr 2020 11:37:03 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags Date: Wed, 29 Apr 2020 11:28:46 -0700 Message-Id: <20200429182856.2588202-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , palmerdabbelt@google.com, Richard Henderson , qemu-devel@nongnu.org, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When doing the fist of a two stage lookup (Hypervisor extensions) don't set the current protection flags from the second stage lookup of the base address PTE. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Tested-by: Anup Patel Message-id: 931db85d6890ed4bc2b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com Message-Id: <931db85d6890ed4bc2b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com> --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d3ba9efb02..f36d184b7b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -452,10 +452,11 @@ restart: hwaddr pte_addr; if (two_stage && first_stage) { + int vbase_prot; hwaddr vbase; /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, prot, base, access_type, + get_physical_address(env, &vbase, &vbase_prot, base, access_type, mmu_idx, false, true); pte_addr = vbase + idx * ptesize; From patchwork Wed Apr 29 18:28:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 283773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D86B1C83000 for ; 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29 Apr 2020 11:37:04 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 08/14] riscv: sifive_e: Support changing CPU type Date: Wed, 29 Apr 2020 11:28:50 -0700 Message-Id: <20200429182856.2588202-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Corey Wharton , palmerdabbelt@google.com, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Corey Wharton Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200313193429.8035-2-coreyw7@fb.com Message-Id: <20200313193429.8035-2-coreyw7@fb.com> [ Changes by AF: - Set "cpu-type" from the machine and not SoC ] Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 646553a7c3..b53109521e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", + &error_abort); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); @@ -219,6 +219,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) mc->desc = "RISC-V Board compatible with SiFive E SDK"; mc->init = riscv_sifive_e_init; mc->max_cpus = 1; + mc->default_cpu_type = SIFIVE_E_CPU; } DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) From patchwork Wed Apr 29 18:28:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 283778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB07AC83000 for ; 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29 Apr 2020 11:37:04 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 09/14] target/riscv: Add a sifive-e34 cpu type Date: Wed, 29 Apr 2020 11:28:51 -0700 Message-Id: <20200429182856.2588202-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Corey Wharton , palmerdabbelt@google.com, qemu-devel@nongnu.org, Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Corey Wharton The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20200313193429.8035-3-coreyw7@fb.com Message-Id: <20200313193429.8035-3-coreyw7@fb.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e578239d3..059d71f2c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } +static void rv32imafcu_nommu_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_PMP); +} + #elif defined(TARGET_RISCV64) static void riscv_base64_cpu_init(Object *obj) @@ -610,6 +619,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), /* Depreacted */ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d21addbab..d0e7f5b9c5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") From patchwork Wed Apr 29 18:28:54 2020 Content-Type: text/plain; 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d="scan'208";a="137935156" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 02:37:08 +0800 IronPort-SDR: /pKT4rYuVgi5xIK10DKDcNZPHR/dCwUuVmf0o25JXK2MOCCc5JgT8OCJTZDx0DUqqvjA5n5v3w S1ObzZGN+4DTSfS9a6nfQ1Q5nucr/T/y8= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 11:27:12 -0700 IronPort-SDR: /ylXJcU/lduVDPmJK/b0Zxt1cLPHkpVDjXJR40jSeY39WHzTbIJh/pC+gljo5TJm2gUHCOfCZA wwQ7imovOTLw== WDCIronportException: Internal Received: from cnf007834.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.253]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 11:37:06 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Date: Wed, 29 Apr 2020 11:28:54 -0700 Message-Id: <20200429182856.2588202-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Anup Patel , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel This patch adds an optional function pointer, "sym_cb", to riscv_load_firmware() which provides the possibility to access the symbol table during kernel loading. The pointer is ignored, if supplied with flat (non-elf) firmware image. The Spike board requires it locate the HTIF symbols from firmware ELF passed via "-bios" option. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20200427080644.168461-2-anup.patel@wdc.com Message-Id: <20200427080644.168461-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 13 ++++++++----- hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 6 ++++-- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index b8e765277d..726300a171 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,8 @@ void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, - hwaddr firmware_load_addr) + hwaddr firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename = NULL; @@ -76,7 +77,7 @@ void riscv_find_and_load_firmware(MachineState *machine, if (firmware_filename) { /* If not "none" load the firmware */ - riscv_load_firmware(firmware_filename, firmware_load_addr); + riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb); g_free(firmware_filename); } } @@ -96,12 +97,14 @@ char *riscv_find_firmware(const char *firmware_filename) } target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr firmware_load_addr) + hwaddr firmware_load_addr, + symbol_fn_t sym_cb) { uint64_t firmware_entry, firmware_start, firmware_end; - if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry, - &firmware_start, &firmware_end, NULL, 0, EM_RISCV, 1, 0) > 0) { + if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, + &firmware_entry, &firmware_start, &firmware_end, NULL, + 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { return firmware_entry; } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0dd0efaa68..cfd6416b19 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -352,7 +352,7 @@ static void sifive_u_machine_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SIFIVE_U_DRAM].base); + memmap[SIFIVE_U_DRAM].base, NULL); if (machine->kernel_filename) { uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c621a970aa..daae3ebdbb 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -511,7 +511,7 @@ static void riscv_virt_board_init(MachineState *machine) mask_rom); riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[VIRT_DRAM].base); + memmap[VIRT_DRAM].base, NULL); if (machine->kernel_filename) { uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index df80051fbc..474a940ad5 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -24,10 +24,12 @@ void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, - hwaddr firmware_load_addr); + hwaddr firmware_load_addr, + symbol_fn_t sym_cb); char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr firmware_load_addr); + hwaddr firmware_load_addr, + symbol_fn_t sym_cb); target_ulong riscv_load_kernel(const char *kernel_filename, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, From patchwork Wed Apr 29 18:28:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 283776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64D49C83004 for ; Wed, 29 Apr 2020 18:41:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C44A2072A for ; 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d="scan'208";a="137935158" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 02:37:08 +0800 IronPort-SDR: yz62U3AD2XWTbk+d303+HyUwcVxT6MrpFTZg0pQAvK75bmKvIO17nsqy1j4po1JwYUehj6Oh++ +xhWvKQeOaP5/9615QUWGdGZD5ANzKgp4= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 11:27:12 -0700 IronPort-SDR: 17OGOyw7LHB3vRJc40YxRHVDy/e+uUBcGlwJkMNaRsIWJ7F4609RoBvV/h/E0VNOgJOmIy2hx6 ZiXrP6+EFZTg== WDCIronportException: Internal Received: from cnf007834.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.253]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 11:37:06 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option Date: Wed, 29 Apr 2020 11:28:55 -0700 Message-Id: <20200429182856.2588202-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Anup Patel , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel This patch extends Spike machine support to allow loading OpenSBI firmware (fw_jump.elf) separately using -bios option. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20200427080644.168461-3-anup.patel@wdc.com Message-Id: <20200427080644.168461-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 98697a244e..e7908b88fe 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -45,6 +45,12 @@ #include +#if defined(TARGET_RISCV32) +# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" +#else +# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf" +#endif + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -187,8 +193,24 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); + riscv_find_and_load_firmware(machine, BIOS_FILENAME, + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, + htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } } /* reset vector */