From patchwork Sun May 31 16:24:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 281600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0883C433E0 for ; Sun, 31 May 2020 16:29:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A8DA720723 for ; Sun, 31 May 2020 16:29:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A8DA720723 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQph-0003Gm-0A for qemu-devel@archiver.kernel.org; Sun, 31 May 2020 12:29:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfQlM-0004Dh-GL for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:40 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:48255) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQlK-0004K0-0D for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:40 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id 1E93DECD38; Mon, 1 Jun 2020 01:24:32 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 6EC0A1C0DB6; Mon, 1 Jun 2020 01:24:32 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 02/10] hw/timer: Renesas 8bit timer module. Date: Mon, 1 Jun 2020 01:24:19 +0900 Message-Id: <20200531162427.57410-3-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200531162427.57410-1-ysato@users.sourceforge.jp> References: <20200531162427.57410-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/31 12:24:33 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_SOFTFAIL=0.665, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" 8bit or 16bit timer. This implementation support only internal clock mode. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_8timer.h | 61 ++++ hw/timer/renesas_8timer.c | 466 ++++++++++++++++++++++++++++++ hw/timer/Kconfig | 3 + hw/timer/Makefile.objs | 2 + 4 files changed, 532 insertions(+) create mode 100644 include/hw/timer/renesas_8timer.h create mode 100644 hw/timer/renesas_8timer.c diff --git a/include/hw/timer/renesas_8timer.h b/include/hw/timer/renesas_8timer.h new file mode 100644 index 0000000000..7e05c7be97 --- /dev/null +++ b/include/hw/timer/renesas_8timer.h @@ -0,0 +1,61 @@ +/* + * Renesas 8bit timer Object + * + * Copyright (c) 2018 Yoshinori Sato + * + * This code is licensed under the GPL version 2 or later. + * + */ + +#ifndef HW_RENESAS_TMR_H +#define HW_RENESAS_TMR_H + +#include "hw/sysbus.h" + +#define TYPE_RENESAS_8TMR "renesas-8tmr" +#define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_8TMR) + +enum timer_event { + cmia, cmib, ovi, wovi, + TMR_NR_EVENTS, +}; + +enum { + TMR_CH = 2, + TMR_NR_COR = 2, + TMR_NR_IRQ = 3, +}; + +enum { + IRQ_CMIA, IRQ_CMIB, IRQ_OVI, +}; + +struct RTMRState; + +struct channel_8tmr { + uint16_t cnt; + uint16_t cor[TMR_NR_COR]; + uint8_t tcr; + uint8_t tccr; + uint8_t tcsr; + qemu_irq irq[TMR_NR_IRQ]; + QEMUTimer *timer; + int64_t base; + int64_t next; + int64_t clk; + enum timer_event event; + int id; + struct RTMRState *tmrp; + bool word; +}; + +typedef struct RTMRState { + SysBusDevice parent_obj; + + uint64_t input_freq; + MemoryRegion memory; + + struct channel_8tmr ch[TMR_CH]; +} RTMRState; + +#endif diff --git a/hw/timer/renesas_8timer.c b/hw/timer/renesas_8timer.c new file mode 100644 index 0000000000..b545ba0e2b --- /dev/null +++ b/hw/timer/renesas_8timer.c @@ -0,0 +1,466 @@ +/* + * Renesas 8bit timer + * + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware + * (Rev.1.40 R01UH0033EJ0140) + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/timer/renesas_8timer.h" +#include "migration/vmstate.h" +#include "qemu/error-report.h" + +REG8(TCR, 0) + FIELD(TCR, CCLR, 3, 2) + FIELD(TCR, OVIE, 5, 1) + FIELD(TCR, CMIEA, 6, 1) + FIELD(TCR, CMIEB, 7, 1) +REG8(TCSR, 2) + FIELD(TCSR, OSA, 0, 2) + FIELD(TCSR, OSB, 2, 2) + FIELD(TCSR, ADTE, 4, 1) +REG8(TCORA, 4) +REG8(TCORB, 6) +REG8(TCNT, 8) +REG8(TCCR, 10) + FIELD(TCCR, CKS, 0, 3) + FIELD(TCCR, CSS, 3, 2) + FIELD(TCCR, TMRIS, 7, 1) + +#define CLK_EVT -1 + +static void update_clk(RTMRState *tmr, int ch) +{ + int64_t t; + static const int divlist[] = {1, 2, 8, 32, 64, 1024, 8192, 0}; + switch (FIELD_EX8(tmr->ch[ch].tccr, TCCR, CSS)) { + case 0: + qemu_log_mask(LOG_UNIMP, + "renesas_8timer: External clock not implemented."); + tmr->ch[ch].clk = 0; + break; + case 1: + /* Internal clock */ + t = divlist[FIELD_EX8(tmr->ch[ch].tccr, TCCR, CKS)]; + if (t > 0) { + tmr->ch[ch].clk = tmr->input_freq / t; + tmr->ch[ch].clk = NANOSECONDS_PER_SECOND / t; + } else { + tmr->ch[ch].clk = 0; + } + break; + case 2: + qemu_log_mask(LOG_UNIMP, + "renesas_8timer: CSS undefined."); + tmr->ch[ch].clk = 0; + break; + case 3: + /* Event count */ + tmr->ch[ch].clk = CLK_EVT; + break; + } +} + +static uint16_t catreg(uint8_t hi, uint8_t lo) +{ + uint16_t ret = 0; + ret = deposit32(ret, 8, 8, hi); + ret = deposit32(ret, 0, 8, lo); + return ret; +} + +static int is_clr(uint8_t tcr, int event) +{ + return FIELD_EX8(tcr, TCR, CCLR) == (event + 1); +} + +static int is_irq(uint8_t tcr, int event) +{ + switch (event) { + case cmia: + return FIELD_EX8(tcr, TCR, CMIEA); + case cmib: + return FIELD_EX8(tcr, TCR, CMIEB); + case ovi: + return FIELD_EX8(tcr, TCR, OVIE); + default: + g_assert_not_reached(); + } +} + +static void set_next_event(RTMRState *tmr, int ch) +{ + int64_t next = 0; + int evt; + int cor; + int min; + if (ch == 1 && tmr->ch[ch].word) { + /* 16bit count mode */ + next = 0x10000 - catreg(tmr->ch[0].cnt, tmr->ch[1].cnt); + next *= tmr->ch[1].clk; + tmr->ch[0].event = tmr->ch[1].event = wovi; + } else if (tmr->ch[1].clk > 0) { + min = 0x101; + for (evt = cmia; evt < TMR_NR_EVENTS - 1; evt++) { + cor = (evt < TMR_NR_COR) ? (tmr->ch[ch].cor[evt]) : 0xff; + /* event happend compare match +1 */ + cor++; + if (tmr->ch[ch].cnt < cor) { + if (evt < TMR_NR_COR && + !is_clr(tmr->ch[ch].tcr, evt) && + !is_irq(tmr->ch[ch].tcr, evt)) { + /* no event happend */ + continue; + } + if (min > cor) { + min = cor; + next = cor - tmr->ch[ch].cnt; + next *= tmr->ch[ch].clk; + tmr->ch[ch].event = evt; + } + } + } + } + if (next > 0) { + tmr->ch[ch].base = tmr->ch[ch].next; + tmr->ch[ch].next += next; + timer_mod(tmr->ch[ch].timer, tmr->ch[ch].next); + } else { + timer_del(tmr->ch[ch].timer); + } +} + +static void event_countup(struct channel_8tmr *ch) +{ + int evt; + int cor; + + ch->cnt++; + for (evt = cmia; evt < TMR_NR_COR - 1; evt++) { + cor = ch->cor[evt]; + if (ch->cnt == (cor + 1) && is_clr(ch->tcr, evt)) { + ch->cnt = 0; + } + if (ch->cnt == cor && is_irq(ch->tcr, evt)) { + qemu_irq_pulse(ch->irq[evt]); + } + } + if (ch->cnt == 0x100) { + ch->cnt = 0; + if (is_irq(ch->tcr, ovi)) { + qemu_irq_pulse(ch->irq[IRQ_OVI]); + } + } +} + +static void timer_event(void *opaque) +{ + struct channel_8tmr *ch = opaque; + RTMRState *tmr = ch->tmrp; + + switch (ch->event) { + case cmia: + if (ch->id == 0 && tmr->ch[1].clk == CLK_EVT) { + /* CH1 event count */ + event_countup(&tmr->ch[1]); + } + /* Falls through. */ + case cmib: + if (FIELD_EX8(ch->tcr, TCR, CCLR) == (ch->event + 1)) { + ch->cnt = 0; + } else { + ch->cnt = ch->cor[ch->event] + 1; + } + if (is_irq(ch->tcr, ch->event)) { + qemu_irq_pulse(ch->irq[ch->event]); + } + break; + case ovi: + ch->cnt = 0; + if (is_irq(ch->tcr, ovi)) { + qemu_irq_pulse(ch->irq[IRQ_OVI]); + } + if (ch->id == 1 && tmr->ch[0].clk == CLK_EVT) { + /* CH0 event count */ + event_countup(&tmr->ch[0]); + } + break; + case wovi: + tmr->ch[0].cnt = tmr->ch[1].cnt = 0; + if (is_irq(tmr->ch[0].tcr, ovi)) { + qemu_irq_pulse(tmr->ch[0].irq[IRQ_OVI]); + } + break; + default: + g_assert_not_reached(); + } + set_next_event(tmr, ch->id); +} + +static uint16_t read_tcnt(RTMRState *tmr, unsigned int size, int ch) +{ + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int64_t delta; + uint8_t ret[2]; + int i; + + switch (size) { + case 1: + if (tmr->ch[ch].clk > 0) { + delta = now - tmr->ch[ch].base; + delta /= tmr->ch[ch].clk; + } else { + delta = 0; + } + return tmr->ch[ch].cnt + delta; + case 2: + if (tmr->ch[1].word) { + /* 16bit count mode */ + delta = now - tmr->ch[1].base; + delta /= tmr->ch[1].clk; + return catreg(tmr->ch[0].cnt, tmr->ch[1].cnt) + delta; + } else { + for (i = 0; i < TMR_CH; i++) { + if (tmr->ch[ch].clk > 0) { + delta = now - tmr->ch[ch].base; + delta /= tmr->ch[ch].clk; + } else { + delta = 0; + } + ret[i] = tmr->ch[i].cnt + delta; + } + return catreg(ret[0], ret[1]); + } + default: + g_assert_not_reached(); + } +} + +static int validate_access(hwaddr addr, unsigned int size) +{ + /* Byte access always OK */ + if (size == 1) { + return 1; + } + return (addr >= A_TCORA); +} + +static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned int size) +{ + RTMRState *tmr = opaque; + int ch = addr & 1; + int cor; + + if (!validate_access(addr, size)) { + qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%" + HWADDR_PRIX "\n", addr); + return UINT64_MAX; + } + switch (addr & ~1) { + case A_TCR: + return tmr->ch[ch].tcr; + case A_TCSR: + return tmr->ch[ch].tcsr; + case A_TCORA: + case A_TCORB: + cor = (addr & 2) >> 1; + if (size == 1) { + return tmr->ch[ch].cor[cor]; + } else { + return catreg(tmr->ch[0].cor[cor], tmr->ch[1].cor[cor]); + } + case A_TCNT: + return read_tcnt(tmr, size, ch); + case A_TCCR: + if (size == 1) { + return tmr->ch[ch].tccr; + } else { + return catreg(tmr->ch[0].tccr, tmr->ch[1].tccr); + } + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", addr); + break; + } + return UINT64_MAX; +} + +static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + RTMRState *tmr = opaque; + int ch = addr & 1; + int cor; + int64_t now; + + if (!validate_access(addr, size)) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_tmr: Invalid write size 0x%" HWADDR_PRIX + "\n", addr); + return; + } + switch (addr & ~1) { + case A_TCR: + tmr->ch[ch].tcr = val; + break; + case A_TCSR: + if (ch == 1) { + val = FIELD_DP8(val, TCSR, ADTE, 1); + } + tmr->ch[ch].tcsr = val; + break; + case A_TCORA: + case A_TCORB: + cor = (addr & 2) >> 1; + if (size == 1) { + tmr->ch[ch].cor[cor] = val; + } else { + tmr->ch[0].cor[cor] = extract32(val, 0, 8); + tmr->ch[1].cor[cor] = extract32(val, 8, 8); + } + break; + case A_TCNT: + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + if (size == 1) { + tmr->ch[ch].base = now; + tmr->ch[ch].cnt = val; + } else { + tmr->ch[0].base = tmr->ch[1].base = now; + tmr->ch[0].cnt = extract32(val, 0, 8); + tmr->ch[1].cnt = extract32(val, 8, 8); + } + break; + case A_TCCR: + val &= ~0x6060; + if (size == 1) { + tmr->ch[ch].tccr = val; + update_clk(tmr, ch); + } else { + tmr->ch[0].tccr = extract32(val, 0, 8); + tmr->ch[1].tccr = extract32(val, 8, 8); + update_clk(tmr, 0); + update_clk(tmr, 1); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX + " not implemented\n", addr); + return; + } + /* + * If some conditions are met, + * the event does not occur until the 16-bit counter overflows. + */ + tmr->ch[1].word = (tmr->ch[0].clk == -1 && tmr->ch[1].clk > 0 && + (tmr->ch[0].tcr & 0xe8) == 0x00 && + (tmr->ch[0].tcr & 0xf8) == 0x00); + if (size == 1) { + set_next_event(tmr, ch); + } else { + set_next_event(tmr, 0); + set_next_event(tmr, 1); + } +} + +static const MemoryRegionOps tmr_ops = { + .write = tmr_write, + .read = tmr_read, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 2, + }, +}; + +static void rtmr_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *d = SYS_BUS_DEVICE(dev); + RTMRState *tmr = RTMR(dev); + int i; + + if (tmr->input_freq == 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_8tmr: input-freq property must be set."); + return; + } + + memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops, + tmr, "renesas-8tmr", 0x10); + sysbus_init_mmio(d, &tmr->memory); + + for (i = 0; i < TMR_CH; i++) { + sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_CMIA]); + sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_CMIB]); + sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_OVI]); + tmr->ch[i].id = i; + tmr->ch[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + timer_event, &tmr->ch[i]); + tmr->ch[i].tmrp = tmr; + tmr->ch[i].tcr = 0x00; + tmr->ch[i].tcsr = (i == 0) ? 0x00 : 0x10; + tmr->ch[i].cnt = 0x00; + tmr->ch[i].cor[0] = 0xff; + tmr->ch[i].cor[1] = 0xff; + tmr->ch[i].tccr = 0x00; + } +} + +static const VMStateDescription vmstate_rtmr = { + .name = "renesas-8tmr", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + +static Property rtmr_properties[] = { + DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rtmr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_rtmr; + dc->realize = rtmr_realize; + device_class_set_props(dc, rtmr_properties); +} + +static const TypeInfo rtmr_info = { + .name = TYPE_RENESAS_8TMR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(RTMRState), + .class_init = rtmr_class_init, +}; + +static void rtmr_register_types(void) +{ + type_register_static(&rtmr_info); +} + +type_init(rtmr_register_types) diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 59b3f44d69..93f62999eb 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -35,3 +35,6 @@ config CMSDK_APB_TIMER config CMSDK_APB_DUALTIMER bool select PTIMER + +config RENESAS_8TMR + bool diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dece235fd7..9ea88b964d 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -35,3 +35,5 @@ common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o common-obj-$(CONFIG_MSF2) += mss-timer.o common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o + +common-obj-$(CONFIG_RENESAS_8TMR) += renesas_8timer.o From patchwork Sun May 31 16:24:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 281602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DB57C433E0 for ; Sun, 31 May 2020 16:27:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C64A20723 for ; Sun, 31 May 2020 16:27:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C64A20723 Authentication-Results: mail.kernel.org; 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Mon, 1 Jun 2020 01:24:34 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id F3A8D1C05D2; Mon, 1 Jun 2020 01:24:33 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 06/10] Add rx-softmmu Date: Mon, 1 Jun 2020 01:24:23 +0900 Message-Id: <20200531162427.57410-7-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200531162427.57410-1-ysato@users.sourceforge.jp> References: <20200531162427.57410-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/31 12:24:33 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_SOFTFAIL=0.665, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Yoshinori Sato Message-Id: <20190607091116.49044-17-ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson pick ed65c02993 target/rx: Add RX to SysEmuTarget pick 01372568ae tests: Add rx to machine-none-test.c [PMD: Squashed patches from Richard Henderson modifying qapi/common.json and tests/machine-none-test.c] Signed-off-by: Philippe Mathieu-Daudé --- default-configs/rx-softmmu.mak | 1 + hw/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak index 7c4eb2c1a0..a3eecefb11 100644 --- a/default-configs/rx-softmmu.mak +++ b/default-configs/rx-softmmu.mak @@ -1,2 +1,3 @@ # Default configuration for rx-softmmu +CONFIG_RX_VIRT=y diff --git a/hw/Kconfig b/hw/Kconfig index ecf491bf04..62f9ebdc22 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -55,6 +55,7 @@ source nios2/Kconfig source openrisc/Kconfig source ppc/Kconfig source riscv/Kconfig +source rx/Kconfig source s390x/Kconfig source sh4/Kconfig source sparc/Kconfig From patchwork Sun May 31 16:24:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 281601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A95DC433E0 for ; Sun, 31 May 2020 16:27:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4152C20723 for ; Sun, 31 May 2020 16:27:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4152C20723 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQoN-00012K-HL for qemu-devel@archiver.kernel.org; Sun, 31 May 2020 12:27:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfQlM-0004Er-Ux for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:40 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:58735) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQlJ-0004KC-Ux for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:40 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id 9475FEB8D4; Mon, 1 Jun 2020 01:24:34 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 421891C0DB3; Mon, 1 Jun 2020 01:24:34 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 07/10] hw/sh4: Convert renesas_sci. Date: Mon, 1 Jun 2020 01:24:24 +0900 Message-Id: <20200531162427.57410-8-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200531162427.57410-1-ysato@users.sourceforge.jp> References: <20200531162427.57410-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/31 12:24:33 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_SOFTFAIL=0.665, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Using new implementation SCI module. Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 11 ----------- hw/sh4/sh7750.c | 45 +++++++++++++++++++++++++++++++++++++++++---- hw/sh4/Kconfig | 1 + 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 767a2df7e2..e184b4b300 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -38,17 +38,6 @@ void tmu012_init(struct MemoryRegion *sysmem, hwaddr base, qemu_irq ch2_irq0, qemu_irq ch2_irq1); -/* sh_serial.c */ -#define SH_SERIAL_FEAT_SCIF (1 << 0) -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source); - /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index d660714443..150d3029f7 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -24,12 +24,15 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "sysemu/sysemu.h" #include "sh7750_regs.h" #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" +#include "hw/char/renesas_sci.h" +#include "hw/qdev-properties.h" #include "cpu.h" #include "exec/exec-all.h" @@ -752,6 +755,40 @@ static const MemoryRegionOps sh7750_mmct_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem, + hwaddr base, int feat, + uint32_t freq, Chardev *chr, + qemu_irq eri_source, + qemu_irq rxi_source, + qemu_irq txi_source, + qemu_irq tei_source, + qemu_irq bri_source) +{ + DeviceState *dev; + SysBusDevice *sci; + + dev = qdev_create(NULL, TYPE_RENESAS_SCI); + + sci = SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + qdev_prop_set_uint64(dev, "input-freq", freq); + qdev_prop_set_int32(dev, "feature", feat); + qdev_prop_set_int32(dev, "register-size", 32); + qdev_init_nofail(dev); + sysbus_mmio_map(sci, 0, base); + sysbus_mmio_map(sci, 1, P4ADDR(base)); + sysbus_mmio_map(sci, 2, A7ADDR(base)); + sysbus_connect_irq(sci, 0, eri_source); + sysbus_connect_irq(sci, 1, rxi_source); + sysbus_connect_irq(sci, 2, txi_source); + if (feat == SCI_FEAT_SCI) { + sysbus_connect_irq(sci, 3, tei_source); + } else { + sysbus_connect_irq(sci, 3, bri_source); + } +} + SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; @@ -800,15 +837,15 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) cpu->env.intc_handle = &s->intc; - sh_serial_init(sysmem, 0x1fe00000, - 0, s->periph_freq, serial_hd(0), + sh_serial_init(s, sysmem, 0x1fe00000, + SCI_FEAT_SCI, s->periph_freq, serial_hd(0), s->intc.irqs[SCI1_ERI], s->intc.irqs[SCI1_RXI], s->intc.irqs[SCI1_TXI], s->intc.irqs[SCI1_TEI], NULL); - sh_serial_init(sysmem, 0x1fe80000, - SH_SERIAL_FEAT_SCIF, + sh_serial_init(s, sysmem, 0x1fe80000, + SCI_FEAT_SCIF, s->periph_freq, serial_hd(1), s->intc.irqs[SCIF_ERI], s->intc.irqs[SCIF_RXI], diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig index 4cbce3a0ed..38509b7e65 100644 --- a/hw/sh4/Kconfig +++ b/hw/sh4/Kconfig @@ -22,3 +22,4 @@ config SH7750 config SH4 bool select PTIMER + select RENESAS_SCI From patchwork Sun May 31 16:24:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 281599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F2CC433E0 for ; Sun, 31 May 2020 16:31:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1DD8D20723 for ; Sun, 31 May 2020 16:31:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1DD8D20723 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQs0-0005wl-Dq for qemu-devel@archiver.kernel.org; Sun, 31 May 2020 12:31:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jfQlQ-0004Ly-Lo for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:44 -0400 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:36015) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQlP-0004KE-CK for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:44 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id AD8E5105239; Mon, 1 Jun 2020 01:24:34 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 7417A1C0DB6; Mon, 1 Jun 2020 01:24:34 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 08/10] hw/char: remove sh_serial.c Date: Mon, 1 Jun 2020 01:24:25 +0900 Message-Id: <20200531162427.57410-9-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200531162427.57410-1-ysato@users.sourceforge.jp> References: <20200531162427.57410-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.13; envelope-from=ysato@users.sourceforge.jp; helo=mail01.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/31 12:24:33 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_SOFTFAIL=0.665, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" SH4 SCI module convert to renesas_sci.c. This file is obsolute. Signed-off-by: Yoshinori Sato --- hw/char/sh_serial.c | 431 -------------------------------------------- 1 file changed, 431 deletions(-) delete mode 100644 hw/char/sh_serial.c diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c deleted file mode 100644 index 167f4d8cb9..0000000000 --- a/hw/char/sh_serial.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * QEMU SCI/SCIF serial port emulation - * - * Copyright (c) 2007 Magnus Damm - * - * Based on serial.c - QEMU 16450 UART emulation - * Copyright (c) 2003-2004 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/irq.h" -#include "hw/sh4/sh.h" -#include "chardev/char-fe.h" -#include "qapi/error.h" -#include "qemu/timer.h" - -//#define DEBUG_SERIAL - -#define SH_SERIAL_FLAG_TEND (1 << 0) -#define SH_SERIAL_FLAG_TDE (1 << 1) -#define SH_SERIAL_FLAG_RDF (1 << 2) -#define SH_SERIAL_FLAG_BRK (1 << 3) -#define SH_SERIAL_FLAG_DR (1 << 4) - -#define SH_RX_FIFO_LENGTH (16) - -typedef struct { - MemoryRegion iomem; - MemoryRegion iomem_p4; - MemoryRegion iomem_a7; - uint8_t smr; - uint8_t brr; - uint8_t scr; - uint8_t dr; /* ftdr / tdr */ - uint8_t sr; /* fsr / ssr */ - uint16_t fcr; - uint8_t sptr; - - uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ - uint8_t rx_cnt; - uint8_t rx_tail; - uint8_t rx_head; - - int freq; - int feat; - int flags; - int rtrg; - - CharBackend chr; - QEMUTimer *fifo_timeout_timer; - uint64_t etu; /* Elementary Time Unit (ns) */ - - qemu_irq eri; - qemu_irq rxi; - qemu_irq txi; - qemu_irq tei; - qemu_irq bri; -} sh_serial_state; - -static void sh_serial_clear_fifo(sh_serial_state * s) -{ - memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); - s->rx_cnt = 0; - s->rx_head = 0; - s->rx_tail = 0; -} - -static void sh_serial_write(void *opaque, hwaddr offs, - uint64_t val, unsigned size) -{ - sh_serial_state *s = opaque; - unsigned char ch; - -#ifdef DEBUG_SERIAL - printf("sh_serial: write offs=0x%02x val=0x%02x\n", - offs, val); -#endif - switch(offs) { - case 0x00: /* SMR */ - s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); - return; - case 0x04: /* BRR */ - s->brr = val; - return; - case 0x08: /* SCR */ - /* TODO : For SH7751, SCIF mask should be 0xfb. */ - s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); - if (!(val & (1 << 5))) - s->flags |= SH_SERIAL_FLAG_TEND; - if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { - qemu_set_irq(s->txi, val & (1 << 7)); - } - if (!(val & (1 << 6))) { - qemu_set_irq(s->rxi, 0); - } - return; - case 0x0c: /* FTDR / TDR */ - if (qemu_chr_fe_backend_connected(&s->chr)) { - ch = val; - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&s->chr, &ch, 1); - } - s->dr = val; - s->flags &= ~SH_SERIAL_FLAG_TDE; - return; -#if 0 - case 0x14: /* FRDR / RDR */ - ret = 0; - break; -#endif - } - if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { - case 0x10: /* FSR */ - if (!(val & (1 << 6))) - s->flags &= ~SH_SERIAL_FLAG_TEND; - if (!(val & (1 << 5))) - s->flags &= ~SH_SERIAL_FLAG_TDE; - if (!(val & (1 << 4))) - s->flags &= ~SH_SERIAL_FLAG_BRK; - if (!(val & (1 << 1))) - s->flags &= ~SH_SERIAL_FLAG_RDF; - if (!(val & (1 << 0))) - s->flags &= ~SH_SERIAL_FLAG_DR; - - if (!(val & (1 << 1)) || !(val & (1 << 0))) { - if (s->rxi) { - qemu_set_irq(s->rxi, 0); - } - } - return; - case 0x18: /* FCR */ - s->fcr = val; - switch ((val >> 6) & 3) { - case 0: - s->rtrg = 1; - break; - case 1: - s->rtrg = 4; - break; - case 2: - s->rtrg = 8; - break; - case 3: - s->rtrg = 14; - break; - } - if (val & (1 << 1)) { - sh_serial_clear_fifo(s); - s->sr &= ~(1 << 1); - } - - return; - case 0x20: /* SPTR */ - s->sptr = val & 0xf3; - return; - case 0x24: /* LSR */ - return; - } - } - else { - switch(offs) { -#if 0 - case 0x0c: - ret = s->dr; - break; - case 0x10: - ret = 0; - break; -#endif - case 0x1c: - s->sptr = val & 0x8f; - return; - } - } - - fprintf(stderr, "sh_serial: unsupported write to 0x%02" - HWADDR_PRIx "\n", offs); - abort(); -} - -static uint64_t sh_serial_read(void *opaque, hwaddr offs, - unsigned size) -{ - sh_serial_state *s = opaque; - uint32_t ret = ~0; - -#if 0 - switch(offs) { - case 0x00: - ret = s->smr; - break; - case 0x04: - ret = s->brr; - break; - case 0x08: - ret = s->scr; - break; - case 0x14: - ret = 0; - break; - } -#endif - if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { - case 0x00: /* SMR */ - ret = s->smr; - break; - case 0x08: /* SCR */ - ret = s->scr; - break; - case 0x10: /* FSR */ - ret = 0; - if (s->flags & SH_SERIAL_FLAG_TEND) - ret |= (1 << 6); - if (s->flags & SH_SERIAL_FLAG_TDE) - ret |= (1 << 5); - if (s->flags & SH_SERIAL_FLAG_BRK) - ret |= (1 << 4); - if (s->flags & SH_SERIAL_FLAG_RDF) - ret |= (1 << 1); - if (s->flags & SH_SERIAL_FLAG_DR) - ret |= (1 << 0); - - if (s->scr & (1 << 5)) - s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; - - break; - case 0x14: - if (s->rx_cnt > 0) { - ret = s->rx_fifo[s->rx_tail++]; - s->rx_cnt--; - if (s->rx_tail == SH_RX_FIFO_LENGTH) - s->rx_tail = 0; - if (s->rx_cnt < s->rtrg) - s->flags &= ~SH_SERIAL_FLAG_RDF; - } - break; - case 0x18: - ret = s->fcr; - break; - case 0x1c: - ret = s->rx_cnt; - break; - case 0x20: - ret = s->sptr; - break; - case 0x24: - ret = 0; - break; - } - } - else { - switch(offs) { -#if 0 - case 0x0c: - ret = s->dr; - break; - case 0x10: - ret = 0; - break; - case 0x14: - ret = s->rx_fifo[0]; - break; -#endif - case 0x1c: - ret = s->sptr; - break; - } - } -#ifdef DEBUG_SERIAL - printf("sh_serial: read offs=0x%02x val=0x%x\n", - offs, ret); -#endif - - if (ret & ~((1 << 16) - 1)) { - fprintf(stderr, "sh_serial: unsupported read from 0x%02" - HWADDR_PRIx "\n", offs); - abort(); - } - - return ret; -} - -static int sh_serial_can_receive(sh_serial_state *s) -{ - return s->scr & (1 << 4); -} - -static void sh_serial_receive_break(sh_serial_state *s) -{ - if (s->feat & SH_SERIAL_FEAT_SCIF) - s->sr |= (1 << 4); -} - -static int sh_serial_can_receive1(void *opaque) -{ - sh_serial_state *s = opaque; - return sh_serial_can_receive(s); -} - -static void sh_serial_timeout_int(void *opaque) -{ - sh_serial_state *s = opaque; - - s->flags |= SH_SERIAL_FLAG_RDF; - if (s->scr & (1 << 6) && s->rxi) { - qemu_set_irq(s->rxi, 1); - } -} - -static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) -{ - sh_serial_state *s = opaque; - - if (s->feat & SH_SERIAL_FEAT_SCIF) { - int i; - for (i = 0; i < size; i++) { - if (s->rx_cnt < SH_RX_FIFO_LENGTH) { - s->rx_fifo[s->rx_head++] = buf[i]; - if (s->rx_head == SH_RX_FIFO_LENGTH) { - s->rx_head = 0; - } - s->rx_cnt++; - if (s->rx_cnt >= s->rtrg) { - s->flags |= SH_SERIAL_FLAG_RDF; - if (s->scr & (1 << 6) && s->rxi) { - timer_del(s->fifo_timeout_timer); - qemu_set_irq(s->rxi, 1); - } - } else { - timer_mod(s->fifo_timeout_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); - } - } - } - } else { - s->rx_fifo[0] = buf[0]; - } -} - -static void sh_serial_event(void *opaque, QEMUChrEvent event) -{ - sh_serial_state *s = opaque; - if (event == CHR_EVENT_BREAK) - sh_serial_receive_break(s); -} - -static const MemoryRegionOps sh_serial_ops = { - .read = sh_serial_read, - .write = sh_serial_write, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source) -{ - sh_serial_state *s; - - s = g_malloc0(sizeof(sh_serial_state)); - - s->feat = feat; - s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; - s->rtrg = 1; - - s->smr = 0; - s->brr = 0xff; - s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ - s->sptr = 0; - - if (feat & SH_SERIAL_FEAT_SCIF) { - s->fcr = 0; - } - else { - s->dr = 0xff; - } - - sh_serial_clear_fifo(s); - - memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s, - "serial", 0x100000000ULL); - - memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); - - memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); - - if (chr) { - qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, - sh_serial_receive1, - sh_serial_event, NULL, s, NULL, true); - } - - s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, - sh_serial_timeout_int, s); - s->etu = NANOSECONDS_PER_SECOND / 9600; - s->eri = eri_source; - s->rxi = rxi_source; - s->txi = txi_source; - s->tei = tei_source; - s->bri = bri_source; -} From patchwork Sun May 31 16:24:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 281603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43360C433E1 for ; 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Sun, 31 May 2020 12:24:39 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:48260) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jfQlJ-0004KS-Uh for qemu-devel@nongnu.org; Sun, 31 May 2020 12:24:39 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id 0A2EDECD3D; Mon, 1 Jun 2020 01:24:35 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id B56F71C0DB3; Mon, 1 Jun 2020 01:24:34 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 09/10] hw/sh4: Convert to renesas_timer.c Date: Mon, 1 Jun 2020 01:24:26 +0900 Message-Id: <20200531162427.57410-10-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200531162427.57410-1-ysato@users.sourceforge.jp> References: <20200531162427.57410-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Received-SPF: softfail client-ip=202.224.55.15; envelope-from=ysato@users.sourceforge.jp; helo=mail03.asahi-net.or.jp X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/31 12:24:33 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_SOFTFAIL=0.665, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Using unified TMU/CMT module. Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 10 --------- hw/sh4/sh7750.c | 47 +++++++++++++++++++++++++++++++++--------- hw/sh4/Kconfig | 2 +- hw/timer/Makefile.objs | 1 - 4 files changed, 38 insertions(+), 22 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index e184b4b300..248cc052e1 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -28,16 +28,6 @@ typedef struct { int sh7750_register_io_device(struct SH7750State *s, sh7750_io_device * device); -/* sh_timer.c */ -#define TMU012_FEAT_TOCR (1 << 0) -#define TMU012_FEAT_3CHAN (1 << 1) -#define TMU012_FEAT_EXTCLK (1 << 2) -void tmu012_init(struct MemoryRegion *sysmem, hwaddr base, - int feat, uint32_t freq, - qemu_irq ch0_irq, qemu_irq ch1_irq, - qemu_irq ch2_irq0, qemu_irq ch2_irq1); - - /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 150d3029f7..733c4009e1 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -32,6 +32,7 @@ #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" #include "hw/char/renesas_sci.h" +#include "hw/timer/renesas_timer.h" #include "hw/qdev-properties.h" #include "cpu.h" #include "exec/exec-all.h" @@ -756,13 +757,13 @@ static const MemoryRegionOps sh7750_mmct_ops = { }; static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source) + hwaddr base, int feat, + uint32_t freq, Chardev *chr, + qemu_irq eri_source, + qemu_irq rxi_source, + qemu_irq txi_source, + qemu_irq tei_source, + qemu_irq bri_source) { DeviceState *dev; SysBusDevice *sci; @@ -789,6 +790,31 @@ static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem, } } +static void tmu012_init(SH7750State *s, MemoryRegion *sysmem, hwaddr base, + int feat, uint32_t freq, + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1) +{ + DeviceState *dev; + SysBusDevice *tmu; + + dev = qdev_create(NULL, TYPE_RENESAS_TIMER); + + tmu = SYS_BUS_DEVICE(dev); + + qdev_prop_set_uint64(dev, "input-freq", freq); + qdev_prop_set_int32(dev, "feature", feat); + qdev_init_nofail(dev); + sysbus_mmio_map(tmu, 0, base); + sysbus_mmio_map(tmu, 1, P4ADDR(base)); + sysbus_mmio_map(tmu, 2, A7ADDR(base)); + sysbus_connect_irq(tmu, 0, ch0_irq); + sysbus_connect_irq(tmu, 1, ch1_irq); + if (ch2_irq0) { + sysbus_connect_irq(tmu, 2, ch2_irq0); + } +} + SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; @@ -853,8 +879,8 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) NULL, s->intc.irqs[SCIF_BRI]); - tmu012_init(sysmem, 0x1fd80000, - TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, + tmu012_init(s, sysmem, 0x1fd80000, + RTIMER_FEAT_TMU_LOW, s->periph_freq, s->intc.irqs[TMU0], s->intc.irqs[TMU1], @@ -877,7 +903,8 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_tmu34), NULL, 0); - tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, + tmu012_init(s, sysmem, 0x1e100000, + RTIMER_FEAT_TMU_HIGH, s->periph_freq, s->intc.irqs[TMU3], s->intc.irqs[TMU4], NULL, NULL); diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig index 38509b7e65..ac21830bb5 100644 --- a/hw/sh4/Kconfig +++ b/hw/sh4/Kconfig @@ -21,5 +21,5 @@ config SH7750 config SH4 bool - select PTIMER + select RENESAS_TIMER select RENESAS_SCI diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 289b6b03ab..f3918836e4 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -22,7 +22,6 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o common-obj-$(CONFIG_OMAP) += omap_gptimer.o common-obj-$(CONFIG_OMAP) += omap_synctimer.o common-obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o -common-obj-$(CONFIG_SH4) += sh_timer.o common-obj-$(CONFIG_DIGIC) += digic-timer.o common-obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o