From patchwork Thu Nov 9 21:03:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118480 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1393619edl; Thu, 9 Nov 2017 13:03:37 -0800 (PST) X-Google-Smtp-Source: ABhQp+RAVn1AQ2KHZhekWqnlakkqRdGOGF+TWY5Zb3xaaoQTYp8zSO+3EnB6r9Q2y9BjwWXXGJAb X-Received: by 10.84.235.137 with SMTP id p9mr1574530plk.291.1510261417188; Thu, 09 Nov 2017 13:03:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261417; cv=none; d=google.com; s=arc-20160816; b=FQDlApJCAeKv6LcgnIZFSGfn3MBmY6vESjQNVVtqtycaTc70EwmYj4QWpNKX5Obilr IEWoz5N0OP5nc+FjA8QPlYc4ZoDPu4MGGHTCkxb6dV49gUAyOPuEeOUo83cDwn6P33aw itKa0VYYmZ07k+NIl0Q/wo4MwZSWju2DTZXL54GyrM4T9SiXP4BHDlxj6ZLJmNfeSuk0 dWsbK4qDPi14TKdHJfYMbDEuiegbShiHqFVRkoEifk9rHZwycME3+xzfYC6H0rnMifdR ItXMkwLynWfx7gDV91xJ25HvB14pIClhmbL0zJ24+uIHjsoT8Xtpjl9NzyOJUkgP5FtP 2YOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=A2agtJK+eBu4FZozaeiJ+VBbr86KksQM2PUN2mzvFpM=; b=N2IANzrB859vHqcVUXmi+bffMO7nvK2plF8O0o8EbrNWBOBD8tUs6UG9v2V8en+4kt ephI2MNAqPacNlOr+irOgmfsXwBse4ParsPrI7Y4jeGmGOWQBDcu1Kx3aPCwdjbYpxac DBYXTbKYjTVqYZ2qM02WQ1lZtrYskV0ilmRaKRHeo3KGIA3CYTfhhfb22E5s4C+0K6HD 9IXTqQGMcHPqK1aPw3rXqEwIIsREneDOthBoaiG7IjA9O/77YjLicBb+Unheoq9heVLE fl31fnemAKO8wQqmD4FMC4s13fcDkDS2oMv/XoGapcm04tQt0X983ecp8qX4VCJHs+AK 6p0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y11si7034820pgr.323.2017.11.09.13.03.36; Thu, 09 Nov 2017 13:03:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754617AbdKIVDe (ORCPT + 26 others); Thu, 9 Nov 2017 16:03:34 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754537AbdKIVD3 (ORCPT ); Thu, 9 Nov 2017 16:03:29 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F46315A2; Thu, 9 Nov 2017 13:03:29 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9F5FC3F3DF; Thu, 9 Nov 2017 13:03:28 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 1/9] ACPICA: Add additional PPTT flags for cache properties Date: Thu, 9 Nov 2017 15:03:03 -0600 Message-Id: <20171109210311.25655-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PPTT table has a number of flags that can be set to describe whether the cache is I/D/U and the allocation and write policies. Add these flags. Signed-off-by: Jeremy Linton --- include/acpi/actbl1.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.13.5 diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 6b8714a428b6..71f874e2790d 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1346,6 +1346,20 @@ struct acpi_pptt_cache { #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ +/* Attributes describing cache */ +#define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ +#define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ +#define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */ +#define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ + +#define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ +#define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ +#define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ +#define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ + +#define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ +#define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ + /* 2: ID Structure */ struct acpi_pptt_id { From patchwork Thu Nov 9 21:03:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118488 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1395884edl; Thu, 9 Nov 2017 13:05:35 -0800 (PST) X-Google-Smtp-Source: ABhQp+Sc9UuOCmQR6BrWzzV8c1f49BS0Zb9Z6DBvfSjiyEE1wx6MDQN82t2SzIcCRsjgKCtzlvqu X-Received: by 10.84.192.37 with SMTP id b34mr1638840pld.451.1510261534990; Thu, 09 Nov 2017 13:05:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261534; cv=none; d=google.com; s=arc-20160816; b=qLUBl0Fl2yeFC42aR+xwawZFkN5G4Qn6AuuJL+r60H50xUUwBLKLHYSPirXkp13nQj iGGebdSlpxPK761S876Y5WaUh8OR51M7QQLE6d9m4XSqb14jRkcbRmvt0sgTsxhE6Kgq oSbnqR7WcRzbrMIs9vN33QZ6sit8AgW0bsC/XzsX19QZE+G+OSmvVTBB02nlxcYSUJMk DbMXT3oFTBLepTseukeDxKPTGHlwhfcHwotCjsVkM7AkFWceLg2mHpRZSHXz+nCZFjBz iFINnvWsONmTVsFX1RMWXdSSMTUUTzIRRomAGcE7pFe24eML2YC6lVmeDhPE9H8Poxhe j8fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=WrIW9xW3uKXMF9NpFt5VxE7bEFG/aYYgRtT6WDo3VGc=; b=HIsgEDWgO5gghObg5iGTVQyhrKuS1jh7JK9ZA2ErlTYkYpFBSZv6iql69QnqgKlqUI Ca9iYAlQE68Ds0yqAq63h6aYJdIg3J09rfehWCOf+9kBSuUWY5p3LqEgHjbeCrmohwRS /q/XAsjc2YoeW6ONim7JaOTSjIwTICjJ0U1oB/2A7oKkAhlizQa/lPWwWrnxH7NBNMTR 6/XX/wiDtaEab/gjtAZ2pj618B4PECyZukwtUpccwNCmQD3nUfu7o/QhIsv8hNYkQkca FtlOnLZgv5VPmtqL+zZQkKBTONMlgtFzyOyY+E03/0MaUZJJ5vyFzTUtqEiyklZ6iouD G/Qw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o19si7633052pfk.349.2017.11.09.13.05.34; Thu, 09 Nov 2017 13:05:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755174AbdKIVFd (ORCPT + 26 others); Thu, 9 Nov 2017 16:05:33 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51640 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754540AbdKIVDd (ORCPT ); Thu, 9 Nov 2017 16:03:33 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 951D2164F; Thu, 9 Nov 2017 13:03:32 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9465C3F3DF; Thu, 9 Nov 2017 13:03:31 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 2/9] ACPI/PPTT: Add Processor Properties Topology Table parsing Date: Thu, 9 Nov 2017 15:03:04 -0600 Message-Id: <20171109210311.25655-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI 6.2 adds a new table, which describes how processing units are related to each other in tree like fashion. Caches are also sprinkled throughout the tree and describe the properties of the caches in relation to other caches and processing units. Add the code to parse the cache hierarchy and report the total number of levels of cache for a given core using acpi_find_last_cache_level() as well as fill out the individual cores cache information with cache_setup_acpi() once the cpu_cacheinfo structure has been populated by the arch specific code. Further, report peers in the topology using setup_acpi_cpu_topology() to report a unique ID for each processing unit at a given level in the tree. These unique id's can then be used to match related processing units which exist as threads, COD (clusters on die), within a given package, etc. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 452 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 drivers/acpi/pptt.c -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c new file mode 100644 index 000000000000..9c9b8b4660e0 --- /dev/null +++ b/drivers/acpi/pptt.c @@ -0,0 +1,452 @@ +/* + * Copyright (C) 2017, ARM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * This file implements parsing of Processor Properties Topology Table (PPTT) + * which is optionally used to describe the processor and cache topology. + * Due to the relative pointers used throughout the table, this doesn't + * leverage the existing subtable parsing in the kernel. + * + * The PPTT structure is an inverted tree, with each node potentially + * holding one or two inverted tree data structures describing + * the caches available at that level. Each cache structure optionally + * contains properties describing the cache at that level which can be + * used to override hardware/probed values. + */ +#define pr_fmt(fmt) "ACPI PPTT: " fmt + +#include +#include +#include + +/* + * Given the PPTT table, find and verify that the subtable entry + * is located within the table + */ +static struct acpi_subtable_header *fetch_pptt_subtable( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + struct acpi_subtable_header *entry; + + /* there isn't a subtable at reference 0 */ + if (pptt_ref < sizeof(struct acpi_subtable_header)) + return NULL; + + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) + return NULL; + + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, pptt_ref); + + if (pptt_ref + entry->length > table_hdr->length) + return NULL; + + return entry; +} + +static struct acpi_pptt_processor *fetch_pptt_node( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr, + pptt_ref); +} + +static struct acpi_pptt_cache *fetch_pptt_cache( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, + pptt_ref); +} + +static struct acpi_subtable_header *acpi_get_pptt_resource( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node, int resource) +{ + u32 *ref; + + if (resource >= node->number_of_priv_resources) + return NULL; + + ref = ACPI_ADD_PTR(u32, node, sizeof(struct acpi_pptt_processor)); + ref += resource; + + return fetch_pptt_subtable(table_hdr, *ref); +} + +/* + * Attempt to find a given cache level, while counting the max number + * of cache levels for the cache node. + * + * Given a pptt resource, verify that it is a cache node, then walk + * down each level of caches, counting how many levels are found + * as well as checking the cache type (icache, dcache, unified). If a + * level & type match, then we set found, and continue the search. + * Once the entire cache branch has been walked return its max + * depth. + */ +static int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr, + int local_level, + struct acpi_subtable_header *res, + struct acpi_pptt_cache **found, + int level, int type) +{ + struct acpi_pptt_cache *cache; + + if (res->type != ACPI_PPTT_TYPE_CACHE) + return 0; + + cache = (struct acpi_pptt_cache *) res; + while (cache) { + local_level++; + + if ((local_level == level) && + (cache->flags & ACPI_PPTT_CACHE_TYPE_VALID) && + ((cache->attributes & ACPI_PPTT_MASK_CACHE_TYPE) == type)) { + if ((*found != NULL) && (cache != *found)) + pr_err("Found duplicate cache level/type unable to determine uniqueness\n"); + + pr_debug("Found cache @ level %d\n", level); + *found = cache; + /* + * continue looking at this node's resource list + * to verify that we don't find a duplicate + * cache node. + */ + } + cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache); + } + return local_level; +} + +/* + * Given a CPU node look for cache levels that exist at this level, and then + * for each cache node, count how many levels exist below (logically above) it. + * If a level and type are specified, and we find that level/type, abort + * processing and return the acpi_pptt_cache structure. + */ +static struct acpi_pptt_cache *acpi_find_cache_level( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + int *starting_level, int level, int type) +{ + struct acpi_subtable_header *res; + int number_of_levels = *starting_level; + int resource = 0; + struct acpi_pptt_cache *ret = NULL; + int local_level; + + /* walk down from processor node */ + while ((res = acpi_get_pptt_resource(table_hdr, cpu_node, resource))) { + resource++; + + local_level = acpi_pptt_walk_cache(table_hdr, *starting_level, + res, &ret, level, type); + /* + * we are looking for the max depth. Since its potentially + * possible for a given node to have resources with differing + * depths verify that the depth we have found is the largest. + */ + if (number_of_levels < local_level) + number_of_levels = local_level; + } + if (number_of_levels > *starting_level) + *starting_level = number_of_levels; + + return ret; +} + +/* + * Given a processor node containing a processing unit, walk into it and count + * how many levels exist solely for it, and then walk up each level until we hit + * the root node (ignore the package level because it may be possible to have + * caches that exist across packages). Count the number of cache levels that + * exist at each level on the way up. + */ +static int acpi_process_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node) +{ + int total_levels = 0; + + do { + acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0); + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while (cpu_node); + + return total_levels; +} + +/* + * Determine if the *node parameter is a leaf node by iterating the + * PPTT table, looking for nodes which reference it. + * Return 0 if we find a node refrencing the passed node, + * or 1 if we don't. + */ +static int acpi_pptt_leaf_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + u32 node_entry; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + node_entry = ACPI_PTR_DIFF(node, table_hdr); + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, + sizeof(struct acpi_table_pptt)); + + while ((unsigned long)(entry + 1) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (cpu_node->parent == node_entry)) + return 0; + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry, + entry->length); + } + return 1; +} + +/* + * Find the subtable entry describing the provided processor. + * This is done by iterating the PPTT table looking for processor nodes + * which have an acpi_processor_id that matches the acpi_cpu_id parameter + * passed into the function. If we find a node that matches this criteria + * we verify that its a leaf node in the topology rather than depending + * on the valid flag, which doesn't need to be set for leaf nodes. + */ +static struct acpi_pptt_processor *acpi_find_processor_node( + struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, + sizeof(struct acpi_table_pptt)); + + /* find the processor structure associated with this cpuid */ + while ((unsigned long)(entry + 1) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + + if (entry->length == 0) { + pr_err("Invalid zero length subtable\n"); + break; + } + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (acpi_cpu_id == cpu_node->acpi_processor_id) && + acpi_pptt_leaf_node(table_hdr, cpu_node)) { + return (struct acpi_pptt_processor *)entry; + } + + entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry, + entry->length); + } + + return NULL; +} + +static int acpi_find_cache_levels(struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + int number_of_levels = 0; + struct acpi_pptt_processor *cpu; + + cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (cpu) + number_of_levels = acpi_process_node(table_hdr, cpu); + + return number_of_levels; +} + +/* Convert the linux cache_type to a ACPI PPTT cache type value */ +static u8 acpi_cache_type(enum cache_type type) +{ + switch (type) { + case CACHE_TYPE_DATA: + pr_debug("Looking for data cache\n"); + return ACPI_PPTT_CACHE_TYPE_DATA; + case CACHE_TYPE_INST: + pr_debug("Looking for instruction cache\n"); + return ACPI_PPTT_CACHE_TYPE_INSTR; + default: + case CACHE_TYPE_UNIFIED: + pr_debug("Looking for unified cache\n"); + /* + * It is important that ACPI_PPTT_CACHE_TYPE_UNIFIED + * contains the bit pattern that will match both + * ACPI unified bit patterns because we use it later + * to match both cases. + */ + return ACPI_PPTT_CACHE_TYPE_UNIFIED; + } +} + +/* find the ACPI node describing the cache type/level for the given CPU */ +static struct acpi_pptt_cache *acpi_find_cache_node( + struct acpi_table_header *table_hdr, u32 acpi_cpu_id, + enum cache_type type, unsigned int level, + struct acpi_pptt_processor **node) +{ + int total_levels = 0; + struct acpi_pptt_cache *found = NULL; + struct acpi_pptt_processor *cpu_node; + u8 acpi_type = acpi_cache_type(type); + + pr_debug("Looking for CPU %d's level %d cache type %d\n", + acpi_cpu_id, level, acpi_type); + + cpu_node = acpi_find_processor_node(table_hdr, acpi_cpu_id); + + while ((cpu_node) && (!found)) { + found = acpi_find_cache_level(table_hdr, cpu_node, + &total_levels, level, acpi_type); + *node = cpu_node; + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } + + return found; +} + +/* + * The ACPI spec implies that the fields in the cache structures are used to + * extend and correct the information probed from the hardware. In the case + * of arm64 the CCSIDR probing has been removed because it might be incorrect. + */ +static void update_cache_properties(struct cacheinfo *this_leaf, + struct acpi_pptt_cache *found_cache, + struct acpi_pptt_processor *cpu_node) +{ + if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) + this_leaf->size = found_cache->size; + if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) + this_leaf->coherency_line_size = found_cache->line_size; + if (found_cache->flags & ACPI_PPTT_NUMBER_OF_SETS_VALID) + this_leaf->number_of_sets = found_cache->number_of_sets; + if (found_cache->flags & ACPI_PPTT_ASSOCIATIVITY_VALID) + this_leaf->ways_of_associativity = found_cache->associativity; + if (found_cache->flags & ACPI_PPTT_WRITE_POLICY_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY) { + case ACPI_PPTT_CACHE_POLICY_WT: + this_leaf->attributes = CACHE_WRITE_THROUGH; + break; + case ACPI_PPTT_CACHE_POLICY_WB: + this_leaf->attributes = CACHE_WRITE_BACK; + break; + } + if (found_cache->flags & ACPI_PPTT_ALLOCATION_TYPE_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE) { + case ACPI_PPTT_CACHE_READ_ALLOCATE: + this_leaf->attributes |= CACHE_READ_ALLOCATE; + break; + case ACPI_PPTT_CACHE_WRITE_ALLOCATE: + this_leaf->attributes |= CACHE_WRITE_ALLOCATE; + break; + case ACPI_PPTT_CACHE_RW_ALLOCATE: + case ACPI_PPTT_CACHE_RW_ALLOCATE_ALT: + this_leaf->attributes |= + CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE; + break; + } +} + +/* + * Update the kernel cache information for each level of cache + * associated with the given acpi cpu. + */ +static void cache_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu) +{ + struct acpi_pptt_cache *found_cache; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + struct cacheinfo *this_leaf; + unsigned int index = 0; + struct acpi_pptt_processor *cpu_node = NULL; + + while (index < get_cpu_cacheinfo(cpu)->num_leaves) { + this_leaf = this_cpu_ci->info_list + index; + found_cache = acpi_find_cache_node(table, acpi_cpu_id, + this_leaf->type, + this_leaf->level, + &cpu_node); + pr_debug("found = %p %p\n", found_cache, cpu_node); + if (found_cache) + update_cache_properties(this_leaf, + found_cache, + cpu_node); + + index++; + } +} + +/** + * acpi_find_last_cache_level() - Determines the number of cache levels for a PE + * @cpu: Kernel logical cpu number + * + * Given a logical cpu number, returns the number of levels of cache represented + * in the PPTT. Errors caused by lack of a PPTT table, or otherwise, return 0 + * indicating we didn't find any cache levels. + * + * Return: Cache levels visible to this core. + */ +int acpi_find_last_cache_level(unsigned int cpu) +{ + u32 acpi_cpu_id; + struct acpi_table_header *table; + int number_of_levels = 0; + acpi_status status; + + pr_debug("Cache Setup find last level cpu=%d\n", cpu); + + acpi_cpu_id = get_acpi_id_for_cpu(cpu); + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + } else { + number_of_levels = acpi_find_cache_levels(table, acpi_cpu_id); + acpi_put_table(table); + } + pr_debug("Cache Setup find last level level=%d\n", number_of_levels); + + return number_of_levels; +} + +/** + * cache_setup_acpi() - Override CPU cache topology with data from the PPTT + * @cpu: Kernel logical cpu number + * + * Updates the global cache info provided by cpu_get_cacheinfo() + * when there are valid properties in the acpi_pptt_cache nodes. A + * successful parse may not result in any updates if none of the + * cache levels have any valid flags set. Futher, a unique value is + * associated with each known CPU cache entry. This unique value + * can be used to determine whether caches are shared between cpus. + * + * Return: -ENOENT on failure to find table, or 0 on success + */ +int cache_setup_acpi(unsigned int cpu) +{ + struct acpi_table_header *table; + acpi_status status; + + pr_debug("Cache Setup ACPI cpu %d\n", cpu); + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + return -ENOENT; + } + + cache_setup_acpi_cpu(table, cpu); + acpi_put_table(table); + + return status; +} From patchwork Thu Nov 9 21:03:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118486 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1395144edl; Thu, 9 Nov 2017 13:04:56 -0800 (PST) X-Google-Smtp-Source: ABhQp+SnirBHnj9uK9RMDrs76ye0KNSSd9uS62Kx+K0UiRttlGWECFMy1iY3I46qSSBulPXdZPJc X-Received: by 10.99.110.6 with SMTP id j6mr1756564pgc.246.1510261496665; Thu, 09 Nov 2017 13:04:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261496; cv=none; d=google.com; s=arc-20160816; b=FcscvX/5FfAY3pB/RlMfC36Z3L29yXbjMepIu36UB8WRVqV+wiwLDpxydHOh12DrOI XONfakhp3zxMkocBvIDC7VkTVnTkXybabE+jPdpUYUt6jf+eTwe6q1+yqX3jkcTRj4Af xhLDneBFTFhqCHJV1A5qPywNlpcjFzvrR1S57EpmgidtqUv56/xlkbwaLxih7OtlIrIb mWLwGcfU5X0jLjgTCSB94aiydpojvnM5V5ddkQCUDjizX/scV/j0kflgIcKgljdYCzbg WTZOOkokqgkoyJWXJlpk/+BC/C14wrZB2azMD238msCMcURu94yrF85HFc4R+7c4IK0Q S6Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=KjBtSdjrWyPsZK+nH5OSG5PbsASv5Tt871+YwC+YBQA=; b=RA9Jfa98UV7NA6FcKtM23SHCnlSU44xlIkkRMXWYUhca9HLQYrSjjX9xyYTW1MRkcG yB45uq23C7oTLYE6Dq8Fk4MWNXC7eFb42LCTwqPGMuiV+Sazq3YOJzCHJn9OhW+D+dxI 81QjG0KUW7feglgwHsuhJ5XCDALJybUjkEq3WTHw+uJ14DLXChji/k8Ues4SJp9ODcbC WhmzAu0xOWjyscKvPTP5haXQVnYTpKTsLrmPW5HSYzqrtY8MCaJN6zFkCbu3fYzMeFY/ 6gup56RbZYNQEBecMnZfOWOZHY2WQ9FgDmQpl/p5MaO7SgmMEF11k+jMctqguHA5aAOE HFwA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m37si7014591pla.169.2017.11.09.13.04.56; Thu, 09 Nov 2017 13:04:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754731AbdKIVDj (ORCPT + 26 others); Thu, 9 Nov 2017 16:03:39 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51668 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754537AbdKIVDe (ORCPT ); Thu, 9 Nov 2017 16:03:34 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81A3E1650; Thu, 9 Nov 2017 13:03:34 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 760FB3F3DF; Thu, 9 Nov 2017 13:03:33 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 3/9] arm64/acpi: Create arch specific cpu to acpi id helper Date: Thu, 9 Nov 2017 15:03:05 -0600 Message-Id: <20171109210311.25655-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Its helpful to be able to lookup the acpi_processor_id associated with a logical cpu. Provide an arm64 helper to do this. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/acpi.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.13.5 diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 59cca1d6ec54..408e7989d3a2 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -86,6 +86,10 @@ static inline bool acpi_has_cpu_in_madt(void) } struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu); +static inline u32 get_acpi_id_for_cpu(unsigned int cpu) +{ + return acpi_cpu_get_madt_gicc(cpu)->uid; +} static inline void arch_fix_phys_package_id(int num, u32 slot) { } void __init acpi_init_cpus(void); From patchwork Thu Nov 9 21:03:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118481 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1393766edl; Thu, 9 Nov 2017 13:03:44 -0800 (PST) X-Google-Smtp-Source: ABhQp+QcdruukL08YCfwtGR3Rs6Jx0DE5EiYo3sifRj1LWkSpA04OfJ4Fb4/36Q9wlEhhsxi16bz X-Received: by 10.98.98.132 with SMTP id w126mr1786426pfb.208.1510261424587; Thu, 09 Nov 2017 13:03:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261424; cv=none; d=google.com; s=arc-20160816; b=Nig3DUE41j7GYqEFV4bb/Ho58D22QJvUciF8Kj7cGhYNkrG+6fynXTYE1Kxx0dk5EZ yt2ZoxKxc87Z8PnC0edintt/u893AqLo783VEolutARC9GziuK5gZdOTF9aaYu1PGkEo 4jteMi3dhIme70VHfzutYbMOEAdOdz8hTtD2yBADB0Xis+CZgGHjLYr9+19LeL2UBtP3 ViqJ7eDD5xUXLr9kNd+tFmiHosS1XGO85ZpNjaLvg8Sy03nrv8yFOc1cT33INdbx423I +8BR6Lu6mWWIDpzKr5HATDQ5C9KxBmcAkxPx9Ub/Pz+6LuJ2uAdKjbgIsLjGtpLVSt3f tGkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=AU4qR6u43gYyFFM4aL16yMhxDZYyq9wcgEa2LNXptbY=; b=aAvd17mNMvXZRezSd9LvkCz+EBWl9P1sEGbn/znaDFgQ/F1r7XCsLWQ2PEzELpyrxT adQLxgcPFGYFxVqtos+OgM0tsutKcrXLR1nHB5NZQhIRBDYbsO57YVY/rHldLzEn2vXg zORrNhgOamxkjNQxLNtbQeoOxiKvT1jQMIRbGd4TMeZO+afnJAmnl+g4+VfA8uILRROD G6OdakOujELfg+DKIK8XNPp/rnGnkO+CgVx1kEZWuXLncXlOudSdpvT/HAiCNBopyLsP klWQPDQATvTmav7+9timF3U6hq/vkIDA+NycKCmiJxe8QhyoSgIENH5dbJkBw9fpkjmb MkoA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j13si7216772pff.341.2017.11.09.13.03.44; Thu, 09 Nov 2017 13:03:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754825AbdKIVDl (ORCPT + 26 others); Thu, 9 Nov 2017 16:03:41 -0500 Received: from foss.arm.com ([217.140.101.70]:51678 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754629AbdKIVDg (ORCPT ); Thu, 9 Nov 2017 16:03:36 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C9BE165D; Thu, 9 Nov 2017 13:03:36 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1C8403F3DF; Thu, 9 Nov 2017 13:03:35 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 4/9] ACPI: Enable PPTT support on ARM64 Date: Thu, 9 Nov 2017 15:03:06 -0600 Message-Id: <20171109210311.25655-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we have a PPTT parser, in preparation for its use on arm64, lets build it. Signed-off-by: Jeremy Linton --- arch/arm64/Kconfig | 1 + drivers/acpi/Kconfig | 3 +++ drivers/acpi/Makefile | 1 + 3 files changed, 5 insertions(+) -- 2.13.5 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..68c9d1289735 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -7,6 +7,7 @@ config ARM64 select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ACPI_MCFG if ACPI select ACPI_SPCR_TABLE if ACPI + select ACPI_PPTT if ACPI select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 1ce52f84dc23..fa8a7aeaaed9 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -533,6 +533,9 @@ config ACPI_CONFIGFS if ARM64 source "drivers/acpi/arm64/Kconfig" + +config ACPI_PPTT + bool endif endif # ACPI diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 90265ab4437a..c92a0c937551 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_ACPI_BGRT) += bgrt.o obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o obj-$(CONFIG_ACPI_SPCR_TABLE) += spcr.o obj-$(CONFIG_ACPI_DEBUGGER_USER) += acpi_dbg.o +obj-$(CONFIG_ACPI_PPTT) += pptt.o # processor has its own "processor." module_param namespace processor-y := processor_driver.o From patchwork Thu Nov 9 21:03:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118487 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1395458edl; Thu, 9 Nov 2017 13:05:13 -0800 (PST) X-Google-Smtp-Source: ABhQp+TFFRd0HzD14Uyk7nbJzsSuJNVeupI+Jyfc5Bc4SYh+wm0EGlch8qzmz/smQENaagHCjV3Q X-Received: by 10.99.51.193 with SMTP id z184mr1656295pgz.285.1510261512965; Thu, 09 Nov 2017 13:05:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261512; cv=none; d=google.com; s=arc-20160816; b=g/O20giX4a3DIldEi7Hpmi6skGXTSUtso+InqKLIDXi6J9A3RUi7jMjKoWOEpQWx4V 9TAy0sUTQa9a5S/xjIflSgPoQeZvlPeIouXVumP1NXIWDe4/ChofQVi3ToYG87iifa/f D91SrUOvT433+tEIMxbii4zG0vlO4LkXWQzzyz+5rk1NAB0FEdHLw4+8E0q9xbt0p1eA DQx2/AkxG5Z+K4U2YD8dYWJrC9B8Ywj3SiwrXNz4rJ3qftr59xFYarqX6YgE7e9V6FPc noPi+WUIiKuw88M8b6XLSy6FpPyqkX6+6kKOEiWKFgdapBH6S+/5yeV0sgBUJEUkiqvf E38w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=CkTnq6104Kx3puwL85Q66RUqzmvsfxTso+uRQNVGhzA=; b=UFWbtgRI2CwPTz3lxCWJSDWA3tIg3LJckRisbtQJhA2fWGgkctqB+uWQJISLi2KQET OIjyO5KhhQ3DXqoLEbpSffjXrLX1ML1b6BOcD/wlxKPnduUs0y2+FhOklVOfF6wcFgWN Iy7kidd7WeEhqxm0W/6wY2811UrgUwKBxqD6tTwXHtOc7a62JmlK+gEvFhi+0oEYWGIQ Vbp5KJ9dk27bUYPggW3n4A0dyhuUUk2A3yh1Hn6AIU1tsx9Z8dTqxX2Uc2MKp98qDTE9 XSX50KkgEpYDHeDCKvpXgWmhWEdcvcUxubH9VnmyTxa9H18Lz2eve6Rq0U8phfFCUhlK X8Cw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o19si7633052pfk.349.2017.11.09.13.05.12; Thu, 09 Nov 2017 13:05:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755146AbdKIVFL (ORCPT + 26 others); Thu, 9 Nov 2017 16:05:11 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51706 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754632AbdKIVDi (ORCPT ); Thu, 9 Nov 2017 16:03:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD26F1682; Thu, 9 Nov 2017 13:03:37 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ACFB23F3DF; Thu, 9 Nov 2017 13:03:36 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 5/9] drivers: base: cacheinfo: arm64: Add support for ACPI based firmware tables Date: Thu, 9 Nov 2017 15:03:07 -0600 Message-Id: <20171109210311.25655-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The /sys cache entries should support ACPI/PPTT generated cache topology information. Lets detect ACPI systems and call an arch specific cache_setup_acpi() routine to update the hardware probed cache topology. For arm64, if ACPI is enabled, determine the max number of cache levels and populate them using a PPTT table if one is available. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cacheinfo.c | 23 ++++++++++++++++++----- drivers/acpi/pptt.c | 1 + drivers/base/cacheinfo.c | 17 +++++++++++------ include/linux/cacheinfo.h | 11 +++++++++-- 4 files changed, 39 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 380f2e2fbed5..2e2cf0d312ba 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -17,6 +17,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -44,9 +45,17 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type = type; } +#ifndef CONFIG_ACPI +int acpi_find_last_cache_level(unsigned int cpu) +{ + /*ACPI kernels should be built with PPTT support*/ + return 0; +} +#endif + static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves, of_level; + unsigned int ctype, level, leaves, fw_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -59,15 +68,19 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } - of_level = of_find_last_cache_level(cpu); - if (level < of_level) { + if (acpi_disabled) + fw_level = of_find_last_cache_level(cpu); + else + fw_level = acpi_find_last_cache_level(cpu); + + if (level < fw_level) { /* * some external caches not specified in CLIDR_EL1 * the information may be available in the device tree * only unified external caches are considered here */ - leaves += (of_level - level); - level = of_level; + leaves += (fw_level - level); + level = fw_level; } this_cpu_ci->num_levels = level; diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 9c9b8b4660e0..aa259502c4eb 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -324,6 +324,7 @@ static void update_cache_properties(struct cacheinfo *this_leaf, struct acpi_pptt_cache *found_cache, struct acpi_pptt_processor *cpu_node) { + this_leaf->firmware_node = cpu_node; if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) this_leaf->size = found_cache->size; if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af2739537..8eca279e50d1 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -86,7 +86,7 @@ static int cache_setup_of_node(unsigned int cpu) static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { - return sib_leaf->of_node == this_leaf->of_node; + return sib_leaf->firmware_node == this_leaf->firmware_node; } /* OF properties to query for a given cache type */ @@ -215,6 +215,11 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, } #endif +int __weak cache_setup_acpi(unsigned int cpu) +{ + return -ENOTSUPP; +} + static int cache_shared_cpu_map_setup(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -225,11 +230,11 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) if (this_cpu_ci->cpu_map_populated) return 0; - if (of_have_populated_dt()) + if (!acpi_disabled) + ret = cache_setup_acpi(cpu); + else if (of_have_populated_dt()) ret = cache_setup_of_node(cpu); - else if (!acpi_disabled) - /* No cache property/hierarchy support yet in ACPI */ - ret = -ENOTSUPP; + if (ret) return ret; @@ -286,7 +291,7 @@ static void cache_shared_cpu_map_remove(unsigned int cpu) static void cache_override_properties(unsigned int cpu) { - if (of_have_populated_dt()) + if (acpi_disabled && of_have_populated_dt()) return cache_of_override_properties(cpu); } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 6a524bf6a06d..d1e9b8e01981 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -36,6 +36,9 @@ enum cache_type { * @of_node: if devicetree is used, this represents either the cpu node in * case there's no explicit cache node or the cache node itself in the * device tree + * @firmware_node: Shared with of_node. When not using DT, this may contain + * pointers to other firmware based values. Particularly ACPI/PPTT + * unique values. * @disable_sysfs: indicates whether this node is visible to the user via * sysfs or not * @priv: pointer to any private data structure specific to particular @@ -64,8 +67,10 @@ struct cacheinfo { #define CACHE_ALLOCATE_POLICY_MASK \ (CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE) #define CACHE_ID BIT(4) - - struct device_node *of_node; + union { + struct device_node *of_node; + void *firmware_node; + }; bool disable_sysfs; void *priv; }; @@ -98,6 +103,8 @@ int func(unsigned int cpu) \ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); +int cache_setup_acpi(unsigned int cpu); +int acpi_find_last_cache_level(unsigned int cpu); const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); From patchwork Thu Nov 9 21:03:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118485 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1394860edl; Thu, 9 Nov 2017 13:04:42 -0800 (PST) X-Google-Smtp-Source: ABhQp+SzHQPh3Z9WMaGAJ3Kr4MAaVeGEapqd89wYJL0kGvVOknuoeq5oCfUzWovPoy2uP9Y9ET4Z X-Received: by 10.98.78.4 with SMTP id c4mr1784452pfb.103.1510261482436; Thu, 09 Nov 2017 13:04:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261482; cv=none; d=google.com; s=arc-20160816; b=A23a5NiRwLIWEXfaxMB2ZbjI7HjNH6NmIJGrDmu1CceHr6sJLj8UxXl+mFsBzjmHPE xnsXrKR5uyN8EpdcRpQj+6CPT3fS4yUui5U/gzukImVjMuapNFZY3zNI5AHeN3L61CpL KJBRfQgckvfvKVt2ybxWbcRFNwcoqogPn/bG1ZsWKNm+yuQxnSBGUCPvFpznCw/e8NRa 1MOe4J/qwCK7y3COPkTAw1zRkwaJds6SH6TeR6JYonUOhlUgXUuA3/fJPHd3JPoaZo6B muHGE9ahYh8Y2KoOT2x6uL4j1vAxhMKArjc7QPbQL7Jcu80E1Fqme9Et+qcqNZVbj2/8 zKjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=RsOjc/t7lj3hFDIg55wScO2N3w3YKOMO915c+3P8zaE=; b=rHeaqkjStKEtxuufyQtqkGZu5LPmQu7v/b0mpem/uDJ1w5lRhxlVQRt//WKxhXCFve tEgisMOGh4MQqju3Mbo78ZNlY43tJog3vi9HjyDB2fepZ2CptBk6QiFY5xgAAfrmmboJ fUnS7SbtlomkcAnBo8DVEs4qIEz0iQf8lebuvFWAHH3f9cv7JCO6RsVJ+z1/e0DfZyXL R8BnEq9zqAcmn4AvTEy7HiSro9pah5Bm3hEKd6D6Ak1I+ZAtOG8UimNk13D08hKM7Bsw ew7K7qObNdTfMumZEHNdJCuTRKIpm0s2lcHFl0JZFpDyZNBPOWbBadKU3+DU03Y+xv48 Hf8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a26si7201470pgn.797.2017.11.09.13.04.42; Thu, 09 Nov 2017 13:04:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755140AbdKIVEk (ORCPT + 26 others); Thu, 9 Nov 2017 16:04:40 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51742 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754728AbdKIVDj (ORCPT ); Thu, 9 Nov 2017 16:03:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4879D1684; Thu, 9 Nov 2017 13:03:39 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4819A3F3DF; Thu, 9 Nov 2017 13:03:38 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 6/9] ACPI/PPTT: Add topology parsing code Date: Thu, 9 Nov 2017 15:03:08 -0600 Message-Id: <20171109210311.25655-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PPTT can be used to determine the groupings of CPU's at given levels in the system. Lets add a few routines to the PPTT parsing code to return a unique id for each unique level in the processor hierarchy. This can then be matched to build thread/core/cluster/die/package/etc mappings for each processing element in the system. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index aa259502c4eb..b629d0b9a3a0 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -388,6 +388,81 @@ static void cache_setup_acpi_cpu(struct acpi_table_header *table, } } +/* + * Passing level values greater than this will result in search termination + */ +#define PPTT_ABORT_PACKAGE 0xFF + +/* + * Given a acpi_pptt_processor node, walk up until we identify the + * package that the node is associated with, or we run out of levels + * to request or the search is terminated with a flag match + * The level parameter also serves to limit possible loops within the tree. + */ +static struct acpi_pptt_processor *acpi_find_processor_package_id( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu, + int level, int flag) +{ + struct acpi_pptt_processor *prev_node; + + while (cpu && level) { + if (cpu->flags & flag) + break; + pr_debug("level %d\n", level); + prev_node = fetch_pptt_node(table_hdr, cpu->parent); + if (prev_node == NULL) + break; + cpu = prev_node; + level--; + } + return cpu; +} + +/* + * Get a unique value given a cpu, and a topology level, that can be + * matched to determine which cpus share common topological features + * at that level. + */ +static int topology_get_acpi_cpu_tag(struct acpi_table_header *table, + unsigned int cpu, int level, int flag) +{ + struct acpi_pptt_processor *cpu_node; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); + if (cpu_node) { + cpu_node = acpi_find_processor_package_id(table, cpu_node, + level, flag); + /* Only the first level has a guaranteed id */ + if (level == 0) + return cpu_node->acpi_processor_id; + return (int)((u8 *)cpu_node - (u8 *)table); + } + pr_err_once("PPTT table found, but unable to locate core for %d\n", + cpu); + return -ENOENT; +} + +static int find_acpi_cpu_topology_tag(unsigned int cpu, int level, int flag) +{ + struct acpi_table_header *table; + acpi_status status; + int retval; + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cpu topology may be inaccurate\n"); + return -ENOENT; + } + retval = topology_get_acpi_cpu_tag(table, cpu, level, flag); + pr_debug("Topology Setup ACPI cpu %d, level %d ret = %d\n", + cpu, level, retval); + acpi_put_table(table); + + return retval; +} + /** * acpi_find_last_cache_level() - Determines the number of cache levels for a PE * @cpu: Kernel logical cpu number @@ -451,3 +526,45 @@ int cache_setup_acpi(unsigned int cpu) return status; } + +/** + * find_acpi_cpu_topology() - Determine a unique topology value for a given cpu + * @cpu: Kernel logical cpu number + * @level: The topological level for which we would like a unique ID + * + * Determine a topology unique ID for each thread/core/cluster/mc_grouping + * /socket/etc. This ID can then be used to group peers, which will have + * matching ids. + * + * The search terminates when either the requested level is found or + * we reach a root node. Levels beyond the termination point will return the + * same unique ID. The unique id for level 0 is the acpi processor id. All + * other levels beyond this use a generated value to uniquely identify + * a topological feature. + * + * Return: -ENOENT if the PPTT doesn't exist, or the cpu cannot be found. + * Otherwise returns a value which represents a unique topological feature. + */ +int find_acpi_cpu_topology(unsigned int cpu, int level) +{ + return find_acpi_cpu_topology_tag(cpu, level, 0); +} + +/** + * find_acpi_cpu_topology_package() - Determine a unique cpu package value + * @cpu: Kernel logical cpu number + * + * Determine a topology unique package ID for the given cpu. + * This ID can then be used to group peers, which will have matching ids. + * + * The search terminates when either a level is found with the PHYSICAL_PACKAGE + * flag set or we reach a root node. + * + * Return: -ENOENT if the PPTT doesn't exist, or the cpu cannot be found. + * Otherwise returns a value which represents the package for this cpu. + */ +int find_acpi_cpu_topology_package(unsigned int cpu) +{ + return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE, + ACPI_PPTT_PHYSICAL_PACKAGE); +} From patchwork Thu Nov 9 21:03:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118482 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1393841edl; Thu, 9 Nov 2017 13:03:48 -0800 (PST) X-Google-Smtp-Source: ABhQp+ScVmsk/CaJCzrNlyOqxZTuDdvULRpYAySQJAK2BvURxj8fHfR2hoEgbaEusgwXNl+WQL7m X-Received: by 10.99.135.199 with SMTP id i190mr1684452pge.356.1510261428460; Thu, 09 Nov 2017 13:03:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261428; cv=none; d=google.com; s=arc-20160816; b=YpjJvmXFaG5GwE6gIksodtrJhpolVtR6H4+fo2r3jhByUHL297hFZq97dYfra5wnVn Nke+olb+ffy+Ltaaid0l000BxPgWxBfKZv3lLD3hPIoRAIL8hMqweGjURkPBg6ydm1q3 DJ2V2EzfIlnzXEz52Tj1m0VoGCXJCfpb9XsUWMWC/V4uD/7yJhn+hdm7UBaXZ1rQwbKU fQnqcjR5JHUHLUVLkwohEkl08NfLAlYCg0xa+Py59bFqEewe9QgpyovrlG3yhMIfZHMd 7mMsAwfiMtI2hyTZBCTSR16MXmGKxo/4skc0rtny06A6tgzmuwmZ2WpsmmncnJ4u5VRt vPkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=vET9fMxHJ1P3rmtbpH7VxBOiCDlMTZIfHuSJfjBHx3M=; b=Z14+eoPoFFbY+S3ubSDG8hLKKmi+j53SxROx4BUx8zADYI08jTlYD+Gdl/N0pkC+gM om+erS7FWk6OQtaxTKh6ahrVNKkj4axdN3/55Zmx0vI0lZtpiZZy/VwA9mq8yAF3d9Ho sX4aLOGMhHOJjAG/9+qPma42+tUFpOnU7U3KYhbav1tFMIVzXLzrvCDjmky2WaSTvirx uEJc2X2UfHA9wzUI0Qk2PIAPgSvVm4NL+z2FCHbKfxegcGZ5182IuW4sRl7mkV+Mg4/h s0GcAYzkZCv+qnozTMSC6VIcxcb2L6tZTME+ZsH/w0vE/p6oXSoc6AAh5Y2oGLlXuUcf qc9w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k5si6877895pgq.184.2017.11.09.13.03.48; Thu, 09 Nov 2017 13:03:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754902AbdKIVDo (ORCPT + 26 others); Thu, 9 Nov 2017 16:03:44 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51764 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754629AbdKIVDl (ORCPT ); Thu, 9 Nov 2017 16:03:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5FE7168F; Thu, 9 Nov 2017 13:03:40 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D505B3F3DF; Thu, 9 Nov 2017 13:03:39 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 7/9] arm64: Topology, rename cluster_id Date: Thu, 9 Nov 2017 15:03:09 -0600 Message-Id: <20171109210311.25655-8-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Lets match the name of the arm64 topology field to the kernel macro that uses it. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/topology.h | 4 ++-- arch/arm64/kernel/topology.c | 27 ++++++++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) -- 2.13.5 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 8b57339823e9..53c3b2c7c35c 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -6,14 +6,14 @@ struct cpu_topology { int thread_id; int core_id; - int cluster_id; + int physical_id; cpumask_t thread_sibling; cpumask_t core_sibling; }; extern struct cpu_topology cpu_topology[NR_CPUS]; -#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_physical_package_id(cpu) (cpu_topology[cpu].physical_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 8d48b233e6ce..74a8a5173a35 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -51,7 +51,7 @@ static int __init get_cpu_for_node(struct device_node *node) return -1; } -static int __init parse_core(struct device_node *core, int cluster_id, +static int __init parse_core(struct device_node *core, int physical_id, int core_id) { char name[10]; @@ -67,7 +67,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, leaf = false; cpu = get_cpu_for_node(t); if (cpu >= 0) { - cpu_topology[cpu].cluster_id = cluster_id; + cpu_topology[cpu].physical_id = physical_id; cpu_topology[cpu].core_id = core_id; cpu_topology[cpu].thread_id = i; } else { @@ -89,7 +89,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, return -EINVAL; } - cpu_topology[cpu].cluster_id = cluster_id; + cpu_topology[cpu].physical_id = physical_id; cpu_topology[cpu].core_id = core_id; } else if (leaf) { pr_err("%pOF: Can't get CPU for leaf core\n", core); @@ -105,7 +105,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) bool leaf = true; bool has_cores = false; struct device_node *c; - static int cluster_id __initdata; + static int physical_id __initdata; int core_id = 0; int i, ret; @@ -144,7 +144,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) } if (leaf) { - ret = parse_core(c, cluster_id, core_id++); + ret = parse_core(c, physical_id, core_id++); } else { pr_err("%pOF: Non-leaf cluster with core %s\n", cluster, name); @@ -162,7 +162,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) pr_warn("%pOF: empty cluster\n", cluster); if (leaf) - cluster_id++; + physical_id++; return 0; } @@ -198,7 +198,7 @@ static int __init parse_dt_topology(void) * only mark cores described in the DT as possible. */ for_each_possible_cpu(cpu) - if (cpu_topology[cpu].cluster_id == -1) + if (cpu_topology[cpu].physical_id == -1) ret = -EINVAL; out_map: @@ -228,7 +228,7 @@ static void update_siblings_masks(unsigned int cpuid) for_each_possible_cpu(cpu) { cpu_topo = &cpu_topology[cpu]; - if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + if (cpuid_topo->physical_id != cpu_topo->physical_id) continue; cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); @@ -249,7 +249,7 @@ void store_cpu_topology(unsigned int cpuid) struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; u64 mpidr; - if (cpuid_topo->cluster_id != -1) + if (cpuid_topo->physical_id != -1) goto topology_populated; mpidr = read_cpuid_mpidr(); @@ -263,19 +263,19 @@ void store_cpu_topology(unsigned int cpuid) /* Multiprocessor system : Multi-threads per core */ cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); - cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | + cpuid_topo->physical_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; } else { /* Multiprocessor system : Single-thread per core */ cpuid_topo->thread_id = -1; cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | + cpuid_topo->physical_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; } pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, + cpuid, cpuid_topo->physical_id, cpuid_topo->core_id, cpuid_topo->thread_id, mpidr); topology_populated: @@ -291,7 +291,7 @@ static void __init reset_cpu_topology(void) cpu_topo->thread_id = -1; cpu_topo->core_id = 0; - cpu_topo->cluster_id = -1; + cpu_topo->physical_id = -1; cpumask_clear(&cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpu_topo->core_sibling); @@ -300,6 +300,7 @@ static void __init reset_cpu_topology(void) } } + void __init init_cpu_topology(void) { reset_cpu_topology(); From patchwork Thu Nov 9 21:03:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 118484 Delivered-To: patch@linaro.org Received: by 10.80.225.132 with SMTP id k4csp1394410edl; Thu, 9 Nov 2017 13:04:18 -0800 (PST) X-Google-Smtp-Source: ABhQp+Q+5sJHboik7GnCjn+aL3vYo+YBpQ5KXBOVSf8hDC2EU/qzWsV5w8JcqUQg5soE+AINTruz X-Received: by 10.159.195.73 with SMTP id z9mr1720517pln.346.1510261458067; Thu, 09 Nov 2017 13:04:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510261458; cv=none; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id s36si7162871pld.67.2017.11.09.13.04.17; Thu, 09 Nov 2017 13:04:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755077AbdKIVEP (ORCPT + 26 others); Thu, 9 Nov 2017 16:04:15 -0500 Received: from foss.arm.com ([217.140.101.70]:51778 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754826AbdKIVDm (ORCPT ); Thu, 9 Nov 2017 16:03:42 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A7D816A3; Thu, 9 Nov 2017 13:03:42 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8A6683F3DF; Thu, 9 Nov 2017 13:03:41 -0800 (PST) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, robert.moore@intel.com, lv.zheng@intel.com, devel@acpica.org, Jeremy Linton Subject: [PATCH v4 8/9] arm64: topology: Enable ACPI/PPTT based CPU topology. Date: Thu, 9 Nov 2017 15:03:10 -0600 Message-Id: <20171109210311.25655-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171109210311.25655-1-jeremy.linton@arm.com> References: <20171109210311.25655-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Propagate the topology information from the PPTT tree to the cpu_topology array. We can get the thread id, core_id and cluster_id by assuming certain levels of the PPTT tree correspond to those concepts. The package_id is flagged in the tree and can be found by passing an arbitrary large level to setup_acpi_cpu_topology() which terminates its search when it finds an ACPI node flagged as the physical package. If the tree doesn't contain enough levels to represent all of thread/core/cod/package then the package id will be used for the missing levels. Since server/ACPI machines are more likely to be multisocket and NUMA, this patch also modifies the default clusters=sockets behavior for ACPI machines to sockets=sockets. DT machines continue to represent sockets as clusters. For ACPI machines, this results in a more normalized view of the topology. Cluster level scheduler decisions are still being made due to the "MC" level in the scheduler which has knowledge of cache sharing domains. This code is loosely based on a combination of code from: Xiongfeng Wang John Garry Jeffrey Hugo Signed-off-by: Jeremy Linton --- arch/arm64/kernel/topology.c | 47 +++++++++++++++++++++++++++++++++++++++++++- include/linux/topology.h | 2 ++ 2 files changed, 48 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 74a8a5173a35..198714aca9e8 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -300,6 +302,47 @@ static void __init reset_cpu_topology(void) } } +#ifdef CONFIG_ACPI +/* + * Propagate the topology information of the processor_topology_node tree to the + * cpu_topology array. + */ +static int __init parse_acpi_topology(void) +{ + u64 is_threaded; + int cpu; + int topology_id; + + is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK; + + for_each_possible_cpu(cpu) { + topology_id = find_acpi_cpu_topology(cpu, 0); + if (topology_id < 0) + return topology_id; + + if (is_threaded) { + cpu_topology[cpu].thread_id = topology_id; + topology_id = find_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].core_id = topology_id; + topology_id = find_acpi_cpu_topology_package(cpu); + cpu_topology[cpu].physical_id = topology_id; + } else { + cpu_topology[cpu].thread_id = -1; + cpu_topology[cpu].core_id = topology_id; + topology_id = find_acpi_cpu_topology_package(cpu); + cpu_topology[cpu].physical_id = topology_id; + } + } + return 0; +} + +#else +static int __init parse_acpi_topology(void) +{ + /*ACPI kernels should be built with PPTT support*/ + return -EINVAL; +} +#endif void __init init_cpu_topology(void) { @@ -309,6 +352,8 @@ void __init init_cpu_topology(void) * Discard anything that was parsed if we hit an error so we * don't use partial information. */ - if (of_have_populated_dt() && parse_dt_topology()) + if ((!acpi_disabled) && parse_acpi_topology()) + reset_cpu_topology(); + else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } diff --git a/include/linux/topology.h b/include/linux/topology.h index cb0775e1ee4b..170ce87edd88 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -43,6 +43,8 @@ if (nr_cpus_node(node)) int arch_update_cpu_topology(void); +int find_acpi_cpu_topology(unsigned int cpu, int level); +int find_acpi_cpu_topology_package(unsigned int cpu); /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10