From patchwork Sat Jun 13 13:36:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 280575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B285C433E0 for ; Sat, 13 Jun 2020 13:50:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 308C92074D for ; Sat, 13 Jun 2020 13:50:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 308C92074D Authentication-Results: mail.kernel.org; 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Sat, 13 Jun 2020 15:45:00 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 3/5] grackle: Set revision in PCI config to match hardware Date: Sat, 13 Jun 2020 15:36:15 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/13 09:45:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Howard Spoelstra , Mark Cave-Ayland , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: BALATON Zoltan --- hw/pci-host/grackle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c index 4b3af0c704..48d11f13ab 100644 --- a/hw/pci-host/grackle.c +++ b/hw/pci-host/grackle.c @@ -130,7 +130,7 @@ static void grackle_pci_class_init(ObjectClass *klass, void *data) k->realize = grackle_pci_realize; k->vendor_id = PCI_VENDOR_ID_MOTOROLA; k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106; - k->revision = 0x00; + k->revision = 0x40; k->class_id = PCI_CLASS_BRIDGE_HOST; /* * PCI-facing part of the host bridge, not usable without the From patchwork Sat Jun 13 13:36:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 280576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFE0FC433DF for ; Sat, 13 Jun 2020 13:46:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A7452078E for ; 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Sat, 13 Jun 2020 15:45:00 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 35788748DDA; Sat, 13 Jun 2020 15:45:00 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 5/5] mac_oldworld: Map macio to expected address at reset Date: Sat, 13 Jun 2020 15:36:15 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Howard Spoelstra , Mark Cave-Ayland , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a reset function that maps macio to the address expected by the firmware of the board at startup. Signed-off-by: BALATON Zoltan --- hw/ppc/mac.h | 12 ++++++++++++ hw/ppc/mac_oldworld.c | 17 +++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 6af87d1fa0..35a5f21163 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -57,6 +57,18 @@ #define OLDWORLD_IDE1_IRQ 0xe #define OLDWORLD_IDE1_DMA_IRQ 0x3 +/* g3beige machine */ +#define TYPE_HEATHROW_MACHINE MACHINE_TYPE_NAME("g3beige") +#define HEATHROW_MACHINE(obj) OBJECT_CHECK(HeathrowMachineState, (obj), \ + TYPE_HEATHROW_MACHINE) + +typedef struct HeathrowMachineState { + /*< private >*/ + MachineState parent; + + PCIDevice *macio_pci; +} HeathrowMachineState; + /* New World IRQs */ #define NEWWORLD_CUDA_IRQ 0x19 #define NEWWORLD_PMU_IRQ 0x19 diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 9138752ccb..fa9527410d 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -73,6 +73,15 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; } +static void ppc_heathrow_reset(MachineState *machine) +{ + HeathrowMachineState *m = HEATHROW_MACHINE(machine); + + qemu_devices_reset(); + pci_default_write_config(m->macio_pci, PCI_COMMAND, PCI_COMMAND_MEMORY, 2); + pci_default_write_config(m->macio_pci, PCI_BASE_ADDRESS_0, 0xf3000000, 4); +} + static void ppc_heathrow_cpu_reset(void *opaque) { PowerPCCPU *cpu = opaque; @@ -91,6 +100,7 @@ const MemoryRegionOps machine_id_reg_ops = { static void ppc_heathrow_init(MachineState *machine) { + HeathrowMachineState *hm = HEATHROW_MACHINE(machine); ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; @@ -298,7 +308,8 @@ static void ppc_heathrow_init(MachineState *machine) ide_drive_get(hd, ARRAY_SIZE(hd)); /* MacIO */ - macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); + hm->macio_pci = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); + macio = OLDWORLD_MACIO(hm->macio_pci); dev = DEVICE(macio); qdev_prop_set_uint64(dev, "frequency", tbfreq); object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", @@ -450,6 +461,7 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->desc = "Heathrow based PowerMAC"; mc->init = ppc_heathrow_init; + mc->reset = ppc_heathrow_reset; mc->block_default_type = IF_IDE; mc->max_cpus = MAX_CPUS; #ifndef TARGET_PPC64 @@ -466,9 +478,10 @@ static void heathrow_class_init(ObjectClass *oc, void *data) } static const TypeInfo ppc_heathrow_machine_info = { - .name = MACHINE_TYPE_NAME("g3beige"), + .name = TYPE_HEATHROW_MACHINE, .parent = TYPE_MACHINE, .class_init = heathrow_class_init, + .instance_size = sizeof(HeathrowMachineState), .interfaces = (InterfaceInfo[]) { { TYPE_FW_PATH_PROVIDER }, { }