From patchwork Tue Jun 16 00:50:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 280440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 912C8C433E0 for ; Tue, 16 Jun 2020 00:51:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5F26A2074D for ; Tue, 16 Jun 2020 00:51:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="npRk3Kbs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5F26A2074D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jkzpT-0008Jk-Lk for qemu-devel@archiver.kernel.org; Mon, 15 Jun 2020 20:51:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jkzoU-00072W-8a; Mon, 15 Jun 2020 20:50:54 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:54924) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jkzoS-0006Hz-Pi; Mon, 15 Jun 2020 20:50:53 -0400 Received: by mail-pj1-x1042.google.com with SMTP id u8so649765pje.4; Mon, 15 Jun 2020 17:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vtcx4S1GPP8c1wwhPLcdjKruiDpr1sKpV2nOfuK2xVs=; b=npRk3Kbs0FMB1jK1aqAaobO2/yWJx488tYBy3NY6SeSka0UbXt3TDtsscG3ol8F0Pk +7jtnyZnqWfnTL18VF6ttDdc78QLuhQptawn7W4CtRgZmxxa0pjXvMGEaNk6q+4N9GgU iiDoUd2PNDTbVS+Niz3LvIwCLM8HlNZT8LA1ThgQ4HE1MjIhTAnBp3xmfB1LuC3S7Ex6 qB2Bk1TnRTt61/6nADBxEo6FAvmaw1zKa2yBaIeZS7uH7V62XkW27FrOce6BCpMmvziz kizl8n17IleXf0S86APvRd5JCS342t91qH9BFl9zuWglaHOneP8F7eyjEK6Ps8VbG7w2 ztYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vtcx4S1GPP8c1wwhPLcdjKruiDpr1sKpV2nOfuK2xVs=; b=Np0teNmsPzP2O9yB3P/DYB7u5t+ODb5lxLMtw/cf4u4BEui0O6HwBm7cJ27DKJ1V1A vV03uL2L5OmFMiJXk/RMUqDZpOptaY5OwpY63jebzQe0DvJqntx5sT7wh0OVHWmpkdUy 5i035k5zr/O3vMwLbF7g0r5eQbnJYo50dCQ0Yx6oRSwIqm8SYUcj1PQ62Ea54Dgb3w5G y66gIcHISQcjLNsbk0hOPMdTXkm1Gv2FAavjXXNxEl4Nks7j/Es98ruCkgTP9jIYXtzA GAccT1lZyRSWcWRDLz4TUc485nwxVB0XnlOrOrYt3PLIHn2XWXsgc7z+u7ja6UNyjP4g pvRQ== X-Gm-Message-State: AOAM5314eI+HXtuqiEG5Na6skHW/292zktk0REYz8Y8tNpQoSgD1Vdol a0WWJpgh2Oh7uhbiUh8n2eg= X-Google-Smtp-Source: ABdhPJz3caIVl/52v0C0mUIa8L83ghSlVgcl44RUSjnS9F2TvL9f4hCI0tQCylPLht9OuhT6UoEWmw== X-Received: by 2002:a17:90a:2683:: with SMTP id m3mr305335pje.196.1592268651224; Mon, 15 Jun 2020 17:50:51 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id i20sm15210539pfd.81.2020.06.15.17.50.50 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 15 Jun 2020 17:50:50 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine Date: Mon, 15 Jun 2020 17:50:37 -0700 Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> References: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Current IBEX CPU init routine name seems to be too generic. Since it uses a different reset vector from the generic one, it merits a dedicated name. Signed-off-by: Bin Meng --- Changes in v2: - new patch: Rename IBEX CPU init routine target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e867766..5f03458 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj) #if defined(TARGET_RISCV32) -static void rv32_imcu_nommu_cpu_init(Object *obj) +static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVC | RVU); @@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init), From patchwork Tue Jun 16 00:50:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 280439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC356C433DF for ; Tue, 16 Jun 2020 00:52:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AE58B20776 for ; Tue, 16 Jun 2020 00:52:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="blHCDv4W" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AE58B20776 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jkzpX-0008P3-RC for qemu-devel@archiver.kernel.org; Mon, 15 Jun 2020 20:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jkzoV-00073U-Mt; Mon, 15 Jun 2020 20:50:55 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:39326) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jkzoT-0006JS-Nw; Mon, 15 Jun 2020 20:50:55 -0400 Received: by mail-pj1-x1029.google.com with SMTP id h95so725683pje.4; Mon, 15 Jun 2020 17:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uw1r8epZoEetYZu7MSacVagmc0CVPicKiM+zkpvkEbQ=; b=blHCDv4WlH9qOfnHL3zeToaevnFVWeu//PM+Ebp/hUkefY9H41k2AKeLpvAwVv6x2x FW6o01rd2HCrtuEnLjCnSn19crNHPX/4ZMd8qIqXg7cWiF9YIMR4yHj8T7FsjE63ISi+ PcCj18aixvcTsD8w0agG+fGSlaSSqFrcmUZzKQXzA1jkiMTFvxys8PlzSHt9vqa6eJWS DonT0UCRQmpOThIASCc3NQdoAyhBZB2Wo7HkOMR984v70T/X6h7fs2pAaYZQg4MZ2tRP xkiyaFYpPTAnL2UdA3+4Y9WGSrXNcyB0uaDrs1rVyFiIbQAmslfynU1rHg+vPtFRO76d WgGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uw1r8epZoEetYZu7MSacVagmc0CVPicKiM+zkpvkEbQ=; b=rZo8sAxh9/FFNDpMPptZLadeey49nuqGBfUQJz9F5VwYUWVr5sXwJ+XtaHru2uIEOq yJ/qoSmBjRSKuN7QWHhqxg+bVvl/QzN3k9gwMcdnZos9b7dXNG8u2OraOHy6wohotQF4 eheUn5ITCASloZg1uWMY9+HyYw1OFNi0DcDF7MFDAXU+a4JCV+W2t9lDpGDgilLbwkfK bfM2oJ5ckI2gf/lD5KDrju5TN1Tn1sM9hDk+9sb1lH/rCK6yB7TG1HDb3eIPhItN6Xof GoEkzQhyheCEYEb2WEr46i3gPz6cNtWT0x4QQCfBZaMeoaVUn+Nh029/lypvMKcwLoWG 5AIQ== X-Gm-Message-State: AOAM5330RU5jgniHy7rLsMgVIGmXNtTbKwicyhTVzHF1so/AJUx9vneu 5UoLvaKyWjfIoxqlwjGzHM8= X-Google-Smtp-Source: ABdhPJy0xij/8bkE+QyhiE0zYs0lKbmfdiyGYyVjpGJi/1JZlRgRjwFzKNJ2D1R8m5Twg95cbyLwqw== X-Received: by 2002:a17:90b:3685:: with SMTP id mj5mr320716pjb.162.1592268652181; Mon, 15 Jun 2020 17:50:52 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id i20sm15210539pfd.81.2020.06.15.17.50.51 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 15 Jun 2020 17:50:51 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Date: Mon, 15 Jun 2020 17:50:38 -0700 Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> References: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1029.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng --- Changes in v2: - rebase on https://github.com/alistair23/qemu riscv-to-apply.next branch - rename SiFive E/U CPU init routine names hw/riscv/sifive_e.c | 10 ++++++---- hw/riscv/sifive_u.c | 6 +++--- target/riscv/cpu.c | 16 ++++++++-------- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d9a5c7b..d1d3bf1 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -98,14 +98,16 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DTIM].base, main_mem); /* Mask ROM reset vector */ - uint32_t reset_vec[2]; + uint32_t reset_vec[4]; if (s->revb) { - reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */ + reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ } else { - reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */ + reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ } - reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */ + reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ + + reset_vec[0] = reset_vec[3] = 0; /* copy in the reset vector in little_endian byte order */ for (i = 0; i < sizeof(reset_vec) >> 2; i++) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index aaa5adb..0a86ffc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -433,18 +433,18 @@ static void sifive_u_machine_init(MachineState *machine) /* reset vector */ uint32_t reset_vec[8] = { + 0x00000000, 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) 0x0182a283, /* lw t0, 24(t0) */ #elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ + 0x0182e283, /* lwu t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ 0x00000000, start_addr, /* start: .dword */ - 0x00000000, /* dtb: */ }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5f03458..391a0b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -134,20 +134,20 @@ static void riscv_base_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } -static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj) +static void rvxx_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); + set_resetvec(env, 0x1004); } -static void rvxx_imacu_nommu_cpu_init(Object *obj) +static void rvxx_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); + set_resetvec(env, 0x1004); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -578,13 +578,13 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), #endif }; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id i20sm15210539pfd.81.2020.06.15.17.50.52 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 15 Jun 2020 17:50:52 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state Date: Mon, 15 Jun 2020 17:50:39 -0700 Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> References: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng SiFive FU540 SoC supports booting from several sources, which are controlled using the Mode Select (MSEL[3:0]) pins on the chip. Typically, the boot process runs through several stages before it begins execution of user-provided programs. The SoC supports booting from memory-mapped QSPI flash, which is how start_in_flash property is used for at present. This matches MSEL = 1 configuration (QSPI0). Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL). It's not necessary for QEMU to implement the full ZSBL ROM codes, because we know ZSBL downloads the next stage program into the L2 LIM at address 0x8000000 and executes from there. We can bypass the whole ZSBL execution and use "-bios" to load the next stage program directly if MSEL indicates a ZSBL booting flow. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++++-------- include/hw/riscv/sifive_u.h | 6 ++++++ 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0a86ffc..f64aa52 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -408,8 +408,34 @@ static void sifive_u_machine_init(MachineState *machine) /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); - riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SIFIVE_U_DRAM].base, NULL); + if (s->start_in_flash) { + /* + * If start_in_flash property is given, assign s->msel to a value + * that representing booting from QSPI0 memory-mapped flash. + * + * This also means that when both start_in_flash and msel properties + * are given, start_in_flash takes the precedence over msel. + * + * Note this is to keep backward compatibility not to break existing + * users that use start_in_flash property. + */ + s->msel = MSEL_MEMMAP_QSPI0_FLASH; + } + + switch (s->msel) { + case MSEL_MEMMAP_QSPI0_FLASH: + start_addr = memmap[SIFIVE_U_FLASH0].base; + break; + case MSEL_L2LIM_QSPI0_FLASH: + case MSEL_L2LIM_QSPI2_SD: + start_addr = memmap[SIFIVE_U_L2LIM].base; + break; + default: + start_addr = memmap[SIFIVE_U_DRAM].base; + break; + } + + riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); if (machine->kernel_filename) { uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, @@ -427,13 +453,9 @@ static void sifive_u_machine_init(MachineState *machine) } } - if (s->start_in_flash) { - start_addr = memmap[SIFIVE_U_FLASH0].base; - } - /* reset vector */ uint32_t reset_vec[8] = { - 0x00000000, + s->msel, /* MSEL pin state */ 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ @@ -505,7 +527,8 @@ static void sifive_u_machine_instance_init(Object *obj) sifive_u_machine_set_start_in_flash); object_property_set_description(obj, "start-in-flash", "Set on to tell QEMU's ROM to jump to " - "flash. Otherwise QEMU will jump to DRAM"); + "flash. Otherwise QEMU will jump to DRAM " + "or L2LIM depending on the msel value"); s->msel = 0; object_property_add(obj, "msel", "uint32", diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d82cfe0..5d80f91 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -111,6 +111,12 @@ enum { SIFIVE_U_RTCCLK_FREQ = 1000000 }; +enum { + MSEL_MEMMAP_QSPI0_FLASH = 1, + MSEL_L2LIM_QSPI0_FLASH = 6, + MSEL_L2LIM_QSPI2_SD = 11 +}; + #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 #define SIFIVE_U_COMPUTE_CPU_COUNT 4