From patchwork Tue Nov 7 20:38:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 118208 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4444840qgn; Tue, 7 Nov 2017 12:41:57 -0800 (PST) X-Google-Smtp-Source: ABhQp+TYV1MnYqhF3IPr9q9JghYqHnAAKN+Act4dU0Y/bW0htLNBRaXek/1QWs+Llk98HgqIW+pm X-Received: by 10.99.4.133 with SMTP id 127mr29401pge.72.1510087317496; Tue, 07 Nov 2017 12:41:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510087317; cv=none; d=google.com; s=arc-20160816; b=WwMefmWv0f2S4M2pqeOjuIYR2RzelNnWHzow/he9oSNZtAaj8K+6QZh7i8idY/dv// 805bVapsE7o9MRXUgJiRbCQ01Fy+gHeGe5Wq2JCOCgyORG+1XqBM2o8Iq2KU1XIRUVq2 W33JDSRsboRx1jCtq6tSx6o4kN6Nwht3Xrpg9W8LvS28P2AmAP1pxaAW7cxpJ8W6UDO2 zvNzg3OsDrXjSjv+dirx0mAguaqzPjyWyXzON8kf/qQ7ITcy2QG6QIcFMYEFRfxbKJK4 ekGRIpTEODN8DH+U6BYYIsRfq3UyDkNJ0iYf4W3QnjYvmYyj5M57jn4F/lHaQAuiJZqP wwtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=ApvgUxckGKIZuGTQGLCfnX3Cq3piHw9s+eMzlT0ax/Y=; b=QTd++xz5SOdrcIeGOjAbGQp0bT0u7VEsqZSBT/ZCegNzLMfYoTXksGR2WbiHGCipWj XarBrRudlukmc949uQqT+bEJ8T7KnNtz6vx4c66P2CX66DlnpuJ3PVk7JaK2NR8TmeQA il40yPq4ILBxajExZ2A0aKdrJMSBskAogZ2tUdtKILx9qSIH8yTQAmx4/JW0+w/RoVln 5kmGnMaZhovl2SZ+0t1++IROYUqSv/TolfBoam6tD1oCdGX5F3hNwVlQWNMHjiVqd1sM 7zCkvV7Dw3SIQXUCrWrlsyzDGfqLKDq3r8x9zgk5T1Ht/g4euh4LBCSzGr72SvswK3zv zD2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=vZXEAl0c; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64si1908200pgc.697.2017.11.07.12.41.57; Tue, 07 Nov 2017 12:41:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=vZXEAl0c; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933450AbdKGUl4 (ORCPT + 4 others); Tue, 7 Nov 2017 15:41:56 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:38801 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933304AbdKGUlz (ORCPT ); Tue, 7 Nov 2017 15:41:55 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vA7KeQgE013930; Tue, 7 Nov 2017 14:40:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1510087226; bh=DCkUEcakBqVEoK3P041dt2AFuD04DvdvLbL5ts8HJk8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vZXEAl0cfOXTkJ2Tg5gRjpYE9rG8RHs31r1OkjtZkCui6mwZlGdx0pmkthu99Or8S GhkGA2S+ewWEKtLfGqajrmBunDSGu+DSwRy+KEOkZ9PzZK03BDeWGI6lrIdWSfi5o0 2EX0jtvOFQLfI8mU5lDitJkTMLv+0cBy5nC1w+sU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KeLv8030226; Tue, 7 Nov 2017 14:40:21 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 7 Nov 2017 14:40:20 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 7 Nov 2017 14:40:20 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KeFwU016393; Tue, 7 Nov 2017 14:40:18 -0600 From: Tero Kristo To: , , , , CC: Tony Lindgren , Santosh Shilimkar , Rob Herring Subject: [PATCH 1/3] Documentation: dt: memory: ti-emif: add edac support under emif Date: Tue, 7 Nov 2017 22:38:57 +0200 Message-ID: <1510087139-21885-2-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510087139-21885-1-git-send-email-t-kristo@ti.com> References: <1510087139-21885-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Certain revisions of the TI EMIF IP contain ECC support in them. Reflect this in the DT binding. Signed-off-by: Tero Kristo Cc: Tony Lindgren Cc: Santosh Shilimkar Cc: Rob Herring --- .../devicetree/bindings/memory-controllers/ti/emif.txt | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 0db6047..f56a347 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -3,12 +3,16 @@ EMIF - External Memory Interface - is an SDRAM controller used in TI SoCs. EMIF supports, based on the IP revision, one or more of DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance -of the EMIF IP and memory parts attached to it. +of the EMIF IP and memory parts attached to it. Certain revisions +of the EMIF IP controller also contain optional ECC support, which +corrects one bit errors and detects two bit errors. Required properties: - compatible : Should be of the form "ti,emif-" where is the IP revision of the specific EMIF instance. For am437x should be ti,emif-am4372. + For dra7xx should be ti,emif-dra7xx. + For k2x family, should be ti,emif-keystone. - phy-type : indicating the DDR phy type. Following are the allowed values @@ -42,6 +46,10 @@ Optional properties: - hw-caps-temp-alert : Have this property if the controller has capability for generating SDRAM temperature alerts +- interrupts : A list of interrupt specifiers for memory + controller interrupts, if available. Required for EMIF instances + that support ECC. + Example: emif1: emif@0x4c000000 { @@ -54,3 +62,9 @@ emif1: emif@0x4c000000 { hw-caps-ll-interface; hw-caps-temp-alert; }; + +emif1: emif@4c000000 { + compatible = "ti,emif-dra7"; + reg = <0x4c000000 0x200>; + interrupts = ; +}; From patchwork Tue Nov 7 20:38:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 118206 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4444379qgn; Tue, 7 Nov 2017 12:41:21 -0800 (PST) X-Google-Smtp-Source: ABhQp+RzI1MLFGgJUZ1F85dOjUzZdU1nY66dhXwuBwkELRW5XtNhulTbTGBfC0eWQK1CXlKafemB X-Received: by 10.99.4.133 with SMTP id 127mr28329pge.72.1510087281632; Tue, 07 Nov 2017 12:41:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510087281; cv=none; d=google.com; s=arc-20160816; b=gb41TfAGZVtPhqm9sh8CmoOkZT1wJTE+C1oLlycINozu1vxZStaZbCaOSsUP5dC10Q r8vIXMfr7yPZmH/D+YM0e8+myAokTTdFdrWkLG9BJ0kawMdkN0T7QMWGzjW3/XFL4MhI 4h7TcrwlmekHl8rLqNJrlb/OwHbcabCfAg09oIrrfNA+EvWm6XOwsfng4WZi7CoqK/yy Z/1hzTqjabX1/nJb8OI8yjz9MMWYU/9VRVTlD6E7/2ewyVJgXuYbcinAQS79xt3tYZos dsKnx+yprN4lQsuH3TqkD4kkHtA6PFoLWcssR4nJJtsUc+VMaVN3dgJKoLvhwUhFvFXI 6vxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=0BSHjpEmIJK0G9ljynW0Z0eCBwLH7myxu5q25VkEHNQ=; b=SXBStcR50tO8IxqXJFyphsGkqXUvCp6mrRbjqjuLkBpcERnbNLNKHufJc4POAoPQNp m4X1hYvMAj1boceVxt98S3jHIYAAeb1Clar7M2TvhzG4laiz5Hhek4O6Tdgs3Hhbb2Fo nLTHyIcz4wWwoTJGO4FGC23ont2pIpKOyn1EpNw49gPjRTNW5teXBDoOUZd4URmkjEEe 7a57tGoMVaJhelta0MTt5Gc4u/LnxtFG1Q59zJiZj0+XYKRpsaKrVDLWtiOAHOKg4NPg YSkOf6Lh8z3w9xro4ycNgqFyGOn1UT7kIib66B3YDXxuV04EvQc/3j8zPWxd78ylLKrd mYqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=QuBarB9u; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64si1908200pgc.697.2017.11.07.12.41.21; Tue, 07 Nov 2017 12:41:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=QuBarB9u; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933441AbdKGUlU (ORCPT + 4 others); Tue, 7 Nov 2017 15:41:20 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:64732 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933304AbdKGUlT (ORCPT ); Tue, 7 Nov 2017 15:41:19 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vA7KeN32030421; Tue, 7 Nov 2017 14:40:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1510087223; bh=3zjVJbDwS6dwbkV7r/GrRFchoy/7IgEejXLCq4JYUcs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QuBarB9ukwaLEVzqg1h5HmkpRhlc/9BFXmOkC9A/dvfszTMLkylyaFVyGTcczUpoh G1aLDdmdqBfeiBID1jIjavsrP20pcljmm29PKi2zEyJ2k1JH+qea6XIvgh0Zzh6arK 4W1RUhVsa+qKpXcNILPGJwufpwgMzWlSoVtLZ/CE= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KeNQW030277; Tue, 7 Nov 2017 14:40:23 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 7 Nov 2017 14:40:22 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 7 Nov 2017 14:40:23 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KeFwV016393; Tue, 7 Nov 2017 14:40:20 -0600 From: Tero Kristo To: , , , , CC: Santosh Shilimkar , Tony Lindgren Subject: [PATCH 2/3] EDAC: ti: add support for TI keystone and DRA7xx EDAC Date: Tue, 7 Nov 2017 22:38:58 +0200 Message-ID: <1510087139-21885-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510087139-21885-1-git-send-email-t-kristo@ti.com> References: <1510087139-21885-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org TI Keystone and DRA7xx SoCs have support for EDAC on DDR3 memory that can correct one bit errors and detect two bit errors. Add EDAC driver for this feature which plugs into the generic kernel EDAC framework. Signed-off-by: Tero Kristo Cc: Santosh Shilimkar Cc: Tony Lindgren --- drivers/edac/Kconfig | 7 ++ drivers/edac/Makefile | 1 + drivers/edac/ti_edac.c | 306 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 314 insertions(+) create mode 100644 drivers/edac/ti_edac.c -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 96afb2a..54f0184 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -457,4 +457,11 @@ config EDAC_XGENE Support for error detection and correction on the APM X-Gene family of SOCs. +config EDAC_TI + tristate "Texas Instruments DDR3 ECC handler" + depends on ARCH_KEYSTONE || SOC_DRA7XX + help + Support for error detection and correction on the + TI SoCs. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 0fd9ffa..b54912e 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o +obj-$(CONFIG_EDAC_TI) += ti_edac.o diff --git a/drivers/edac/ti_edac.c b/drivers/edac/ti_edac.c new file mode 100644 index 0000000..54bacf3 --- /dev/null +++ b/drivers/edac/ti_edac.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * Texas Instruments DDR3 ECC error correction and detection driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "edac_module.h" + +/* EMIF controller registers */ +#define EMIF_SDRAM_CONFIG 0x008 +#define EMIF_IRQ_STATUS 0x0ac +#define EMIF_IRQ_ENABLE_SET 0x0b4 +#define EMIF_ECC_CTRL 0x110 +#define EMIF_1B_ECC_ERR_CNT 0x130 +#define EMIF_1B_ECC_ERR_THRSH 0x134 +#define EMIF_1B_ECC_ERR_ADDR_LOG 0x13c +#define EMIF_2B_ECC_ERR_ADDR_LOG 0x140 + +/* Bit definitions for EMIF_SDRAM_CONFIG */ +#define SDRAM_TYPE_SHIFT 29 +#define SDRAM_TYPE_MASK GENMASK(31,29) +#define SDRAM_TYPE_DDR3 (3 << SDRAM_TYPE_SHIFT) +#define SDRAM_TYPE_DDR2 (2 << SDRAM_TYPE_SHIFT) +#define SDRAM_NARROW_MODE_MASK GENMASK(15,14) +#define SDRAM_K2_NARROW_MODE_SHIFT 12 +#define SDRAM_K2_NARROW_MODE_MASK GENMASK(13,12) +#define SDRAM_ROWSIZE_SHIFT 7 +#define SDRAM_ROWSIZE_MASK GENMASK(9,7) +#define SDRAM_IBANK_SHIFT 4 +#define SDRAM_IBANK_MASK GENMASK(6,4) +#define SDRAM_K2_IBANK_SHIFT 5 +#define SDRAM_K2_IBANK_MASK GENMASK(6,5) +#define SDRAM_K2_EBANK_SHIFT 3 +#define SDRAM_K2_EBANK_MASK BIT(SDRAM_K2_EBANK_SHIFT) +#define SDRAM_PAGESIZE_SHIFT 0 +#define SDRAM_PAGESIZE_MASK GENMASK(2,0) +#define SDRAM_K2_PAGESIZE_SHIFT 0 +#define SDRAM_K2_PAGESIZE_MASK GENMASK(1,0) + +#define EMIF_1B_ECC_ERR_THRSH_SHIFT 24 + +/* IRQ bit definitions */ +#define EMIF_1B_ECC_ERR BIT(5) +#define EMIF_2B_ECC_ERR BIT(4) +#define EMIF_WR_ECC_ERR BIT(3) +#define EMIF_SYS_ERR BIT(0) +/* Bit 31 enables ECC and 28 enables RMW */ +#define ECC_ENABLED (BIT(31) | BIT(28)) + +enum { + EMIF_TYPE_DRA7, + EMIF_TYPE_K2 +}; + +struct ti_edac { + void __iomem *reg; +}; + +static DEFINE_MUTEX(ti_edac_lock); + +static u32 ti_edac_readl(struct ti_edac *edac, u16 offset) +{ + return readl_relaxed(edac->reg + offset); +} + +static void ti_edac_writel(struct ti_edac *edac, u32 val, u16 offset) +{ + writel_relaxed(val, edac->reg + offset); +} + +static irqreturn_t ti_edac_isr(int irq, void *data) +{ + struct mem_ctl_info *mci = data; + struct ti_edac *edac = mci->pvt_info; + u32 irq_status; + u32 err_addr; + int err_count; + + irq_status = ti_edac_readl(edac, EMIF_IRQ_STATUS); + + if (irq_status & EMIF_1B_ECC_ERR) { + err_addr = ti_edac_readl(edac, EMIF_1B_ECC_ERR_ADDR_LOG); + err_count = ti_edac_readl(edac, EMIF_1B_ECC_ERR_CNT); + ti_edac_writel(edac, err_count, EMIF_1B_ECC_ERR_CNT); + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, + err_addr >> PAGE_SHIFT, + err_addr & ~PAGE_MASK, -1, 0, 0, 0, + mci->ctl_name, "1B"); + } + + if (irq_status & EMIF_2B_ECC_ERR) { + err_addr = ti_edac_readl(edac, EMIF_2B_ECC_ERR_ADDR_LOG); + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, + err_addr >> PAGE_SHIFT, + err_addr & ~PAGE_MASK, -1, 0, 0, 0, + mci->ctl_name, "2B"); + } + + if (irq_status & EMIF_WR_ECC_ERR) + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, + 0, 0, -1, 0, 0, 0, + mci->ctl_name, "WR"); + + ti_edac_writel(edac, irq_status, EMIF_IRQ_STATUS); + + return IRQ_HANDLED; +} + +static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type) +{ + struct dimm_info *dimm; + struct ti_edac *edac = mci->pvt_info; + int bits; + u32 val; + u32 memsize; + + dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); + + val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG); + + if (type == EMIF_TYPE_DRA7) { + bits = ((val & SDRAM_PAGESIZE_MASK) >> + SDRAM_PAGESIZE_SHIFT) + 8; + bits += ((val & SDRAM_ROWSIZE_MASK) >> + SDRAM_ROWSIZE_SHIFT) + 9; + bits += (val & SDRAM_IBANK_MASK) >> SDRAM_IBANK_SHIFT; + + if (val & SDRAM_NARROW_MODE_MASK) { + bits++; + dimm->dtype = DEV_X16; + } else { + bits += 2; + dimm->dtype = DEV_X32; + } + } else { + bits = 16; + bits += ((val & SDRAM_K2_PAGESIZE_MASK) >> + SDRAM_K2_PAGESIZE_SHIFT) + 8; + bits += (val & SDRAM_K2_IBANK_MASK) >> SDRAM_K2_IBANK_SHIFT; + bits += (val & SDRAM_K2_EBANK_MASK) >> SDRAM_K2_EBANK_SHIFT; + + val = (val & SDRAM_K2_NARROW_MODE_MASK) >> + SDRAM_K2_NARROW_MODE_SHIFT; + switch (val) { + case 0: + bits += 3; + dimm->dtype = DEV_X64; + break; + case 1: + bits += 2; + dimm->dtype = DEV_X32; + break; + case 2: + bits ++; + dimm->dtype = DEV_X16; + break; + } + } + + memsize = 1 << bits; + + dimm->nr_pages = memsize >> PAGE_SHIFT; + dimm->grain = 4; + if ((val & SDRAM_TYPE_MASK) == SDRAM_TYPE_DDR2) + dimm->mtype = MEM_DDR2; + else + dimm->mtype = MEM_DDR3; + + val = ti_edac_readl(edac, EMIF_ECC_CTRL); + if (val & ECC_ENABLED) + dimm->edac_mode = EDAC_SECDED; + else + dimm->edac_mode = EDAC_NONE; +} + +static const struct of_device_id ti_edac_of_match[] = { + { .compatible = "ti,emif-keystone", .data = (void *)EMIF_TYPE_K2 }, + { .compatible = "ti,emif-dra7xx", .data = (void *)EMIF_TYPE_DRA7 }, + {}, +}; + +static int ti_edac_probe(struct platform_device *pdev) +{ + int error_irq = 0, ret = -ENODEV; + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *reg; + struct mem_ctl_info *mci; + struct edac_mc_layer layers[1]; + const struct of_device_id *id; + struct ti_edac *edac; + static int edac_id; + int my_id; + + id = of_match_device(ti_edac_of_match, &pdev->dev); + if (!id) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(dev, res); + if (IS_ERR(reg)) { + dev_err(dev, "DDR3 controller regs not defined\n"); + return PTR_ERR(reg); + } + + layers[0].type = EDAC_MC_LAYER_ALL_MEM; + layers[0].size = 1; + + /* Allocate ID number for our EMIF controller */ + mutex_lock(&ti_edac_lock); + my_id = edac_id++; + mutex_unlock(&ti_edac_lock); + + mci = edac_mc_alloc(my_id, 1, layers, sizeof(*edac)); + if (!mci) + return -ENOMEM; + + mci->pdev = &pdev->dev; + edac = mci->pvt_info; + edac->reg = reg; + platform_set_drvdata(pdev, mci); + + mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; + mci->edac_ctl_cap = EDAC_FLAG_SECDED | EDAC_FLAG_NONE; + mci->mod_name = pdev->dev.driver->name; + mci->ctl_name = id->compatible; + mci->dev_name = dev_name(&pdev->dev); + + /* Setup memory layout */ + ti_edac_setup_dimm(mci, (u32)(id->data)); + + if (edac_mc_add_mc(mci)) { + pr_err("%s: Failed to register mci.\n", __func__); + return -ENOMEM; + } + + /* add EMIF ECC error handler */ + error_irq = platform_get_irq(pdev, 0); + if (!error_irq) { + dev_err(dev, "DDR3 EDAC irq number not defined\n"); + return ret; + } + + ret = devm_request_irq(dev, error_irq, ti_edac_isr, 0, + "ddr3-edac-irq", mci); + if (ret) { + dev_err(dev, "request_irq fail for DDR3 EDAC error irq\n"); + return ret; + } + + /* Generate an interrupt with each 1b error */ + ti_edac_writel(edac, 1 << EMIF_1B_ECC_ERR_THRSH_SHIFT, + EMIF_1B_ECC_ERR_THRSH); + + /* Enable interrupts */ + ti_edac_writel(edac, + EMIF_1B_ECC_ERR | EMIF_2B_ECC_ERR | EMIF_WR_ECC_ERR, + EMIF_IRQ_ENABLE_SET); + + return ret; +} + +static int ti_edac_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = platform_get_drvdata(pdev); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +static struct platform_driver ti_edac_driver = { + .probe = ti_edac_probe, + .remove = ti_edac_remove, + .driver = { + .name = "ti_edac", + .of_match_table = ti_edac_of_match, + }, +}; + +module_platform_driver(ti_edac_driver); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("EDAC Driver for Texas Instruments DDR3 MC"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Nov 7 20:38:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 118205 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4444146qgn; Tue, 7 Nov 2017 12:41:02 -0800 (PST) X-Google-Smtp-Source: ABhQp+TdziM/SvmIsJRgKZAgQjbE56xuZM6f/kKN8uk0Uqr3h6gCcTRi83/9VVB0pfWmsG4mewVr X-Received: by 10.159.244.18 with SMTP id x18mr5010plr.338.1510087262507; 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[209.132.180.67]) by mx.google.com with ESMTP id t64si1908200pgc.697.2017.11.07.12.41.02; Tue, 07 Nov 2017 12:41:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=AB2LScXG; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933438AbdKGUlB (ORCPT + 4 others); Tue, 7 Nov 2017 15:41:01 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:59245 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933304AbdKGUlA (ORCPT ); Tue, 7 Nov 2017 15:41:00 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vA7KePWT001331; Tue, 7 Nov 2017 14:40:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1510087225; bh=ky8Vnk1zsSPU1x3Vo8NjDRkMmcxmyGxK1rA6gJuAb6M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AB2LScXG6qaDh1+ttBVHH5uDeIqmbkEer4tm/wKMwjfEocqdM0G6ig5AlnvhnE/0R xsfdYq1cHRHnesAFYeHqaJKug4zBF5STXW6Vzy6jHWlTQBYJwn6V+89LyWp5lniNyC HDE2+pwJJHmk9dz6ewRHD2r07yOzx6Q5NWai+eho= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KePMk031124; Tue, 7 Nov 2017 14:40:25 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 7 Nov 2017 14:40:25 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 7 Nov 2017 14:40:25 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA7KeFwW016393; Tue, 7 Nov 2017 14:40:23 -0600 From: Tero Kristo To: , , , , CC: Murali Karicheri , Santosh Shilimkar Subject: [PATCH 3/3] ARM: dts: Keystone: add ECC error handler support Date: Tue, 7 Nov 2017 22:38:59 +0200 Message-ID: <1510087139-21885-4-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510087139-21885-1-git-send-email-t-kristo@ti.com> References: <1510087139-21885-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Murali Karicheri Add emif node for keystone2 devices, which is used for ECC support. Signed-off-by: Murali Karicheri [t-kristo@ti.com: made emif enabled by default for all keystone2 devices] Signed-off-by: Tero Kristo Cc: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 6 ++++++ arch/arm/boot/dts/keystone.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 826b286..33e12c1 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -343,5 +343,11 @@ clock-names = "fck", "mmchsdb_fck"; status = "disabled"; }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + }; }; }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 8dd74f4..5f4e38f 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -340,5 +340,11 @@ ; }; }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + }; }; };