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[111.243.189.249]) by smtp.gmail.com with ESMTPSA id c27sm7578483pfj.163.2020.07.30.19.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2020 19:47:58 -0700 (PDT) From: Green Wan To: Subject: [RFC PATCH v2 2/2] hw/riscv: sifive_u: Add write-once protection. Date: Fri, 31 Jul 2020 10:47:08 +0800 Message-Id: <20200731024708.32725-3-green.wan@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200731024708.32725-1-green.wan@sifive.com> References: <20200731024708.32725-1-green.wan@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=green.wan@sifive.com; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , qemu-devel@nongnu.org, Green Wan , Alistair Francis , Palmer Dabbelt , bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add array to store the 'written' status for all bit of OTP to block the write operation to the same bit. Ignore the control register offset from 0x0 to 0x38 of OTP memory mapping. Signed-off-by: Green Wan --- hw/riscv/sifive_u_otp.c | 20 ++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c index e359f30fdb..a793093d47 100644 --- a/hw/riscv/sifive_u_otp.c +++ b/hw/riscv/sifive_u_otp.c @@ -35,6 +35,11 @@ #define TRACE_PREFIX "FU540_OTP: " #define SIFIVE_FU540_OTP_SIZE (SIFIVE_U_OTP_NUM_FUSES * 4) +#define SET_WRITTEN_BIT(map, idx, bit) \ + (map[idx] |= (0x1 << bit)) + +#define GET_WRITTEN_BIT(map, idx, bit) \ + ((map[idx] >> bit) & 0x1) static int32_t sifive_u_otp_backed_open(const char *filename, int32_t *fd, uint32_t **map) @@ -195,6 +200,18 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr, s->ptrim = val32; break; case SIFIVE_U_OTP_PWE: + /* Keep written state for data only and PWE is enabled. Ignore PAS=1 */ + if ((s->pa > SIFIVE_U_OTP_PWE) && (val32 & 0x1) && !s->pas) { + if (GET_WRITTEN_BIT(s->fuse_wo, s->pa, s->paio)) { + qemu_log_mask(LOG_GUEST_ERROR, + TRACE_PREFIX "Error: write idx<%u>, bit<%u>\n", + s->pa, s->paio); + break; + } else { + SET_WRITTEN_BIT(s->fuse_wo, s->pa, s->paio); + } + } + /* open and mmap OTP image file */ if (0 == sifive_u_otp_backed_open(s->otp_file, &fd, &map)) { /* store value */ @@ -248,6 +265,9 @@ static void sifive_u_otp_reset(DeviceState *dev) /* Make a valid content of serial number */ s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); + + /* Initialize write-once map */ + memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo)); } static void sifive_u_otp_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h index f3d71ce82d..4c6ac2e75e 100644 --- a/include/hw/riscv/sifive_u_otp.h +++ b/include/hw/riscv/sifive_u_otp.h @@ -73,6 +73,7 @@ typedef struct SiFiveUOTPState { uint32_t ptrim; uint32_t pwe; uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; /* config */ uint32_t serial; char *otp_file;