From patchwork Tue Aug 18 15:50:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BFE9C433DF for ; Tue, 18 Aug 2020 15:53:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 186942080C for ; Tue, 18 Aug 2020 15:53:23 +0000 (UTC) Authentication-Results: mail.kernel.org; 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envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson --- target/hexagon/cpu-param.h | 26 ++++ target/hexagon/cpu.h | 164 +++++++++++++++++++++++ target/hexagon/cpu_bits.h | 34 +++++ target/hexagon/internal.h | 40 ++++++ target/hexagon/cpu.c | 316 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 580 insertions(+) create mode 100644 target/hexagon/cpu-param.h create mode 100644 target/hexagon/cpu.h create mode 100644 target/hexagon/cpu_bits.h create mode 100644 target/hexagon/internal.h create mode 100644 target/hexagon/cpu.c diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h new file mode 100644 index 0000000..3a6b727 --- /dev/null +++ b/target/hexagon/cpu-param.h @@ -0,0 +1,26 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_CPU_PARAM_H +#define HEXAGON_CPU_PARAM_H + +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + +#define NB_MMU_MODES 1 + +#endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h new file mode 100644 index 0000000..af3d644 --- /dev/null +++ b/target/hexagon/cpu.h @@ -0,0 +1,164 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_CPU_H +#define HEXAGON_CPU_H + +/* Forward declaration needed by some of the header files */ +typedef struct CPUHexagonState CPUHexagonState; + +#include + +#define TARGET_PAGE_BITS 16 /* 64K pages */ +#define TARGET_LONG_BITS 32 + +#include "qemu/compiler.h" +#include "qemu-common.h" +#include "exec/cpu-defs.h" +#include "hex_regs.h" + +#define NUM_PREGS 4 +#ifdef CONFIG_USER_ONLY +#define TOTAL_PER_THREAD_REGS 64 +#else +#error System mode not implemented +#endif + +#define SLOTS_MAX 4 +#define STORES_MAX 2 +#define REG_WRITES_MAX 32 +#define PRED_WRITES_MAX 5 /* 4 insns + endloop */ + +#define TYPE_HEXAGON_CPU "hexagon-cpu" + +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU + +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") + +#define MMU_USER_IDX 0 + +struct MemLog { + target_ulong va; + uint8_t width; + uint32_t data32; + uint64_t data64; +}; + +#define EXEC_STATUS_OK 0x0000 +#define EXEC_STATUS_STOP 0x0002 +#define EXEC_STATUS_REPLAY 0x0010 +#define EXEC_STATUS_LOCKED 0x0020 +#define EXEC_STATUS_EXCEPTION 0x0100 + + +#define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) +#define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) +#define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) +#define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) + +struct CPUHexagonState { + target_ulong gpr[TOTAL_PER_THREAD_REGS]; + target_ulong pred[NUM_PREGS]; + target_ulong branch_taken; + target_ulong next_PC; + + /* For comparing with LLDB on target - see hack_stack_ptrs function */ + target_ulong stack_start; + target_ulong stack_adjust; + + uint8_t slot_cancelled; + target_ulong new_value[TOTAL_PER_THREAD_REGS]; + + /* + * Only used when HEX_DEBUG is on, but unconditionally included + * to reduce recompile time when turning HEX_DEBUG on/off. + */ + target_ulong this_PC; + target_ulong reg_written[TOTAL_PER_THREAD_REGS]; + + target_ulong new_pred_value[NUM_PREGS]; + target_ulong pred_written; + + struct MemLog mem_log_stores[STORES_MAX]; + target_ulong pkt_has_store_s1; + target_ulong dczero_addr; + + fenv_t fenv; + + target_ulong llsc_addr; + target_ulong llsc_val; + uint64_t llsc_val_i64; + + target_ulong is_gather_store_insn; + target_ulong gather_issued; +}; + +#define HEXAGON_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU) +#define HEXAGON_CPU(obj) \ + OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU) +#define HEXAGON_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU) + +typedef struct HexagonCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + DeviceReset parent_reset; +} HexagonCPUClass; + +typedef struct HexagonCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + CPUNegativeOffsetState neg; + CPUHexagonState env; +} HexagonCPU; + +static inline HexagonCPU *hexagon_env_get_cpu(CPUHexagonState *env) +{ + return container_of(env, HexagonCPU, env); +} + +#include "cpu_bits.h" + +#define cpu_signal_handler cpu_hexagon_signal_handler +extern int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); + +static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + *pc = env->gpr[HEX_REG_PC]; + *cs_base = 0; +#ifdef CONFIG_USER_ONLY + *flags = 0; +#else +#error System mode not supported on Hexagon yet +#endif +} + +typedef struct CPUHexagonState CPUArchState; +typedef HexagonCPU ArchCPU; + +void hexagon_translate_init(void); + +#include "exec/cpu-all.h" + +#endif /* HEXAGON_CPU_H */ diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h new file mode 100644 index 0000000..586c717 --- /dev/null +++ b/target/hexagon/cpu_bits.h @@ -0,0 +1,34 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_CPU_BITS_H +#define HEXAGON_CPU_BITS_H + +#define HEX_EXCP_FETCH_NO_UPAGE 0x012 +#define HEX_EXCP_INVALID_PACKET 0x015 +#define HEX_EXCP_INVALID_OPCODE 0x015 +#define HEX_EXCP_PRIV_NO_UREAD 0x024 +#define HEX_EXCP_PRIV_NO_UWRITE 0x025 + +#define HEX_EXCP_TRAP0 0x172 + +#define PACKET_WORDS_MAX 4 + +extern int disassemble_hexagon(uint32_t *words, int nwords, + char *buf, int bufsize); + +#endif diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h new file mode 100644 index 0000000..d3e4412 --- /dev/null +++ b/target/hexagon/internal.h @@ -0,0 +1,40 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_INTERNAL_H +#define HEXAGON_INTERNAL_H + +/* + * Change HEX_DEBUG to 1 to turn on debugging output + */ +#define HEX_DEBUG 0 +#define HEX_DEBUG_LOG(...) \ + do { \ + if (HEX_DEBUG) { \ + rcu_read_lock(); \ + fprintf(stderr, __VA_ARGS__); \ + rcu_read_unlock(); \ + } \ + } while (0) + +extern void hexagon_debug(CPUHexagonState *env); + +extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS]; + +extern void init_genptr(void); + +#endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c new file mode 100644 index 0000000..d812913 --- /dev/null +++ b/target/hexagon/cpu.c @@ -0,0 +1,316 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/qemu-print.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" +#include "qapi/error.h" +#include "migration/vmstate.h" + +static void hexagon_v67_cpu_init(Object *obj) +{ +} + +static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + char **cpuname; + + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); + oc = object_class_by_name(typename); + g_strfreev(cpuname); + g_free(typename); + if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || + object_class_is_abstract(oc)) { + return NULL; + } + return oc; +} + +const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", + "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", + "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "c22", "c23", + "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", +}; + +/* + * One of the main debugging techniques is to use "-d cpu" and compare against + * LLDB output when single stepping. However, the target and qemu put the + * stacks at different locations. This is used to compensate so the diff is + * cleaner. + */ +static inline target_ulong hack_stack_ptrs(CPUHexagonState *env, + target_ulong addr) +{ + static bool first = true; + if (first) { + first = false; + env->stack_start = env->gpr[HEX_REG_SP]; + env->gpr[HEX_REG_USR] = 0x56000; + +#define ADJUST_STACK 0 +#if ADJUST_STACK + /* + * Change the two numbers below to + * 1 qemu stack location + * 2 hardware stack location + * Or set to zero for normal mode (no stack adjustment) + */ + env->stack_adjust = 0xfffeeb80 - 0xbf89f980; +#else + env->stack_adjust = 0; +#endif + } + + target_ulong stack_start = env->stack_start; + target_ulong stack_size = 0x10000; + target_ulong stack_adjust = env->stack_adjust; + + if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { + return addr - stack_adjust; + } + return addr; +} + +/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */ +static inline target_ulong read_p3_0(CPUHexagonState *env) +{ + int32_t control_reg = 0; + int i; + for (i = NUM_PREGS - 1; i >= 0; i--) { + control_reg <<= 8; + control_reg |= env->pred[i] & 0xff; + } + return control_reg; +} + +static void print_reg(FILE *f, CPUHexagonState *env, int regnum) +{ + target_ulong value; + + if (regnum == HEX_REG_P3_0) { + value = read_p3_0(env); + } else { + value = regnum < 32 ? hack_stack_ptrs(env, env->gpr[regnum]) + : env->gpr[regnum]; + } + + qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", + hexagon_regnames[regnum], value); +} + +static void hexagon_dump(CPUHexagonState *env, FILE *f) +{ + static target_ulong last_pc; + int i; + + /* + * When comparing with LLDB, it doesn't step through single-cycle + * hardware loops the same way. So, we just skip them here + */ + if (env->gpr[HEX_REG_PC] == last_pc) { + return; + } + last_pc = env->gpr[HEX_REG_PC]; + qemu_fprintf(f, "General Purpose Registers = {\n"); + for (i = 0; i < 32; i++) { + print_reg(f, env, i); + } + print_reg(f, env, HEX_REG_SA0); + print_reg(f, env, HEX_REG_LC0); + print_reg(f, env, HEX_REG_SA1); + print_reg(f, env, HEX_REG_LC1); + print_reg(f, env, HEX_REG_M0); + print_reg(f, env, HEX_REG_M1); + print_reg(f, env, HEX_REG_USR); + print_reg(f, env, HEX_REG_P3_0); + print_reg(f, env, HEX_REG_GP); + print_reg(f, env, HEX_REG_UGP); + print_reg(f, env, HEX_REG_PC); +#ifdef CONFIG_USER_ONLY + /* + * Not modelled in user mode, print junk to minimize the diff's + * with LLDB output + */ + qemu_fprintf(f, " cause = 0x000000db\n"); + qemu_fprintf(f, " badva = 0x00000000\n"); + qemu_fprintf(f, " cs0 = 0x00000000\n"); + qemu_fprintf(f, " cs1 = 0x00000000\n"); +#else + print_reg(f, env, HEX_REG_CAUSE); + print_reg(f, env, HEX_REG_BADVA); + print_reg(f, env, HEX_REG_CS0); + print_reg(f, env, HEX_REG_CS1); +#endif + qemu_fprintf(f, "}\n"); +} + +static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) +{ + HexagonCPU *cpu = HEXAGON_CPU(cs); + CPUHexagonState *env = &cpu->env; + + hexagon_dump(env, f); +} + +void hexagon_debug(CPUHexagonState *env) +{ + hexagon_dump(env, stdout); +} + +static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) +{ + HexagonCPU *cpu = HEXAGON_CPU(cs); + CPUHexagonState *env = &cpu->env; + env->gpr[HEX_REG_PC] = value; +} + +static void hexagon_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + HexagonCPU *cpu = HEXAGON_CPU(cs); + CPUHexagonState *env = &cpu->env; + env->gpr[HEX_REG_PC] = tb->pc; +} + +static bool hexagon_cpu_has_work(CPUState *cs) +{ + return true; +} + +void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb, + target_ulong *data) +{ + env->gpr[HEX_REG_PC] = data[0]; +} + +static void hexagon_cpu_reset(DeviceState *dev) +{ + CPUState *cs = CPU(dev); + HexagonCPU *cpu = HEXAGON_CPU(cs); + HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); + + mcc->parent_reset(dev); +} + +static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) +{ + info->print_insn = print_insn_hexagon; +} + +static void hexagon_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); + Error *local_err = NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + qemu_init_vcpu(cs); + cpu_reset(cs); + + mcc->parent_realize(dev, errp); +} + +static void hexagon_cpu_init(Object *obj) +{ + HexagonCPU *cpu = HEXAGON_CPU(obj); + + cpu_set_cpustate_pointers(cpu); +} + +static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ +#ifdef CONFIG_USER_ONLY + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE; + break; + case MMU_DATA_LOAD: + cs->exception_index = HEX_EXCP_PRIV_NO_UREAD; + break; + case MMU_DATA_STORE: + cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE; + break; + } + cpu_loop_exit_restore(cs, retaddr); +#else +#error System mode not implemented for Hexagon +#endif +} + +static void hexagon_cpu_class_init(ObjectClass *c, void *data) +{ + HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); + CPUClass *cc = CPU_CLASS(c); + DeviceClass *dc = DEVICE_CLASS(c); + + device_class_set_parent_realize(dc, hexagon_cpu_realize, + &mcc->parent_realize); + + device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset); + + cc->class_by_name = hexagon_cpu_class_by_name; + cc->has_work = hexagon_cpu_has_work; + cc->dump_state = hexagon_dump_state; + cc->set_pc = hexagon_cpu_set_pc; + cc->synchronize_from_tb = hexagon_cpu_synchronize_from_tb; + cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; + cc->gdb_stop_before_watchpoint = true; + cc->disas_set_info = hexagon_cpu_disas_set_info; +#ifdef CONFIG_TCG + cc->tcg_initialize = hexagon_translate_init; + cc->tlb_fill = hexagon_tlb_fill; +#endif +} + +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name = type_name, \ + .parent = TYPE_HEXAGON_CPU, \ + .instance_init = initfn \ + } + +static const TypeInfo hexagon_cpu_type_infos[] = { + { + .name = TYPE_HEXAGON_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(HexagonCPU), + .instance_init = hexagon_cpu_init, + .abstract = true, + .class_size = sizeof(HexagonCPUClass), + .class_init = hexagon_cpu_class_init, + }, + DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), +}; + +DEFINE_TYPES(hexagon_cpu_type_infos) From patchwork Tue Aug 18 15:50:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DC57C433E1 for ; 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18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 9EBDC16D3; Tue, 18 Aug 2020 10:50:55 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 05/34] Hexagon (target/hexagon) register names Date: Tue, 18 Aug 2020 10:50:18 -0500 Message-Id: <1597765847-16637-6-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/hex_regs.h | 83 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h new file mode 100644 index 0000000..3b4249a --- /dev/null +++ b/target/hexagon/hex_regs.h @@ -0,0 +1,83 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_REGS_H +#define HEXAGON_REGS_H + +enum { + HEX_REG_R00 = 0, + HEX_REG_R01 = 1, + HEX_REG_R02 = 2, + HEX_REG_R03 = 3, + HEX_REG_R04 = 4, + HEX_REG_R05 = 5, + HEX_REG_R06 = 6, + HEX_REG_R07 = 7, + HEX_REG_R08 = 8, + HEX_REG_R09 = 9, + HEX_REG_R10 = 10, + HEX_REG_R11 = 11, + HEX_REG_R12 = 12, + HEX_REG_R13 = 13, + HEX_REG_R14 = 14, + HEX_REG_R15 = 15, + HEX_REG_R16 = 16, + HEX_REG_R17 = 17, + HEX_REG_R18 = 18, + HEX_REG_R19 = 19, + HEX_REG_R20 = 20, + HEX_REG_R21 = 21, + HEX_REG_R22 = 22, + HEX_REG_R23 = 23, + HEX_REG_R24 = 24, + HEX_REG_R25 = 25, + HEX_REG_R26 = 26, + HEX_REG_R27 = 27, + HEX_REG_R28 = 28, + HEX_REG_R29 = 29, + HEX_REG_SP = 29, + HEX_REG_FP = 30, + HEX_REG_R30 = 30, + HEX_REG_LR = 31, + HEX_REG_R31 = 31, + HEX_REG_SA0 = 32, + HEX_REG_LC0 = 33, + HEX_REG_SA1 = 34, + HEX_REG_LC1 = 35, + HEX_REG_P3_0 = 36, + HEX_REG_M0 = 38, + HEX_REG_M1 = 39, + HEX_REG_USR = 40, + HEX_REG_PC = 41, + HEX_REG_UGP = 42, + HEX_REG_GP = 43, + HEX_REG_CS0 = 44, + HEX_REG_CS1 = 45, + HEX_REG_UPCYCLELO = 46, + HEX_REG_UPCYCLEHI = 47, + HEX_REG_FRAMELIMIT = 48, + HEX_REG_FRAMEKEY = 49, + HEX_REG_PKTCNTLO = 50, + HEX_REG_PKTCNTHI = 51, + /* Use reserved control registers for qemu execution counts */ + HEX_REG_QEMU_PKT_CNT = 52, + HEX_REG_QEMU_INSN_CNT = 53, + HEX_REG_UTIMERLO = 62, + HEX_REG_UTIMERHI = 63, +}; + +#endif From patchwork Tue Aug 18 15:50:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C044DC433DF for ; Tue, 18 Aug 2020 16:08:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CCE02076E for ; Tue, 18 Aug 2020 16:08:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="zpGIxdXR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7CCE02076E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k849s-0002X2-Mr for qemu-devel@archiver.kernel.org; Tue, 18 Aug 2020 12:08:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tL-0006iX-8S for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:15 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:55147) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tH-0005r3-2y for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765871; x=1629301871; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZP82MTfYnmOflHHB8pyYBGXkzdx6M6wBBtL8qISwEto=; b=zpGIxdXRTzivNTgeI+J2LDxkH3++nvnxVNOUa94jfy1njf4xpBd3k7LA AFtCXFEusom89M7nLaXqZCtyveWmFlSUeFmhPSpBT3iHUHkluVYb3b+vX qBRoBCXuCphj6HtoYExnpID5HhPyGmQlrJQ4EbJCAQoc7aWBobGd+5IN6 U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D30E317F5; Tue, 18 Aug 2020 10:50:55 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 07/34] Hexagon (target/hexagon) scalar core helpers Date: Tue, 18 Aug 2020 10:50:20 -0500 Message-Id: <1597765847-16637-8-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 33 ++++ target/hexagon/op_helper.c | 368 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 401 insertions(+) create mode 100644 target/hexagon/helper.h create mode 100644 target/hexagon/op_helper.c diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h new file mode 100644 index 0000000..48b1917 --- /dev/null +++ b/target/hexagon/helper.h @@ -0,0 +1,33 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_1(debug_start_packet, void, env) +DEF_HELPER_3(debug_check_store_width, void, env, int, int) +DEF_HELPER_3(debug_commit_end, void, env, int, int) +DEF_HELPER_3(merge_inflight_store1s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store1u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store2s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store2u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store4s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store4u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store8u, s64, env, s32, s64) + +#include "helper_protos_generated.h" + +DEF_HELPER_2(debug_value, void, env, s32) +DEF_HELPER_2(debug_value_i64, void, env, s64) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c new file mode 100644 index 0000000..f86d45b --- /dev/null +++ b/target/hexagon/op_helper.c @@ -0,0 +1,368 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include "qemu/osdep.h" +#include "qemu.h" +#include "exec/helper-proto.h" +#include "cpu.h" +#include "internal.h" +#include "macros.h" +#include "arch.h" +#include "fma_emu.h" +#include "conv_emu.h" + +/* Exceptions processing helpers */ +static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env, + uint32_t exception, + uintptr_t pc) +{ + CPUState *cs = CPU(hexagon_env_get_cpu(env)); + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); + cs->exception_index = exception; + cpu_loop_exit_restore(cs, pc); +} + +void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exception) +{ + do_raise_exception_err(env, exception, 0); +} + +static inline void log_reg_write(CPUHexagonState *env, int rnum, + target_ulong val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")", + rnum, val, val); + if (env->slot_cancelled & (1 << slot)) { + HEX_DEBUG_LOG(" CANCELLED"); + } + if (val == env->gpr[rnum]) { + HEX_DEBUG_LOG(" NO CHANGE"); + } + HEX_DEBUG_LOG("\n"); + if (!(env->slot_cancelled & (1 << slot))) { + env->new_value[rnum] = val; +#if HEX_DEBUG + /* Do this so HELPER(debug_commit_end) will know */ + env->reg_written[rnum] = 1; +#endif + } +} + +static __attribute__((unused)) +inline void log_reg_write_pair(CPUHexagonState *env, int rnum, + int64_t val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val); + log_reg_write(env, rnum, val & 0xFFFFFFFF, slot); + log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot); +} + +static inline void log_pred_write(CPUHexagonState *env, int pnum, + target_ulong val) +{ + HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld + " (0x" TARGET_FMT_lx ")\n", + pnum, val, val); + + /* Multiple writes to the same preg are and'ed together */ + if (env->pred_written & (1 << pnum)) { + env->new_pred_value[pnum] &= val & 0xff; + } else { + env->new_pred_value[pnum] = val & 0xff; + env->pred_written |= 1 << pnum; + } +} + +static inline void log_store32(CPUHexagonState *env, target_ulong addr, + target_ulong val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld + " [0x" TARGET_FMT_lx "])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data32 = val; +} + +static inline void log_store64(CPUHexagonState *env, target_ulong addr, + int64_t val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data64 = val; +} + +static inline void write_new_pc(CPUHexagonState *env, target_ulong addr) +{ + HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); + + /* + * If more than one branch is taken in a packet, only the first one + * is actually done. + */ + if (env->branch_taken) { + HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " + "ignoring the second one\n"); + } else { + fCHECK_PCALIGN(addr); + env->branch_taken = 1; + env->next_PC = addr; + } +} + +/* Handy place to set a breakpoint */ +void HELPER(debug_start_packet)(CPUHexagonState *env) +{ + HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", + env->gpr[HEX_REG_PC]); + + int i; + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + env->reg_written[i] = 0; + } +} + +static inline int32_t new_pred_value(CPUHexagonState *env, int pnum) +{ + return env->new_pred_value[pnum]; +} + +/* Checks for bookkeeping errors between disassembly context and runtime */ +void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) +{ + if (env->mem_log_stores[slot].width != check) { + HEX_DEBUG_LOG("ERROR: %d != %d\n", + env->mem_log_stores[slot].width, check); + g_assert_not_reached(); + } +} + +static void print_store(CPUHexagonState *env, int slot) +{ + if (!(env->slot_cancelled & (1 << slot))) { + size1u_t width = env->mem_log_stores[slot].width; + if (width == 1) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xff; + HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %d (0x%02x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 2) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xffff; + HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %d (0x%04x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 4) { + size4u_t data = env->mem_log_stores[slot].data32; + HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %d (0x%08x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 8) { + HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu (0x%016lx)\n", + env->mem_log_stores[slot].va, + env->mem_log_stores[slot].data64, + env->mem_log_stores[slot].data64); + } else { + HEX_DEBUG_LOG("\tBad store width %d\n", width); + g_assert_not_reached(); + } + } +} + +/* This function is a handy place to set a breakpoint */ +void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) +{ + bool reg_printed = false; + bool pred_printed = false; + int i; + + HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", + env->this_PC); + HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled); + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + if (env->reg_written[i]) { + if (!reg_printed) { + HEX_DEBUG_LOG("Regs written\n"); + reg_printed = true; + } + HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", + i, env->new_value[i], env->new_value[i]); + } + } + + for (i = 0; i < NUM_PREGS; i++) { + if (env->pred_written & (1 << i)) { + if (!pred_printed) { + HEX_DEBUG_LOG("Predicates written\n"); + pred_printed = true; + } + HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", + i, env->new_pred_value[i]); + } + } + + if (has_st0 || has_st1) { + HEX_DEBUG_LOG("Stores\n"); + if (has_st0) { + print_store(env, 0); + } + if (has_st1) { + print_store(env, 1); + } + } + + HEX_DEBUG_LOG("Next PC = 0x%x\n", env->next_PC); + HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx + ", insn = " TARGET_FMT_lx + "\n", + env->gpr[HEX_REG_QEMU_PKT_CNT], + env->gpr[HEX_REG_QEMU_INSN_CNT]); + +} + +/* + * Handle mem_noshuf + * + * This occurs when there is a load that might need data forwarded + * from an inflight store in slot 1. Note that the load and store + * might have different sizes, so we can't simply compare the + * addresses. We merge only the bytes that overlap (if any). + */ +static int64_t merge_bytes(CPUHexagonState *env, target_ulong load_addr, + int64_t load_data, uint32_t load_width) +{ + /* Don't do anything if slot 1 was cancelled */ + const int store_slot = 1; + if (env->slot_cancelled & (1 << store_slot)) { + return load_data; + } + + int store_width = env->mem_log_stores[store_slot].width; + target_ulong store_addr = env->mem_log_stores[store_slot].va; + union { + uint8_t bytes[8]; + uint32_t data32; + uint64_t data64; + } retdata, storedata; + int bigmask = ((-load_width) & (-store_width)); + if ((load_addr & bigmask) != (store_addr & bigmask)) { + /* no overlap */ + return load_data; + } + retdata.data64 = load_data; + + if (store_width == 1 || store_width == 2 || store_width == 4) { + storedata.data32 = env->mem_log_stores[store_slot].data32; + } else if (store_width == 8) { + storedata.data64 = env->mem_log_stores[store_slot].data64; + } else { + g_assert_not_reached(); + } + int i, j; + i = store_addr & (load_width - 1); + j = load_addr & (store_width - 1); + while ((i < load_width) && (j < store_width)) { + retdata.bytes[i] = storedata.bytes[j]; + i++; + j++; + } + return retdata.data64; +} + +#define MERGE_INFLIGHT(NAME, RET, IN_TYPE, OUT_TYPE, SIZE) \ +RET HELPER(NAME)(CPUHexagonState *env, int32_t addr, IN_TYPE data) \ +{ \ + return (OUT_TYPE)merge_bytes(env, addr, data, SIZE); \ +} + +MERGE_INFLIGHT(merge_inflight_store1s, int32_t, int32_t, int8_t, 1) +MERGE_INFLIGHT(merge_inflight_store1u, int32_t, int32_t, uint8_t, 1) +MERGE_INFLIGHT(merge_inflight_store2s, int32_t, int32_t, int16_t, 2) +MERGE_INFLIGHT(merge_inflight_store2u, int32_t, int32_t, uint16_t, 2) +MERGE_INFLIGHT(merge_inflight_store4s, int32_t, int32_t, int32_t, 4) +MERGE_INFLIGHT(merge_inflight_store4u, int32_t, int32_t, uint32_t, 4) +MERGE_INFLIGHT(merge_inflight_store8u, int64_t, int64_t, int64_t, 8) + +#define CHECK_NOSHUF(DST, VA, SZ, SIGN) \ + do { \ + if (slot == 0 && env->pkt_has_store_s1) { \ + DST = HELPER(merge_inflight_store##SZ##SIGN)(env, VA, DST); \ + } \ + } while (0) + +static inline uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint8_t retval; + get_user_u8(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 1, u); + return retval; +} + +static inline uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint16_t retval; + get_user_u16(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 2, u); + return retval; +} + +static inline uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint32_t retval; + get_user_u32(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 4, u); + return retval; +} + +static inline uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint64_t retval; + get_user_u64(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 8, u); + return retval; +} + +/* Helpful for printing intermediate values within instructions */ +void HELPER(debug_value)(CPUHexagonState *env, int32_t value) +{ + HEX_DEBUG_LOG("value = 0x%x\n", value); +} + +void HELPER(debug_value_i64)(CPUHexagonState *env, int64_t value) +{ + HEX_DEBUG_LOG("value_i64 = 0x%lx\n", value); +} + +static void cancel_slot(CPUHexagonState *env, uint32_t slot) +{ + HEX_DEBUG_LOG("Slot %d cancelled\n", slot); + env->slot_cancelled |= (1 << slot); +} + +/* These macros can be referenced in the generated helper functions */ +#define warn(...) /* Nothing */ +#define fatal(...) g_assert_not_reached(); + +#define BOGUS_HELPER(tag) \ + printf("ERROR: bogus helper: " #tag "\n") + +#include "helper_funcs_generated.h" + From patchwork Tue Aug 18 15:50:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA48C433DF for ; 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18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 21B447BD; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 10/34] Hexagon (target/hexagon) instruction and packet types Date: Tue, 18 Aug 2020 10:50:23 -0500 Message-Id: <1597765847-16637-11-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson --- target/hexagon/insn.h | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 target/hexagon/insn.h diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h new file mode 100644 index 0000000..aa2d1dd --- /dev/null +++ b/target/hexagon/insn.h @@ -0,0 +1,75 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_INSN_H +#define HEXAGON_INSN_H + +#include "cpu.h" +#include "hex_arch_types.h" + +#define INSTRUCTIONS_MAX 7 /* 2 pairs + loopend */ +#define REG_OPERANDS_MAX 5 +#define IMMEDS_MAX 2 + +struct Instruction; +struct Packet; +struct DisasContext; + +typedef void (*semantic_insn_t)(CPUHexagonState *env, + struct DisasContext *ctx, + struct Instruction *insn, + struct Packet *pkt); + +struct Instruction { + semantic_insn_t generate; /* pointer to genptr routine */ + size1u_t regno[REG_OPERANDS_MAX]; /* reg operands including predicates */ + size2u_t opcode; + + size4u_t iclass:6; + size4u_t slot:3; + size4u_t part1:1; /* + * cmp-jumps are split into two insns. + * set for the compare and clear for the jump + */ + size4u_t extension_valid:1; /* Has a constant extender attached */ + size4u_t which_extended:1; /* If has an extender, which immediate */ + size4u_t is_endloop:1; /* This is an end of loop */ + size4u_t new_value_producer_slot:4; + size4s_t immed[IMMEDS_MAX]; /* immediate field */ +}; + +typedef struct Instruction insn_t; + +struct Packet { + size2u_t num_insns; + size2u_t encod_pkt_size_in_bytes; + + /* Pre-decodes about COF */ + size8u_t pkt_has_cof:1; /* Has any change-of-flow */ + size8u_t pkt_has_endloop:1; + + size8u_t pkt_has_dczeroa:1; + + size8u_t pkt_has_store_s0:1; + size8u_t pkt_has_store_s1:1; + + insn_t insn[INSTRUCTIONS_MAX]; +}; + +typedef struct Packet packet_t; + +#endif From patchwork Tue Aug 18 15:50:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44278C433DF for ; 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18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 573FE8F7; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 12/34] Hexagon (target/hexagon) instruction attributes Date: Tue, 18 Aug 2020 10:50:25 -0500 Message-Id: <1597765847-16637-13-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/attribs.h | 32 +++++++++++++++ target/hexagon/attribs_def.h | 98 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 target/hexagon/attribs.h create mode 100644 target/hexagon/attribs_def.h diff --git a/target/hexagon/attribs.h b/target/hexagon/attribs.h new file mode 100644 index 0000000..d35af0c --- /dev/null +++ b/target/hexagon/attribs.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ATTRIBS_H +#define HEXAGON_ATTRIBS_H + +enum { +#define DEF_ATTRIB(NAME, ...) A_##NAME, +#include "attribs_def.h" +#undef DEF_ATTRIB +}; + +#define ATTRIB_WIDTH 32 +#define GET_ATTRIB(opcode, attrib) \ + (((opcode_attribs[opcode][attrib / ATTRIB_WIDTH])\ + >> (attrib % ATTRIB_WIDTH)) & 0x1) + +#endif /* ATTRIBS_H */ diff --git a/target/hexagon/attribs_def.h b/target/hexagon/attribs_def.h new file mode 100644 index 0000000..d024176 --- /dev/null +++ b/target/hexagon/attribs_def.h @@ -0,0 +1,98 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* Keep this as the first attribute: */ +DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "") + +/* Misc */ +DEF_ATTRIB(EXTENSION, "Extension instruction", "", "") + +DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "") +DEF_ATTRIB(GUEST, "Not available in user mode", "", "") + +DEF_ATTRIB(FPOP, "Floating Point Operation", "", "") + +DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "") + +DEF_ATTRIB(ARCHV2, "V2 architecture", "", "") +DEF_ATTRIB(ARCHV3, "V3 architecture", "", "") +DEF_ATTRIB(ARCHV4, "V4 architecture", "", "") +DEF_ATTRIB(ARCHV5, "V5 architecture", "", "") + +DEF_ATTRIB(SUBINSN, "sub-instruction", "", "") + +/* Load and Store attributes */ +DEF_ATTRIB(LOAD, "Loads from memory", "", "") +DEF_ATTRIB(STORE, "Stores to memory", "", "") +DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "") +DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "") + + +/* Change-of-flow attributes */ +DEF_ATTRIB(JUMP, "Jump-type instruction", "", "") +DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "") +DEF_ATTRIB(CALL, "Function call instruction", "", "") +DEF_ATTRIB(COF, "Change-of-flow instruction", "", "") +DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "") +DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "") +DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "") + +/* access to implicit registers */ +DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR") +DEF_ATTRIB(IMPLICIT_WRITES_PC, "Writes the program counter", "", "UREG.PC") +DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP") +DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP") +DEF_ATTRIB(IMPLICIT_WRITES_GP, "Writes the GP register", "", "UREG.GP") +DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0") +DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1") +DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0") +DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1") +DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0") +DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1") +DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") +DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") + +DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") +DEF_ATTRIB(IT_NOP, "nop instruction", "", "") +DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "") + + +/* Restrictions to make note of */ +DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "") +DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "") +DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "") +DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "") +DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "") +DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "") + +DEF_ATTRIB(ICOP, "Instruction cache op", "", "") + +DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "") +DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "") +DEF_ATTRIB(DCZEROA, "dczeroa type", "", "") +DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "") +DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "") +DEF_ATTRIB(DCFETCH, "dcfetch type", "", "") + +DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "") + +DEF_ATTRIB(ICINVA, "icinva", "", "") +DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "") + +/* Keep this as the last attribute: */ +DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") + From patchwork Tue Aug 18 15:50:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4515C433E1 for ; Tue, 18 Aug 2020 15:54:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E15E2080C for ; Tue, 18 Aug 2020 15:54:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="yImP2DRW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6E15E2080C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k83wF-0003oq-GU for qemu-devel@archiver.kernel.org; Tue, 18 Aug 2020 11:54:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tI-0006du-Lh for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:12 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:12941) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tE-0005sP-Th for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765868; x=1629301868; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tUWIh60VIBZ0LRuhNAwMPb0vZxGR3JoiB9ulRsp8naY=; b=yImP2DRWKS+9UDZdC0j3gkUr8rZKhQpRAlOzP+GiaWIJzD3DHDbf0vuG YKjzCRBfRSZjdp/bK5FiqjF0+p9npVeP6cZYlnOK2Bh/vgAN4cxf7Ke+c 7CTZe/9vpxC3QmkYOhx5Obh68IJy7nyXoUsc5akleidL7mt22aQZSoUIJ s=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:50:57 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 6ADFD1A4A; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 13/34] Hexagon (target/hexagon) register map Date: Tue, 18 Aug 2020 10:50:26 -0500 Message-Id: <1597765847-16637-14-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Certain operand types represent a non-contiguous set of values. For example, the compound compare-and-jump instruction can only access registers R0-R7 and R16-23. This table represents the mapping from the encoding to the actual values. Signed-off-by: Taylor Simpson --- target/hexagon/regmap.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 target/hexagon/regmap.h diff --git a/target/hexagon/regmap.h b/target/hexagon/regmap.h new file mode 100644 index 0000000..2bcc0de --- /dev/null +++ b/target/hexagon/regmap.h @@ -0,0 +1,38 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Certain operand types represent a non-contiguous set of values. + * For example, the compound compare-and-jump instruction can only access + * registers R0-R7 and R16-23. + * This table represents the mapping from the encoding to the actual values. + */ + +#ifndef HEXAGON_REGMAP_H +#define HEXAGON_REGMAP_H + + /* Name Num Table */ +DEF_REGMAP(R_16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23) +DEF_REGMAP(R__8, 8, 0, 2, 4, 6, 16, 18, 20, 22) +DEF_REGMAP(R__4, 4, 0, 2, 4, 6) +DEF_REGMAP(R_4, 4, 0, 1, 2, 3) +DEF_REGMAP(R_8S, 8, 0, 1, 2, 3, 16, 17, 18, 19) +DEF_REGMAP(R_8, 8, 0, 1, 2, 3, 4, 5, 6, 7) +DEF_REGMAP(V__8, 8, 0, 4, 8, 12, 16, 20, 24, 28) +DEF_REGMAP(V__16, 16, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30) + +#endif From patchwork Tue Aug 18 15:50:27 2020 Content-Type: text/plain; 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dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k83yF-0007aB-Qc for qemu-devel@archiver.kernel.org; Tue, 18 Aug 2020 11:56:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tK-0006gt-Cq for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:14 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:12936) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tF-0005rl-E6 for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765869; x=1629301869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zrMTkdkNJVB1lA8gjwiL80FK8ZHm5uJLdu8wbhwUcCY=; b=kIMrAaz5wY0MmtumrTkyWXK56VRqmFhDQqbqbSrOu4qzK804ZksSIfS8 tXHWBgwAduTL7n+fBqOI4a3EiwErlKzvoJWz55fOTMPDgca4hAD3WwzmT 9TBtyTllJBD2y6ctgLkiHVFqCpJECnB/lPXQmvc7vFizHNslPlUUhAWiJ c=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:50:57 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 8C2DF1618; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 14/34] Hexagon (target/hexagon) instruction/packet decode Date: Tue, 18 Aug 2020 10:50:27 -0500 Message-Id: <1597765847-16637-15-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson --- target/hexagon/decode.h | 39 +++ target/hexagon/decode.c | 593 ++++++++++++++++++++++++++++++++++++++++++++ target/hexagon/q6v_decode.c | 373 ++++++++++++++++++++++++++++ 3 files changed, 1005 insertions(+) create mode 100644 target/hexagon/decode.h create mode 100644 target/hexagon/decode.c create mode 100644 target/hexagon/q6v_decode.c diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h new file mode 100644 index 0000000..7f63b1c --- /dev/null +++ b/target/hexagon/decode.h @@ -0,0 +1,39 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_DECODE_H +#define HEXAGON_DECODE_H + +#include "cpu.h" +#include "opcodes.h" +#include "hex_arch_types.h" +#include "insn.h" + +extern void decode_init(void); + +static inline int is_packet_end(uint32_t word) +{ + uint32_t bits = (word >> 14) & 0x3; + return ((bits == 0x3) || (bits == 0x0)); +} + +extern void decode_send_insn_to(packet_t *packet, int start, int newloc); + +extern packet_t *decode_this(int max_words, size4u_t *words, + packet_t *decode_pkt); + +#endif diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c new file mode 100644 index 0000000..2e882bc --- /dev/null +++ b/target/hexagon/decode.c @@ -0,0 +1,593 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "iclass.h" +#include "opcodes.h" +#include "genptr.h" +#include "decode.h" +#include "insn.h" +#include "printinsn.h" + +#define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) + +enum { + EXT_IDX_noext = 0, + EXT_IDX_noext_AFTER = 4, + EXT_IDX_mmvec = 4, + EXT_IDX_mmvec_AFTER = 8, + XX_LAST_EXT_IDX +}; + +#define DEF_REGMAP(NAME, ELEMENTS, ...) \ + static const unsigned int DECODE_REGISTER_##NAME[ELEMENTS] = \ + { __VA_ARGS__ }; +#include "regmap.h" + +#define DECODE_MAPPED_REG(REGNO, NAME) \ + insn->regno[REGNO] = DECODE_REGISTER_##NAME[insn->regno[REGNO]]; + +typedef struct { + struct _dectree_table_struct *table_link; + struct _dectree_table_struct *table_link_b; + opcode_t opcode; + enum { + DECTREE_ENTRY_INVALID, + DECTREE_TABLE_LINK, + DECTREE_SUBINSNS, + DECTREE_EXTSPACE, + DECTREE_TERMINAL + } type; +} dectree_entry_t; + +typedef struct _dectree_table_struct { + unsigned int (*lookup_function)(int startbit, int width, size4u_t opcode); + unsigned int size; + unsigned int startbit; + unsigned int width; + dectree_entry_t table[]; +} dectree_table_t; + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \ + static struct _dectree_table_struct dectree_table_##TAG; +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#include "dectree_generated.h" + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +#define DECODE_SEPARATOR_BITS(START, WIDTH) NULL, START, WIDTH +#define DECODE_NEW_TABLE_HELPER(TAG, SIZE, FN, START, WIDTH) \ + static dectree_table_t dectree_table_##TAG = { \ + .size = SIZE, \ + .lookup_function = FN, \ + .startbit = START, \ + .width = WIDTH, \ + .table = { +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \ + DECODE_NEW_TABLE_HELPER(TAG, SIZE, WHATNOT) + +#define TABLE_LINK(TABLE) \ + { .type = DECTREE_TABLE_LINK, .table_link = &dectree_table_##TABLE }, +#define TERMINAL(TAG, ENC) \ + { .type = DECTREE_TERMINAL, .opcode = TAG }, +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) \ + { \ + .type = DECTREE_SUBINSNS, \ + .table_link = &dectree_table_DECODE_SUBINSN_##CLASSA, \ + .table_link_b = &dectree_table_DECODE_SUBINSN_##CLASSB \ + }, +#define EXTSPACE(TAG, ENC) { .type = DECTREE_EXTSPACE }, +#define INVALID() { .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE }, + +#define DECODE_END_TABLE(...) } }; + +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#include "dectree_generated.h" + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_NEW_TABLE_HELPER +#undef DECODE_SEPARATOR_BITS + +static dectree_table_t dectree_table_DECODE_EXT_EXT_noext = { + .size = 1, .lookup_function = NULL, .startbit = 0, .width = 0, + .table = { + { .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE }, + } +}; + +static dectree_table_t *ext_trees[XX_LAST_EXT_IDX]; + +static void decode_ext_init(void) +{ + int i; + for (i = EXT_IDX_noext; i < EXT_IDX_noext_AFTER; i++) { + ext_trees[i] = &dectree_table_DECODE_EXT_EXT_noext; + } +} + +typedef struct { + size4u_t mask; + size4u_t match; +} decode_itable_entry_t; + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) /* NOTHING */ +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#define DECODE_MATCH_INFO_NORMAL(TAG, MASK, MATCH) \ + [TAG] = { \ + .mask = MASK, \ + .match = MATCH, \ + }, + +#define DECODE_MATCH_INFO_NULL(TAG, MASK, MATCH) \ + [TAG] = { .match = ~0 }, + +#define DECODE_MATCH_INFO(...) DECODE_MATCH_INFO_NORMAL(__VA_ARGS__) +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ + +static const decode_itable_entry_t decode_itable[XX_LAST_OPCODE] = { +#include "dectree_generated.h" +}; + +#undef DECODE_MATCH_INFO +#define DECODE_MATCH_INFO(...) DECODE_MATCH_INFO_NULL(__VA_ARGS__) + +#undef DECODE_LEGACY_MATCH_INFO +#define DECODE_LEGACY_MATCH_INFO(...) DECODE_MATCH_INFO_NORMAL(__VA_ARGS__) + +static const decode_itable_entry_t decode_legacy_itable[XX_LAST_OPCODE] = { +#include "dectree_generated.h" +}; + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +void decode_init(void) +{ + decode_ext_init(); +} + +void decode_send_insn_to(packet_t *packet, int start, int newloc) +{ + insn_t tmpinsn; + int direction; + int i; + if (start == newloc) { + return; + } + if (start < newloc) { + /* Move towards end */ + direction = 1; + } else { + /* move towards beginning */ + direction = -1; + } + for (i = start; i != newloc; i += direction) { + tmpinsn = packet->insn[i]; + packet->insn[i] = packet->insn[i + direction]; + packet->insn[i + direction] = tmpinsn; + } +} + +/* Fill newvalue registers with the correct regno */ +static int +decode_fill_newvalue_regno(packet_t *packet) +{ + int i, use_regidx, def_idx; + size2u_t def_opcode, use_opcode; + char *dststr; + + for (i = 1; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE) && + !GET_ATTRIB(packet->insn[i].opcode, A_EXTENSION)) { + use_opcode = packet->insn[i].opcode; + + /* It's a store, so we're adjusting the Nt field */ + if (GET_ATTRIB(use_opcode, A_STORE)) { + use_regidx = strchr(opcode_reginfo[use_opcode], 't') - + opcode_reginfo[use_opcode]; + } else { /* It's a Jump, so we're adjusting the Ns field */ + use_regidx = strchr(opcode_reginfo[use_opcode], 's') - + opcode_reginfo[use_opcode]; + } + + /* + * What's encoded at the N-field is the offset to who's producing + * the value. Shift off the LSB which indicates odd/even register. + */ + def_idx = i - ((packet->insn[i].regno[use_regidx]) >> 1); + + /* + * Check for a badly encoded N-field which points to an instruction + * out-of-range + */ + if ((def_idx < 0) || (def_idx > (packet->num_insns - 1))) { + g_assert_not_reached(); + return 1; + } + + /* previous insn is the producer */ + def_opcode = packet->insn[def_idx].opcode; + dststr = strstr(opcode_wregs[def_opcode], "Rd"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'd'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Rx"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'x'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Re"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'e'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Ry"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'y'); + } else { + g_assert_not_reached(); + return 1; + } + } + } + } + g_assert(dststr != NULL); + + /* Now patch up the consumer with the register number */ + packet->insn[i].regno[use_regidx] = + packet->insn[def_idx].regno[dststr - + opcode_reginfo[def_opcode]]; + /* + * We need to remember who produces this value to later + * check if it was dynamically cancelled + */ + packet->insn[i].new_value_producer_slot = + packet->insn[def_idx].slot; + } + } + return 0; +} + +/* Split CJ into a compare and a jump */ +static int decode_split_cmpjump(packet_t *pkt) +{ + int last, i; + int numinsns = pkt->num_insns; + + /* + * First, split all compare-jumps. + * The compare is sent to the end as a new instruction. + * Do it this way so we don't reorder dual jumps. Those need to stay in + * original order. + */ + for (i = 0; i < numinsns; i++) { + /* It's a cmp-jump */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_NEWCMPJUMP)) { + last = pkt->num_insns; + pkt->insn[last] = pkt->insn[i]; /* copy the instruction */ + pkt->insn[last].part1 = 1; /* last instruction does the CMP */ + pkt->insn[i].part1 = 0; /* existing instruction does the JUMP */ + pkt->num_insns++; + } + } + + /* Now re-shuffle all the compares back to the beginning */ + for (i = 0; i < pkt->num_insns; i++) { + if (pkt->insn[i].part1) { + decode_send_insn_to(pkt, i, 0); + } + } + return 0; +} + +static inline int decode_opcode_can_jump(int opcode) +{ + if ((GET_ATTRIB(opcode, A_JUMP)) || + (GET_ATTRIB(opcode, A_CALL)) || + (opcode == J2_trap0)) { + /* Exception to A_JUMP attribute */ + if (opcode == J4_hintjumpr) { + return 0; + } + return 1; + } + + return 0; +} + +static inline int decode_opcode_ends_loop(int opcode) +{ + return GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END); +} + +/* Set the is_* fields in each instruction */ +static int decode_set_insn_attr_fields(packet_t *pkt) +{ + int i; + int numinsns = pkt->num_insns; + size2u_t opcode; + int canjump; + + pkt->pkt_has_cof = 0; + pkt->pkt_has_endloop = 0; + pkt->pkt_has_dczeroa = 0; + + for (i = 0; i < numinsns; i++) { + opcode = pkt->insn[i].opcode; + if (pkt->insn[i].part1) { + continue; /* Skip compare of cmp-jumps */ + } + + if (GET_ATTRIB(opcode, A_DCZEROA)) { + pkt->pkt_has_dczeroa = 1; + } + + if (GET_ATTRIB(opcode, A_STORE)) { + if (pkt->insn[i].slot == 0) { + pkt->pkt_has_store_s0 = 1; + } else { + pkt->pkt_has_store_s1 = 1; + } + } + + canjump = decode_opcode_can_jump(opcode); + pkt->pkt_has_cof |= canjump; + + pkt->insn[i].is_endloop = decode_opcode_ends_loop(opcode); + + pkt->pkt_has_endloop |= pkt->insn[i].is_endloop; + + pkt->pkt_has_cof |= pkt->pkt_has_endloop; + } + + return 0; +} + +/* + * Shuffle for execution + * Move stores to end (in same order as encoding) + * Move compares to beginning (for use by .new insns) + */ +static int decode_shuffle_for_execution(packet_t *packet) +{ + int changed = 0; + int i; + int flag; /* flag means we've seen a non-memory instruction */ + int n_mems; + int last_insn = packet->num_insns - 1; + + /* + * Skip end loops, somehow an end loop is getting in and messing + * up the order + */ + if (decode_opcode_ends_loop(packet->insn[last_insn].opcode)) { + last_insn--; + } + + do { + changed = 0; + /* + * Stores go last, must not reorder. + * Cannot shuffle stores past loads, either. + * Iterate backwards. If we see a non-memory instruction, + * then a store, shuffle the store to the front. Don't shuffle + * stores wrt each other or a load. + */ + for (flag = n_mems = 0, i = last_insn; i >= 0; i--) { + int opcode = packet->insn[i].opcode; + + if (flag && GET_ATTRIB(opcode, A_STORE)) { + decode_send_insn_to(packet, i, last_insn - n_mems); + n_mems++; + changed = 1; + } else if (GET_ATTRIB(opcode, A_STORE)) { + n_mems++; + } else if (GET_ATTRIB(opcode, A_LOAD)) { + /* + * Don't set flag, since we don't want to shuffle a + * store pasta load + */ + n_mems++; + } else if (GET_ATTRIB(opcode, A_DOTNEWVALUE)) { + /* + * Don't set flag, since we don't want to shuffle past + * a .new value + */ + } else { + flag = 1; + } + } + + if (changed) { + continue; + } + /* Compares go first, may be reordered wrt each other */ + for (flag = 0, i = 0; i < last_insn + 1; i++) { + int opcode = packet->insn[i].opcode; + + if ((strstr(opcode_wregs[opcode], "Pd4") || + strstr(opcode_wregs[opcode], "Pe4")) && + GET_ATTRIB(opcode, A_STORE) == 0) { + /* This should be a compare (not a store conditional) */ + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P3) && + !decode_opcode_ends_loop(packet->insn[i].opcode)) { + /* + * spNloop instruction + * Don't reorder endloops; they are not valid for .new uses, + * and we want to match HW + */ + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P0) && + !GET_ATTRIB(opcode, A_NEWCMPJUMP)) { + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else { + flag = 1; + } + } + if (changed) { + continue; + } + } while (changed); + + /* + * If we have a .new register compare/branch, move that to the very + * very end, past stores + */ + for (i = 0; i < last_insn; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE)) { + decode_send_insn_to(packet, i, last_insn); + break; + } + } + + return 0; +} + +static int +apply_extender(packet_t *pkt, int i, size4u_t extender) +{ + int immed_num; + size4u_t base_immed; + + immed_num = opcode_which_immediate_is_extended(pkt->insn[i].opcode); + base_immed = pkt->insn[i].immed[immed_num]; + + pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed); + return 0; +} + +static int decode_apply_extenders(packet_t *packet) +{ + int i; + for (i = 0; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { + packet->insn[i + 1].extension_valid = 1; + apply_extender(packet, i + 1, packet->insn[i].immed[0]); + } + } + return 0; +} + +static int decode_remove_extenders(packet_t *packet) +{ + int i, j; + for (i = 0; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { + for (j = i; + (j < packet->num_insns - 1) && (j < INSTRUCTIONS_MAX - 1); + j++) { + packet->insn[j] = packet->insn[j + 1]; + } + packet->num_insns--; + } + } + return 0; +} + +static const char * +get_valid_slot_str(const packet_t *pkt, unsigned int slot) +{ + return find_iclass_slots(pkt->insn[slot].opcode, + pkt->insn[slot].iclass); +} + +#include "q6v_decode.c" + +packet_t *decode_this(int max_words, size4u_t *words, packet_t *decode_pkt) +{ + int ret; + ret = do_decode_packet(max_words, words, decode_pkt); + if (ret <= 0) { + /* ERROR or BAD PARSE */ + return NULL; + } + return decode_pkt; +} + +/* Used for "-d in_asm" logging */ +int disassemble_hexagon(uint32_t *words, int nwords, char *buf, int bufsize) +{ + packet_t pkt; + + if (decode_this(nwords, words, &pkt)) { + snprint_a_pkt(buf, bufsize, &pkt); + return pkt.encod_pkt_size_in_bytes; + } else { + snprintf(buf, bufsize, ""); + return 0; + } +} diff --git a/target/hexagon/q6v_decode.c b/target/hexagon/q6v_decode.c new file mode 100644 index 0000000..c108ac2 --- /dev/null +++ b/target/hexagon/q6v_decode.c @@ -0,0 +1,373 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) /* NOTHING */ +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ + +#define DECODE_REG(REGNO, WIDTH, STARTBIT) \ + insn->regno[REGNO] = ((encoding >> STARTBIT) & ((1 << WIDTH) - 1)); + +#define DECODE_IMPL_REG(REGNO, VAL) \ + insn->regno[REGNO] = VAL; + +#define DECODE_IMM(IMMNO, WIDTH, STARTBIT, VALSTART) \ + insn->immed[IMMNO] |= (((encoding >> STARTBIT) & ((1 << WIDTH) - 1))) << \ + (VALSTART); + +#define DECODE_IMM_SXT(IMMNO, WIDTH) \ + insn->immed[IMMNO] = ((((size4s_t)insn->immed[IMMNO]) << (32 - WIDTH)) >> \ + (32 - WIDTH)); + +#define DECODE_IMM_NEG(IMMNO, WIDTH) \ + insn->immed[IMMNO] = -insn->immed[IMMNO]; + +#define DECODE_IMM_SHIFT(IMMNO, SHAMT) \ + if ((!insn->extension_valid) || \ + (insn->which_extended != IMMNO)) { \ + insn->immed[IMMNO] <<= SHAMT; \ + } + +#define DECODE_OPINFO(TAG, BEH) \ + case TAG: \ + { BEH } \ + break; \ + +static void +decode_op(insn_t *insn, opcode_t tag, size4u_t encoding) +{ + insn->immed[0] = 0; + insn->immed[1] = 0; + insn->opcode = tag; + if (insn->extension_valid) { + insn->which_extended = opcode_which_immediate_is_extended(tag); + } + + switch (tag) { +#include "dectree_generated.h" + default: + break; + } + + insn->generate = opcode_genptr[tag]; + insn->iclass = (encoding >> 28) & 0xf; + if (((encoding >> 14) & 3) == 0) { + insn->iclass += 16; + } +} + +#undef DECODE_REG +#undef DECODE_IMPL_REG +#undef DECODE_IMM +#undef DECODE_IMM_SHIFT +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +static unsigned int +decode_subinsn_tablewalk(insn_t *insn, dectree_table_t *table, + size4u_t encoding) +{ + unsigned int i; + opcode_t opc; + if (table->lookup_function) { + i = table->lookup_function(table->startbit, table->width, encoding); + } else { + i = ((encoding >> table->startbit) & ((1 << table->width) - 1)); + } + if (table->table[i].type == DECTREE_TABLE_LINK) { + return decode_subinsn_tablewalk(insn, table->table[i].table_link, + encoding); + } else if (table->table[i].type == DECTREE_TERMINAL) { + opc = table->table[i].opcode; + if ((encoding & decode_itable[opc].mask) != decode_itable[opc].match) { + return 0; + } + decode_op(insn, opc, encoding); + return 1; + } else { + return 0; + } +} + +static unsigned int get_insn_a(size4u_t encoding) +{ + return encoding & 0x00001fff; +} + +static unsigned int get_insn_b(size4u_t encoding) +{ + return (encoding >> 16) & 0x00001fff; +} + +static unsigned int +decode_insns_tablewalk(insn_t *insn, dectree_table_t *table, size4u_t encoding) +{ + unsigned int i; + unsigned int a, b; + opcode_t opc; + if (table->lookup_function) { + i = table->lookup_function(table->startbit, table->width, encoding); + } else { + i = ((encoding >> table->startbit) & ((1 << table->width) - 1)); + } + if (table->table[i].type == DECTREE_TABLE_LINK) { + return decode_insns_tablewalk(insn, table->table[i].table_link, + encoding); + } else if (table->table[i].type == DECTREE_SUBINSNS) { + a = get_insn_a(encoding); + b = get_insn_b(encoding); + b = decode_subinsn_tablewalk(insn, table->table[i].table_link_b, b); + a = decode_subinsn_tablewalk(insn + 1, table->table[i].table_link, a); + if ((a == 0) || (b == 0)) { + return 0; + } + return 2; + } else if (table->table[i].type == DECTREE_TERMINAL) { + opc = table->table[i].opcode; + if ((encoding & decode_itable[opc].mask) != decode_itable[opc].match) { + if ((encoding & decode_legacy_itable[opc].mask) != + decode_legacy_itable[opc].match) { + return 0; + } + } + decode_op(insn, opc, encoding); + return 1; + } else { + return 0; + } +} + +static unsigned int +decode_insns(insn_t *insn, size4u_t encoding) +{ + dectree_table_t *table; + if ((encoding & 0x0000c000) != 0) { + /* Start with PP table */ + table = &dectree_table_DECODE_ROOT_32; + } else { + /* start with EE table */ + table = &dectree_table_DECODE_ROOT_EE; + } + return decode_insns_tablewalk(insn, table, encoding); +} + +static void decode_add_endloop_insn(insn_t *insn, int loopnum) +{ + if (loopnum == 10) { + insn->opcode = J2_endloop01; + insn->generate = opcode_genptr[J2_endloop01]; + } else if (loopnum == 1) { + insn->opcode = J2_endloop1; + insn->generate = opcode_genptr[J2_endloop1]; + } else { + insn->opcode = J2_endloop0; + insn->generate = opcode_genptr[J2_endloop0]; + } +} + +static inline int decode_parsebits_is_end(size4u_t encoding32) +{ + size4u_t bits = (encoding32 >> 14) & 0x3; + return ((bits == 0x3) || (bits == 0x0)); +} + +static inline int decode_parsebits_is_loopend(size4u_t encoding32) +{ + size4u_t bits = (encoding32 >> 14) & 0x3; + return ((bits == 0x2)); +} + +static int +decode_set_slot_number(packet_t *pkt) +{ + int slot; + int i; + int hit_mem_insn = 0; + int hit_duplex = 0; + const char *valid_slot_str; + + for (i = 0, slot = 3; i < pkt->num_insns; i++) { + valid_slot_str = get_valid_slot_str(pkt, i); + + while (strchr(valid_slot_str, '0' + slot) == NULL) { + slot--; + } + pkt->insn[i].slot = slot; + if (slot) { + /* I've assigned the slot, now decrement it for the next insn */ + slot--; + } + } + + /* Fix the exceptions - mem insns to slot 0,1 */ + for (i = pkt->num_insns - 1; i >= 0; i--) { + + /* First memory instruction always goes to slot 0 */ + if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || + GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && + !hit_mem_insn) { + hit_mem_insn = 1; + pkt->insn[i].slot = 0; + continue; + } + + /* Next memory instruction always goes to slot 1 */ + if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || + GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && + hit_mem_insn) { + pkt->insn[i].slot = 1; + } + } + + /* Fix the exceptions - duplex always slot 0,1 */ + for (i = pkt->num_insns - 1; i >= 0; i--) { + + /* First subinsn always goes to slot 0 */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && !hit_duplex) { + hit_duplex = 1; + pkt->insn[i].slot = 0; + continue; + } + + /* Next subinsn always goes to slot 1 */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && hit_duplex) { + pkt->insn[i].slot = 1; + } + } + + /* Fix the exceptions - slot 1 is never empty, always aligns to slot 0 */ + { + int slot0_found = 0; + int slot1_found = 0; + int slot1_iidx = 0; + for (i = pkt->num_insns - 1; i >= 0; i--) { + /* Is slot0 used? */ + if (pkt->insn[i].slot == 0) { + int is_endloop = (pkt->insn[i].opcode == J2_endloop01); + is_endloop |= (pkt->insn[i].opcode == J2_endloop0); + is_endloop |= (pkt->insn[i].opcode == J2_endloop1); + + /* + * Make sure it's not endloop since, we're overloading + * slot0 for endloop + */ + if (!is_endloop) { + slot0_found = 1; + } + } + /* Is slot1 used? */ + if (pkt->insn[i].slot == 1) { + slot1_found = 1; + slot1_iidx = i; + } + } + /* Is slot0 empty and slot1 used? */ + if ((slot0_found == 0) && (slot1_found == 1)) { + /* Then push it to slot0 */ + pkt->insn[slot1_iidx].slot = 0; + } + } + return 0; +} + +/* + * do_decode_packet + * Decodes packet with given words + * Returns negative on error, 0 on insufficient words, + * and number of words used on success + */ + +static int do_decode_packet(int max_words, const size4u_t *words, packet_t *pkt) +{ + int num_insns = 0; + int words_read = 0; + int end_of_packet = 0; + int new_insns = 0; + int errors = 0; + size4u_t encoding32; + + /* Initialize */ + memset(pkt, 0, sizeof(*pkt)); + /* Try to build packet */ + while (!end_of_packet && (words_read < max_words)) { + encoding32 = words[words_read]; + end_of_packet = decode_parsebits_is_end(encoding32); + new_insns = decode_insns(&pkt->insn[num_insns], encoding32); + /* + * If we saw an extender, mark next word extended so immediate + * decode works + */ + if (pkt->insn[num_insns].opcode == A4_ext) { + pkt->insn[num_insns + 1].extension_valid = 1; + } + num_insns += new_insns; + words_read++; + } + + pkt->num_insns = num_insns; + if (!end_of_packet) { + /* Ran out of words! */ + return 0; + } + pkt->encod_pkt_size_in_bytes = words_read * 4; + + /* Shuffle / split / reorder for execution */ + if ((words_read == 2) && (decode_parsebits_is_loopend(words[0]))) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); + } + if (words_read >= 3) { + size4u_t has_loop0, has_loop1; + has_loop0 = decode_parsebits_is_loopend(words[0]); + has_loop1 = decode_parsebits_is_loopend(words[1]); + if (has_loop0 && has_loop1) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 10); + } else if (has_loop1) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 1); + } else if (has_loop0) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); + } + } + + errors += decode_apply_extenders(pkt); + errors += decode_remove_extenders(pkt); + errors += decode_set_slot_number(pkt); + errors += decode_fill_newvalue_regno(pkt); + + errors += decode_shuffle_for_execution(pkt); + errors += decode_split_cmpjump(pkt); + errors += decode_set_insn_attr_fields(pkt); + if (errors) { + return -1; + } + + return words_read; +} From patchwork Tue Aug 18 15:50:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3CE6C433E1 for ; Tue, 18 Aug 2020 16:12:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71620207DA for ; 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Tue, 18 Aug 2020 11:51:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765869; x=1629301869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ihRUx1xcJmNsWiTFAyr/jP786FX0UTZtmCyzFe5VxYQ=; b=r6+hUKcfBBlwaQacbHr9eY4nH+o/H7UsZyZSbYcsJe3gUU5qavLIqC1i LEajJM+qUvAaejK47cZ5rDz0KimjtK4Zj8v1ffGD0FEWyg4IatTk1MEjO q8t5Beoyc6Kt7VdRmavv9sj/a6tN/hrRQJp2LsQF6lXrud7nRPtUHKjxO 0=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:57 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id F3FD51B76; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 17/34] Hexagon (target/hexagon/imported) arch import - macro definitions Date: Tue, 18 Aug 2020 10:50:30 -0500 Message-Id: <1597765847-16637-18-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The macro definitions specify instruction attributes that are applied to each instruction that references the macro. The generator will recursively apply attributes to each instruction that used the macro. Signed-off-by: Taylor Simpson --- target/hexagon/imported/macros.def | 1529 ++++++++++++++++++++++++++++++++++++ 1 file changed, 1529 insertions(+) create mode 100755 target/hexagon/imported/macros.def diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/macros.def new file mode 100755 index 0000000..affbb1d --- /dev/null +++ b/target/hexagon/imported/macros.def @@ -0,0 +1,1529 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +DEF_MACRO( + LIKELY, /* NAME */ + __builtin_expect((X),1), /* BEH */ + () /* attribs */ +) + +DEF_MACRO( + UNLIKELY, /* NAME */ + __builtin_expect((X),0), /* BEH */ + () /* attribs */ +) + +DEF_MACRO( + CANCEL, /* macro name */ + {if (thread->last_pkt) thread->last_pkt->slot_cancelled |= (1<slot); return;} , /* behavior */ + (A_CONDEXEC) +) + +DEF_MACRO( + LOAD_CANCEL, /* macro name */ + {mem_general_load_cancelled(thread,EA,insn);CANCEL;} , /* behavior */ + (A_CONDEXEC) +) + +DEF_MACRO( + STORE_CANCEL, /* macro name */ + {mem_general_store_cancelled(thread,EA,insn);CANCEL;} , /* behavior */ + (A_CONDEXEC) +) + +DEF_MACRO( + fMAX, /* macro name */ + (((A) > (B)) ? (A) : (B)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fMIN, /* macro name */ + (((A) < (B)) ? (A) : (B)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fABS, /* macro name */ + (((A)<0)?(-(A)):(A)), /* behavior */ + /* optional attributes */ +) + + +/* Bit insert */ +DEF_MACRO( + fINSERT_BITS, + { + REG = ((REG) & ~(((fCONSTLL(1)<<(WIDTH))-1)<<(OFFSET))) | (((INVAL) & ((fCONSTLL(1)<<(WIDTH))-1)) << (OFFSET)); + }, + /* attribs */ +) + +/* Bit extract */ +DEF_MACRO( + fEXTRACTU_BITS, + (fZXTN(WIDTH,32,(INREG >> OFFSET))), + /* attribs */ +) + +DEF_MACRO( + fEXTRACTU_BIDIR, + (fZXTN(WIDTH,32,fBIDIR_LSHIFTR((INREG),(OFFSET),4_8))), + /* attribs */ +) + +DEF_MACRO( + fEXTRACTU_RANGE, + (fZXTN((HIBIT-LOWBIT+1),32,(INREG >> LOWBIT))), + /* attribs */ +) + +DEF_MACRO( + f8BITSOF, + ( (VAL) ? 0xff : 0x00), + /* attribs */ +) + +DEF_MACRO( + fLSBOLD, + ((VAL) & 1), + () +) + +DEF_MACRO( + fLSBNEW, + predlog_read(thread,PNUM), + () +) + +DEF_MACRO( + fLSBNEW0, + predlog_read(thread,0), + () +) + +DEF_MACRO( + fLSBNEW1, + predlog_read(thread,1), + () +) + +DEF_MACRO( + fLSBOLDNOT, + (!fLSBOLD(VAL)), + () +) + +DEF_MACRO( + fLSBNEWNOT, + (!fLSBNEW(PNUM)), + () +) + +DEF_MACRO( + fLSBNEW0NOT, + (!fLSBNEW0), + () +) + +DEF_MACRO( + fLSBNEW1NOT, + (!fLSBNEW1), + () +) + +DEF_MACRO( + fNEWREG, + ({if (newvalue_missing(thread,RNUM) || + IS_CANCELLED(insn->new_value_producer_slot)) CANCEL; reglog_read(thread,RNUM);}), + (A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY) +) +// Store new with a missing newvalue or cancelled goes out as a zero byte store in V65 +// take advantage of the fact that reglog_read returns zero for not valid rnum +DEF_MACRO( + fNEWREG_ST, + ({if (newvalue_missing(thread,RNUM) || + IS_CANCELLED(insn->new_value_producer_slot)) { STORE_ZERO; RNUM = -1; }; reglog_read(thread,RNUM);}), + (A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY) +) + +DEF_MACRO( + fSATUVALN, + ({fSET_OVERFLOW(); ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}), + () +) + +DEF_MACRO( + fSATVALN, + ({fSET_OVERFLOW(); ((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}), + () +) + +DEF_MACRO( + fZXTN, /* macro name */ + ((VAL) & ((1LL<<(N))-1)), + /* attribs */ +) + +DEF_MACRO( + fSXTN, /* macro name */ + ((fZXTN(N,M,VAL) ^ (1LL<<((N)-1))) - (1LL<<((N)-1))), + /* attribs */ +) + +DEF_MACRO( + fSATN, + ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATVALN(N,VAL)), + () +) + +DEF_MACRO( + fADDSAT64, + { + size8u_t __a = fCAST8u(A); + size8u_t __b = fCAST8u(B); + size8u_t __sum = __a + __b; + size8u_t __xor = __a ^ __b; + const size8u_t __mask = 0x8000000000000000ULL; + if (__xor & __mask) { + /* Opposite signs, OK */ + DST = __sum; + } else if ((__a ^ __sum) & __mask) { + /* Signs mismatch */ + if (__sum & __mask) { + /* overflowed to negative, make max pos */ + DST=0x7FFFFFFFFFFFFFFFLL; fSET_OVERFLOW(); + } else { + /* overflowed to positive, make max neg */ + DST=0x8000000000000000LL; fSET_OVERFLOW(); + } + } else { + /* signs did not mismatch, OK */ + DST = __sum; + } + }, + () +) + +DEF_MACRO( + fSATUN, + ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATUVALN(N,VAL)), + () +) + +DEF_MACRO( + fSATH, + (fSATN(16,VAL)), + () +) + + +DEF_MACRO( + fSATUH, + (fSATUN(16,VAL)), + () +) + +DEF_MACRO( + fSATUB, + (fSATUN(8,VAL)), + () +) +DEF_MACRO( + fSATB, + (fSATN(8,VAL)), + () +) + + +/*************************************/ +/* immediate extension */ +/*************************************/ + +DEF_MACRO( + fIMMEXT, + (IMM = IMM), + (A_EXTENDABLE) +) + +DEF_MACRO( + fMUST_IMMEXT, + fIMMEXT(IMM), + (A_EXTENDABLE) +) + +DEF_MACRO( + fPCALIGN, + IMM=(IMM & ~PCALIGN_MASK), + (A_EXTENDABLE) +) + +/*************************************/ +/* Read and Write Implicit Regs */ +/*************************************/ + +DEF_MACRO( + fREAD_LR, /* read link register */ + (READ_RREG(REG_LR)), /* behavior */ + () +) + +DEF_MACRO( + fWRITE_LR, /* write lr */ + WRITE_RREG(REG_LR,A), /* behavior */ + (A_IMPLICIT_WRITES_LR) +) + +DEF_MACRO( + fWRITE_FP, /* write sp */ + WRITE_RREG(REG_FP,A), /* behavior */ + (A_IMPLICIT_WRITES_FP) +) + +DEF_MACRO( + fWRITE_SP, /* write sp */ + WRITE_RREG(REG_SP,A), /* behavior */ + (A_IMPLICIT_WRITES_SP) +) + +DEF_MACRO( + fREAD_SP, /* read stack pointer */ + (READ_RREG(REG_SP)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_LC0, /* read loop count */ + (READ_RREG(REG_LC0)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_LC1, /* read loop count */ + (READ_RREG(REG_LC1)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_SA0, /* read start addr */ + (READ_RREG(REG_SA0)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_SA1, /* read start addr */ + (READ_RREG(REG_SA1)), /* behavior */ + () +) + + +DEF_MACRO( + fREAD_FP, /* read frame pointer */ + (READ_RREG(REG_FP)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_GP, /* read global pointer */ + (insn->extension_valid ? 0 : READ_RREG(REG_GP)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_PC, /* read PC */ + (READ_RREG(REG_PC)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_NPC, /* read next PC */ + (thread->next_PC & (0xfffffffe)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_P0, /* read Predicate 0 */ + (READ_PREG(0)), /* behavior */ + () +) + +DEF_MACRO( + fREAD_P3, /* read Predicate 3 */ + (READ_PREG(3)), /* behavior */ + () +) + +DEF_MACRO( + fCHECK_PCALIGN, + if (((A) & PCALIGN_MASK)) { + register_error_exception(thread,PRECISE_CAUSE_PC_NOT_ALIGNED,thread->Regs[REG_BADVA0],thread->Regs[REG_BADVA1],GET_SSR_FIELD(SSR_BVS),GET_SSR_FIELD(SSR_V0),GET_SSR_FIELD(SSR_V1),0); + }, + () +) + +DEF_MACRO( + fWRITE_NPC, /* write next PC */ + if (!thread->branch_taken) { + if (A != thread->next_PC) { + thread->next_pkt_guess=thread->last_pkt->taken_ptr; + } + fCHECK_PCALIGN(A); + thread->branched = 1; thread->branch_taken = 1; thread->next_PC = A; \ + thread->branch_offset = insn->encoding_offset; thread->branch_opcode = insn->opcode; + } + , /* behavior */ + (A_COF) +) + +DEF_MACRO( + fBRANCH, + fWRITE_NPC(LOC); fCOF_CALLBACK(LOC,TYPE), + () +) + +DEF_MACRO( + fJUMPR, /* A jumpr has executed */ + {fBRANCH(TARGET,COF_TYPE_JUMPR);}, + (A_INDIRECT) +) + +DEF_MACRO( + fHINTJR, /* A hintjr instruction has executed */ + { }, +) + +DEF_MACRO( + fCALL, /* Do a call */ + if (!thread->branch_taken) {fBP_RAS_CALL(A); fWRITE_LR(fREAD_NPC()); fBRANCH(A,COF_TYPE_CALL);}, + (A_COF,A_IMPLICIT_WRITES_LR,A_CALL) +) + +DEF_MACRO( + fCALLR, /* Do a call Register */ + if (!thread->branch_taken) {fBP_RAS_CALL(A); fWRITE_LR(fREAD_NPC()); fBRANCH(A,COF_TYPE_CALLR);}, + (A_COF,A_IMPLICIT_WRITES_LR,A_CALL) +) + +DEF_MACRO( + fWRITE_LOOP_REGS0, /* write ln,sa,ea,lc */ + {WRITE_RREG(REG_LC0,COUNT); + WRITE_RREG(REG_SA0,START);}, + (A_IMPLICIT_WRITES_LC0,A_IMPLICIT_WRITES_SA0) +) + +DEF_MACRO( + fWRITE_LOOP_REGS1, /* write ln,sa,ea,lc */ + {WRITE_RREG(REG_LC1,COUNT); + WRITE_RREG(REG_SA1,START);}, + (A_IMPLICIT_WRITES_LC1,A_IMPLICIT_WRITES_SA1) +) + +DEF_MACRO( + fWRITE_LC0, + WRITE_RREG(REG_LC0,VAL), + (A_IMPLICIT_WRITES_LC0) +) + +DEF_MACRO( + fWRITE_LC1, + WRITE_RREG(REG_LC1,VAL), + (A_IMPLICIT_WRITES_LC1) +) + +DEF_MACRO( + fCARRY_FROM_ADD, + carry_from_add64(A,B,C), + /* NOTHING */ +) + +DEF_MACRO( + fSET_OVERFLOW, + SET_USR_FIELD(USR_OVF,1), + () +) + +DEF_MACRO( + fSET_LPCFG, + SET_USR_FIELD(USR_LPCFG,(VAL)), + () +) + + +DEF_MACRO( + fGET_LPCFG, + (GET_USR_FIELD(USR_LPCFG)), + () +) + + + +DEF_MACRO( + fWRITE_P0, /* write Predicate 0 */ + WRITE_PREG(0,VAL), /* behavior */ + (A_IMPLICIT_WRITES_P0) +) + +DEF_MACRO( + fWRITE_P1, /* write Predicate 0 */ + WRITE_PREG(1,VAL), /* behavior */ + (A_IMPLICIT_WRITES_P1) +) + +DEF_MACRO( + fWRITE_P2, /* write Predicate 0 */ + WRITE_PREG(2,VAL), /* behavior */ + (A_IMPLICIT_WRITES_P2) +) + +DEF_MACRO( + fWRITE_P3, /* write Predicate 0 */ + WRITE_PREG(3,VAL), /* behavior */ + (A_IMPLICIT_WRITES_P3) +) + +DEF_MACRO( + fPART1, /* write Predicate 0 */ + if (insn->part1) { WORK; return; }, /* behavior */ + /* optional attributes */ +) + + +/*************************************/ +/* Casting, Sign-Zero extension, etc */ +/*************************************/ + +DEF_MACRO( + fCAST4u, /* macro name */ + ((size4u_t)(A)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fCAST4s, /* macro name */ + ((size4s_t)(A)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fCAST8u, /* macro name */ + ((size8u_t)(A)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fCAST8s, /* macro name */ + ((size8s_t)(A)), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fCAST4_4s, /* macro name */ + ((size4s_t)(A)), + /* optional attributes */ +) + +DEF_MACRO( + fCAST4_4u, /* macro name */ + ((size4u_t)(A)), + /* optional attributes */ +) + + +DEF_MACRO( + fCAST4_8s, /* macro name */ + ((size8s_t)((size4s_t)(A))), + /* optional attributes */ +) + +DEF_MACRO( + fCAST4_8u, /* macro name */ + ((size8u_t)((size4u_t)(A))), + /* optional attributes */ +) + +DEF_MACRO( + fCAST8_8s, /* macro name */ + ((size8s_t)(A)), + /* optional attributes */ +) + +DEF_MACRO( + fCAST8_8u, /* macro name */ + ((size8u_t)(A)), + /* optional attributes */ +) + +DEF_MACRO( + fCAST2_8s, /* macro name */ + ((size8s_t)((size2s_t)(A))), + /* optional attributes */ +) +DEF_MACRO( + fCAST2_8u, /* macro name */ + ((size8u_t)((size2u_t)(A))), + /* optional attributes */ +) + +DEF_MACRO( + fZE8_16, /* zero-extend 8 to 16 */ + ((size2s_t)((size1u_t)(A))), + /* optional attributes */ +) +DEF_MACRO( + fSE8_16, /* sign-extend 8 to 16 */ + ((size2s_t)((size1s_t)(A))), + /* optional attributes */ +) + + +DEF_MACRO( + fSE16_32, /* sign-extend 16 to 32 */ + ((size4s_t)((size2s_t)(A))), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fZE16_32, /* zero-extend 16 to 32 */ + ((size4u_t)((size2u_t)(A))), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fSE32_64, + ( (size8s_t)((size4s_t)(A)) ), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fZE32_64, + ( (size8u_t)((size4u_t)(A)) ), /* behavior */ + /* optional attributes */ +) + +DEF_MACRO( + fSE8_32, /* sign-extend 8 to 32 */ + ((size4s_t)((size1s_t)(A))), + /* optional attributes */ +) + +DEF_MACRO( + fZE8_32, /* zero-extend 8 to 32 */ + ((size4s_t)((size1u_t)(A))), + /* optional attributes */ +) + +/*************************************/ +/* DSP arithmetic support */ +/************************************/ +DEF_MACRO( + fMPY8UU, /* multiply half integer */ + (int)(fZE8_16(A)*fZE8_16(B)), /* behavior */ + () +) +DEF_MACRO( + fMPY8US, /* multiply half integer */ + (int)(fZE8_16(A)*fSE8_16(B)), /* behavior */ + () +) +DEF_MACRO( + fMPY8SU, /* multiply half integer */ + (int)(fSE8_16(A)*fZE8_16(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY8SS, /* multiply half integer */ + (int)((short)(A)*(short)(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY16SS, /* multiply half integer */ + fSE32_64(fSE16_32(A)*fSE16_32(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY16UU, /* multiply unsigned half integer */ + fZE32_64(fZE16_32(A)*fZE16_32(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY16SU, /* multiply half integer */ + fSE32_64(fSE16_32(A)*fZE16_32(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY16US, /* multiply half integer */ + fMPY16SU(B,A), + () +) + +DEF_MACRO( + fMPY32SS, /* multiply half integer */ + (fSE32_64(A)*fSE32_64(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY32UU, /* multiply half integer */ + (fZE32_64(A)*fZE32_64(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY32SU, /* multiply half integer */ + (fSE32_64(A)*fZE32_64(B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY3216SS, /* multiply mixed precision */ + (fSE32_64(A)*fSXTN(16,64,B)), /* behavior */ + () +) + +DEF_MACRO( + fMPY3216SU, /* multiply mixed precision */ + (fSE32_64(A)*fZXTN(16,64,B)), /* behavior */ + () +) + +DEF_MACRO( + fROUND, /* optional rounding */ + (A+0x8000), + /* optional attributes */ +) + +DEF_MACRO( + fCLIP, /* optional rounding */ + { size4s_t maxv = (1< 0) && ((A) == 0)) ? + fSATVALN(32,(ORIG_REG)) : + fSAT(A))), + () +) + +DEF_MACRO( + fPASS, + A, +) + +DEF_MACRO( + fRND, /* saturating to 32-bits*/ + (((A)+1)>>1), +) + + +DEF_MACRO( + fBIDIR_SHIFTL, + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT))-1)) >>1) : (fCAST##REGSTYPE(SRC) << (SHAMT))), + () +) + +DEF_MACRO( + fBIDIR_ASHIFTL, + fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##s), + () +) + +DEF_MACRO( + fBIDIR_LSHIFTL, + fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##u), + () +) + +DEF_MACRO( + fBIDIR_ASHIFTL_SAT, + (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT))-1)) >>1) : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT),(SRC))), + () +) + + +DEF_MACRO( + fBIDIR_SHIFTR, + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT))-1)) << 1) : (fCAST##REGSTYPE(SRC) >> (SHAMT))), + () +) + +DEF_MACRO( + fBIDIR_ASHIFTR, + fBIDIR_SHIFTR(SRC,SHAMT,REGSTYPE##s), + () +) + +DEF_MACRO( + fBIDIR_LSHIFTR, + fBIDIR_SHIFTR(SRC,SHAMT,REGSTYPE##u), + () +) + +DEF_MACRO( + fBIDIR_ASHIFTR_SAT, + (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) << ((-(SHAMT))-1)) << 1,(SRC)) : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))), + () +) + +DEF_MACRO( + fASHIFTR, + (fCAST##REGSTYPE##s(SRC) >> (SHAMT)), + /* */ +) + +DEF_MACRO( + fLSHIFTR, + (((SHAMT) >= 64)?0:(fCAST##REGSTYPE##u(SRC) >> (SHAMT))), + /* */ +) + +DEF_MACRO( + fROTL, + (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ + ((fCAST##REGSTYPE##u(SRC) >> ((sizeof(SRC)*8)-(SHAMT)))))), + /* */ +) + +DEF_MACRO( + fROTR, + (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ + ((fCAST##REGSTYPE##u(SRC) << ((sizeof(SRC)*8)-(SHAMT)))))), + /* */ +) + +DEF_MACRO( + fASHIFTL, + (((SHAMT) >= 64)?0:(fCAST##REGSTYPE##s(SRC) << (SHAMT))), + /* */ +) + +/*************************************/ +/* Floating-Point Support */ +/************************************/ + +DEF_MACRO( + fFLOAT, /* name */ + ({ union { float f; size4u_t i; } _fipun; _fipun.i = (A); _fipun.f; }), /* behavior */ + (A_FPOP) +) + +DEF_MACRO( + fUNFLOAT, /* multiply half integer */ + ({ union { float f; size4u_t i; } _fipun; _fipun.f = (A); isnan(_fipun.f) ? 0xFFFFFFFFU : _fipun.i; }), /* behavior */ + (A_FPOP) +) + +DEF_MACRO( + fSFNANVAL, + 0xffffffff, + () +) + +DEF_MACRO( + fSFINFVAL, + (((A) & 0x80000000) | 0x7f800000), + () +) + +DEF_MACRO( + fSFONEVAL, + (((A) & 0x80000000) | fUNFLOAT(1.0)), + () +) + +DEF_MACRO( + fCHECKSFNAN, + do { + if (isnan(fFLOAT(A))) { + if ((fGETBIT(22,A)) == 0) fRAISEFLAGS(FE_INVALID); + DST = fSFNANVAL(); + } + } while (0), + () +) + +DEF_MACRO( + fCHECKSFNAN3, + do { + fCHECKSFNAN(DST,A); + fCHECKSFNAN(DST,B); + fCHECKSFNAN(DST,C); + } while (0), + () +) + +DEF_MACRO( + fSF_BIAS, + 127, + () +) + +DEF_MACRO( + fSF_MANTBITS, + 23, + () +) + +DEF_MACRO( + fSF_MUL_POW2, + (fUNFLOAT(fFLOAT(A) * fFLOAT((fSF_BIAS() + (B)) << fSF_MANTBITS()))), + () +) + +DEF_MACRO( + fSF_GETEXP, + (((A) >> fSF_MANTBITS()) & 0xff), + () +) + +DEF_MACRO( + fSF_MAXEXP, + (254), + () +) + +DEF_MACRO( + fSF_RECIP_COMMON, + arch_sf_recip_common(&N,&D,&O,&A), + (A_FPOP) +) + +DEF_MACRO( + fSF_INVSQRT_COMMON, + arch_sf_invsqrt_common(&N,&O,&A), + (A_FPOP) +) + +DEF_MACRO( + fFMAFX, + internal_fmafx(A,B,C,fSXTN(8,64,ADJ)), + () +) + +DEF_MACRO( + fFMAF, + internal_fmafx(A,B,C,0), + () +) + +DEF_MACRO( + fSFMPY, + internal_mpyf(A,B), + () +) + +DEF_MACRO( + fMAKESF, + ((((SIGN) & 1) << 31) | (((EXP) & 0xff) << fSF_MANTBITS()) | + ((MANT) & ((1<= 512), + () +) + +DEF_MACRO( + fDF_MANTBITS, + 52, + () +) + +DEF_MACRO( + fDF_GETEXP, + (((A) >> fDF_MANTBITS()) & 0x7ff), + () +) + +DEF_MACRO( + fFMA, + internal_fma(A,B,C), + /* nothing */ +) + +DEF_MACRO( + fDF_MPY_HH, + internal_mpyhh(A,B,ACC), + /* nothing */ +) + +DEF_MACRO( + fFPOP_START, + arch_fpop_start(thread), + /* nothing */ +) + +DEF_MACRO( + fFPOP_END, + arch_fpop_end(thread), + /* nothing */ +) + +DEF_MACRO( + fFPSETROUND_NEAREST, + fesetround(FE_TONEAREST), + /* nothing */ +) + +DEF_MACRO( + fFPSETROUND_CHOP, + fesetround(FE_TOWARDZERO), + /* nothing */ +) + +DEF_MACRO( + fFPCANCELFLAGS, + feclearexcept(FE_ALL_EXCEPT), + /* nothing */ +) + +DEF_MACRO( + fISINFPROD, + ((isinf(A) && isinf(B)) || + (isinf(A) && isfinite(B) && ((B) != 0.0)) || + (isinf(B) && isfinite(A) && ((A) != 0.0))), + /* nothing */ +) + +DEF_MACRO( + fISZEROPROD, + ((((A) == 0.0) && isfinite(B)) || (((B) == 0.0) && isfinite(A))), + /* nothing */ +) + +DEF_MACRO( + fRAISEFLAGS, + arch_raise_fpflag(A), + /* NOTHING */ +) + +DEF_MACRO( + fDF_MAX, + (((A)==(B)) + ? fDOUBLE(fUNDOUBLE(A) & fUNDOUBLE(B)) + : fmax(A,B)), + (A_FPOP) +) + +DEF_MACRO( + fDF_MIN, + (((A)==(B)) + ? fDOUBLE(fUNDOUBLE(A) | fUNDOUBLE(B)) + : fmin(A,B)), + (A_FPOP) +) + +DEF_MACRO( + fSF_MAX, + (((A)==(B)) + ? fFLOAT(fUNFLOAT(A) & fUNFLOAT(B)) + : fmaxf(A,B)), + (A_FPOP) +) + +DEF_MACRO( + fSF_MIN, + (((A)==(B)) + ? fFLOAT(fUNFLOAT(A) | fUNFLOAT(B)) + : fminf(A,B)), + (A_FPOP) +) + +/*************************************/ +/* Load/Store support */ +/*************************************/ + +DEF_MACRO(fLOAD, + { DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(thread,EA,insn); }, + (A_LOAD,A_MEMLIKE) +) + +DEF_MACRO(fMEMOP, + { memop##SIZE##_##FNTYPE(thread,EA,VALUE); }, + (A_LOAD,A_STORE,A_MEMLIKE) +) + +DEF_MACRO(fGET_FRAMEKEY, + READ_RREG(REG_FRAMEKEY), + () +) + +DEF_MACRO(fFRAME_SCRAMBLE, + ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)), + /* ATTRIBS */ +) + +DEF_MACRO(fFRAME_UNSCRAMBLE, + fFRAME_SCRAMBLE(VAL), + /* ATTRIBS */ +) + +DEF_MACRO(fFRAMECHECK, + sys_check_framelimit(thread,ADDR,EA), + () +) + +DEF_MACRO(fLOAD_LOCKED, + { DST = (size##SIZE##SIGN##_t)mem_load_locked(thread,EA,SIZE,insn); + }, + (A_LOAD,A_MEMLIKE) +) + +DEF_MACRO(fSTORE, + { MEM_STORE##SIZE(thread,EA,SRC,insn); }, + (A_STORE,A_MEMLIKE) +) + + +DEF_MACRO(fSTORE_LOCKED, + { PRED = (mem_store_conditional(thread,EA,SRC,SIZE,insn) ? 0xff : 0); }, + (A_STORE,A_MEMLIKE) +) + +/*************************************/ +/* Functions to help with bytes */ +/*************************************/ + +DEF_MACRO(fGETBYTE, + ((size1s_t)((SRC>>((N)*8))&0xff)), + /* nothing */ +) + +DEF_MACRO(fGETUBYTE, + ((size1u_t)((SRC>>((N)*8))&0xff)), + /* nothing */ +) + +DEF_MACRO(fSETBYTE, + { + DST = (DST & ~(0x0ffLL<<((N)*8))) | (((size8u_t)((VAL) & 0x0ffLL)) << ((N)*8)); + }, + /* nothing */ +) + +DEF_MACRO(fGETHALF, + ((size2s_t)((SRC>>((N)*16))&0xffff)), + /* nothing */ +) + +DEF_MACRO(fGETUHALF, + ((size2u_t)((SRC>>((N)*16))&0xffff)), + /* nothing */ +) + +DEF_MACRO(fSETHALF, + { + DST = (DST & ~(0x0ffffLL<<((N)*16))) | (((size8u_t)((VAL) & 0x0ffff)) << ((N)*16)); + }, + /* nothing */ +) + + + +DEF_MACRO(fGETWORD, + ((size8s_t)((size4s_t)((SRC>>((N)*32))&0x0ffffffffLL))), + /* nothing */ +) + +DEF_MACRO(fGETUWORD, + ((size8u_t)((size4u_t)((SRC>>((N)*32))&0x0ffffffffLL))), + /* nothing */ +) + +DEF_MACRO(fSETWORD, + { + DST = (DST & ~(0x0ffffffffLL<<((N)*32))) | (((VAL) & 0x0ffffffffLL) << ((N)*32)); + }, + /* nothing */ +) + +DEF_MACRO(fSETBIT, + { + DST = (DST & ~(1ULL<<(N))) | (((size8u_t)(VAL))<<(N)); + }, + /* nothing */ +) + +DEF_MACRO(fGETBIT, + (((SRC)>>N)&1), + /* nothing */ +) + + +DEF_MACRO(fSETBITS, + do { + int j; + for (j=LO;j<=HI;j++) { + fSETBIT(j,DST,VAL); + } + } while (0), + /* nothing */ +) + +/*************************************/ +/* Used for parity, etc........ */ +/*************************************/ +DEF_MACRO(fCOUNTONES_4, + count_ones_4(VAL), + /* nothing */ +) + +DEF_MACRO(fCOUNTONES_8, + count_ones_8(VAL), + /* nothing */ +) + +DEF_MACRO(fBREV_8, + reverse_bits_8(VAL), + /* nothing */ +) + +DEF_MACRO(fBREV_4, + reverse_bits_4(VAL), + /* nothing */ +) + +DEF_MACRO(fCL1_8, + count_leading_ones_8(VAL), + /* nothing */ +) + +DEF_MACRO(fCL1_4, + count_leading_ones_4(VAL), + /* nothing */ +) + +DEF_MACRO(fINTERLEAVE, + interleave(ODD,EVEN), + /* nothing */ +) + +DEF_MACRO(fDEINTERLEAVE, + deinterleave(MIXED), + /* nothing */ +) + +DEF_MACRO(fHIDE, + A, + () +) + +DEF_MACRO(fCONSTLL, + A##LL, +) + +/* Do the things in the parens, but don't print the parens. */ +DEF_MACRO(fECHO, + (A), + /* nothing */ +) + + +/********************************************/ +/* OS interface and stop/wait */ +/********************************************/ + +DEF_MACRO(fTRAP, + warn("Trap NPC=%x ",fREAD_NPC()); + warn("Trap exception, PCYCLE=%lld TYPE=%d NPC=%x IMM=0x%x",thread->processor_ptr->pstats[pcycles],TRAPTYPE,fREAD_NPC(),IMM); + register_trap_exception(thread,fREAD_NPC(),TRAPTYPE,IMM);, + () +) + +DEF_MACRO(fALIGN_REG_FIELD_VALUE, + ((VAL)<Regs[REG_##REG], + reg_field_info[FIELD].width, + reg_field_info[FIELD].offset), + /* ATTRIBS */ +) + +DEF_MACRO(fGET_FIELD, + fEXTRACTU_BITS(VAL, + reg_field_info[FIELD].width, + reg_field_info[FIELD].offset), + /* ATTRIBS */ +) + +DEF_MACRO(fSET_FIELD, + fINSERT_BITS(VAL, + reg_field_info[FIELD].width, + reg_field_info[FIELD].offset, + (NEWVAL)), + /* ATTRIBS */ +) + +/********************************************/ +/* Cache Management */ +/********************************************/ + +DEF_MACRO(fBARRIER, + { + sys_barrier(thread, insn->slot); + }, + () +) + +DEF_MACRO(fSYNCH, + { + sys_sync(thread, insn->slot); + }, + () +) + +DEF_MACRO(fISYNC, + { + sys_isync(thread, insn->slot); + }, + () +) + + +DEF_MACRO(fDCFETCH, + sys_dcfetch(thread, (REG), insn->slot), + (A_MEMLIKE) +) + +DEF_MACRO(fICINVA, + { + arch_internal_flush(thread->processor_ptr, 0, 0xffffffff); + sys_icinva(thread, (REG),insn->slot); + }, + (A_ICINVA) +) + +DEF_MACRO(fL2FETCH, + sys_l2fetch(thread, ADDR,HEIGHT,WIDTH,STRIDE,FLAGS, insn->slot), + (A_MEMLIKE,A_L2FETCH) +) + +DEF_MACRO(fDCCLEANA, + sys_dccleana(thread, (REG)), + (A_MEMLIKE) +) + +DEF_MACRO(fDCCLEANINVA, + sys_dccleaninva(thread, (REG), insn->slot), + (A_MEMLIKE,A_DCCLEANINVA) +) + +DEF_MACRO(fDCZEROA, + sys_dczeroa(thread, (REG)), + (A_MEMLIKE) +) + +DEF_MACRO(fCHECKFORPRIV, + {sys_check_privs(thread); if (EXCEPTION_DETECTED) return; }, + () +) + +DEF_MACRO(fCHECKFORGUEST, + {sys_check_guest(thread); if (EXCEPTION_DETECTED) return; }, + () +) + +DEF_MACRO(fBRANCH_SPECULATE_STALL, + { +sys_speculate_branch_stall(thread, insn->slot, JUMP_COND(JUMP_PRED_SET), + SPEC_DIR, + DOTNEWVAL, + HINTBITNUM, + STRBITNUM, + 0, + thread->last_pkt->pkt_has_dual_jump, + insn->is_2nd_jump, + (thread->fetch_access.vaddr + insn->encoding_offset*4)); + }, + () +) + From patchwork Tue Aug 18 15:50:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB547C433E1 for ; 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18 Aug 2020 08:50:57 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 85CB1848; Tue, 18 Aug 2020 10:50:57 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 19/34] Hexagon (target/hexagon/imported) arch import - instruction encoding Date: Tue, 18 Aug 2020 10:50:32 -0500 Message-Id: <1597765847-16637-20-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Imported from the Hexagon architecture library Instruction encoding bit patterns for every instruction Signed-off-by: Taylor Simpson --- target/hexagon/imported/encode.def | 125 ++ target/hexagon/imported/encode_pp.def | 2110 ++++++++++++++++++++++++++++ target/hexagon/imported/encode_subinsn.def | 150 ++ 3 files changed, 2385 insertions(+) create mode 100644 target/hexagon/imported/encode.def create mode 100644 target/hexagon/imported/encode_pp.def create mode 100644 target/hexagon/imported/encode_subinsn.def diff --git a/target/hexagon/imported/encode.def b/target/hexagon/imported/encode.def new file mode 100644 index 0000000..ae23301 --- /dev/null +++ b/target/hexagon/imported/encode.def @@ -0,0 +1,125 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * This just includes all encoding files + */ + +#ifndef DEF_FIELD32 +#define __SELF_DEF_FIELD32 +#define DEF_FIELD32(...) /* nothing */ +#endif + +#ifndef DEF_CLASS32 +#define __SELF_DEF_CLASS32 +#define DEF_CLASS32(...) /* nothing */ +#endif + +#ifndef DEF_ANTICLASS32 +#define __SELF_DEF_ANTICLASS32 +#define DEF_ANTICLASS32(...) /* nothing */ +#endif + +#ifndef LEGACY_DEF_ENC32 +#define __SELF_DEF_LEGACY_DEF_ENC32 +#define LEGACY_DEF_ENC32(...) /* nothing */ +#endif + +#ifndef DEF_FIELDROW_DESC32 +#define __SELF_DEF_FIELDROW_DESC32 +#define DEF_FIELDROW_DESC32(...) /* nothing */ +#endif + +#ifndef DEF_ENC32 +#define __SELF_DEF_ENC32 +#define DEF_ENC32(...) /* nothing */ +#endif + +#ifndef DEF_PACKED32 +#define __SELF_DEF_PACKED32 +#define DEF_PACKED32(...) /* nothing */ +#endif + +#ifndef DEF_ENC_SUBINSN +#define __SELF_DEF_ENC_SUBINSN +#define DEF_ENC_SUBINSN(...) /* nothing */ +#endif + +#ifndef DEF_EXT_ENC +#define __SELF_DEF_EXT_ENC +#define DEF_EXT_ENC(...) /* nothing */ +#endif + +#ifndef DEF_EXT_SPACE +#define __SELF_DEF_EXT_SPACE +#define DEF_EXT_SPACE(...) /* nothing */ +#endif + +#include "encode_pp.def" +#include "encode_subinsn.def" + +#ifdef __SELF_DEF_FIELD32 +#undef __SELF_DEF_FIELD32 +#undef DEF_FIELD32 +#endif + +#ifdef __SELF_DEF_CLASS32 +#undef __SELF_DEF_CLASS32 +#undef DEF_CLASS32 +#endif + +#ifdef __SELF_DEF_ANTICLASS32 +#undef __SELF_DEF_ANTICLASS32 +#undef DEF_ANTICLASS32 +#endif + +#ifdef __SELF_DEF_LEGACY_DEF_ENC32 +#undef __SELF_DEF_LEGACY_DEF_ENC32 +#undef LEGACY_DEF_ENC32 +#endif + +#ifdef __SELF_DEF_FIELDROW_DESC32 +#undef __SELF_DEF_FIELDROW_DESC32 +#undef DEF_FIELDROW_DESC32 +#endif + +#ifdef __SELF_DEF_ENC32 +#undef __SELF_DEF_ENC32 +#undef DEF_ENC32 +#endif + +#ifdef __SELF_DEF_EXT_SPACE +#undef __SELF_DEF_EXT_SPACE +#undef DEF_EXT_SPACE +#endif + + +#ifdef __SELF_DEF_PACKED32 +#undef __SELF_DEF_PACKED32 +#undef DEF_PACKED32 +#endif + +#ifdef __SELF_DEF_ENC_SUBINSN +#undef __SELF_DEF_ENC_SUBINSN +#undef DEF_ENC_SUBINSN +#endif + +#ifdef __SELF_DEF_EXT_ENC +#undef __SELF_DEF_EXT_ENC +#undef DEF_EXT_ENC +#endif + diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def new file mode 100644 index 0000000..d3ff2c3 --- /dev/null +++ b/target/hexagon/imported/encode_pp.def @@ -0,0 +1,2110 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Encodings for 32 bit instructions + * + */ + + + + +DEF_CLASS32("---- ---- -------- PP------ --------",ALL_PP) +DEF_FIELD32("---- ---- -------- !!------ --------",Parse,"Packet/Loop parse bits") +DEF_FIELD32("!!!! ---- -------- PP------ --------",ICLASS,"Instruction Class") + +#define ICLASS_EXTENDER "0000" +#define ICLASS_CJ "0001" +#define ICLASS_NCJ "0010" +#define ICLASS_V4LDST "0011" +#define ICLASS_V2LDST "0100" +#define ICLASS_J "0101" +#define ICLASS_CR "0110" +#define ICLASS_ALU2op "0111" +#define ICLASS_S2op "1000" +#define ICLASS_LD "1001" +#define ICLASS_ST "1010" +#define ICLASS_ADDI "1011" +#define ICLASS_S3op "1100" +#define ICLASS_ALU64 "1101" +#define ICLASS_M "1110" +#define ICLASS_ALU3op "1111" + + + +/*******************************/ +/* */ +/* */ +/* V4 Immediate Payload */ +/* */ +/* */ +/*******************************/ + +DEF_CLASS32(ICLASS_EXTENDER" ---- -------- PP------ --------",EXTENDER) +DEF_ENC32(A4_ext, ICLASS_EXTENDER "iiii iiiiiiii PPiiiiii iiiiiiii") + + + +/*******************************/ +/* */ +/* */ +/* V2 PREDICATED LD/ST */ +/* */ +/* */ +/*******************************/ + +DEF_CLASS32(ICLASS_V2LDST" ---- -------- PP------ --------",V2LDST) +DEF_CLASS32(ICLASS_V2LDST" ---1 -------- PP------ --------",V2LD) +DEF_CLASS32(ICLASS_V2LDST" ---0 -------- PP------ --------",V2ST) +DEF_CLASS32(ICLASS_V2LDST" 0--1 -------- PP------ --------",PLD) +DEF_CLASS32(ICLASS_V2LDST" 0--0 -------- PP------ --------",PST) +DEF_CLASS32(ICLASS_V2LDST" 1--1 -------- PP------ --------",GPLD) +DEF_CLASS32(ICLASS_V2LDST" 1--0 -------- PP------ --------",GPST) + +DEF_FIELD32(ICLASS_V2LDST" 0!-- -------- PP------ --------",PMEM_Sense,"Sense") +DEF_FIELD32(ICLASS_V2LDST" 0-!- -------- PP------ --------",PMEM_PredNew,"PredNew") +DEF_FIELD32(ICLASS_V2LDST" ---1 !!------ PP------ --------",PMEML_Type,"Type") +DEF_FIELD32(ICLASS_V2LDST" ---1 --!----- PP------ --------",PMEML_UN,"Unsigned") +DEF_FIELD32(ICLASS_V2LDST" ---0 !!!----- PP------ --------",PMEMS_Type,"Type") + +#define STD_PLD_IOENC(TAG,OPC) \ +DEF_ENC32(L2_pload##TAG##t_io, ICLASS_V2LDST" 0001 "OPC" sssss PP0ttiii iiiddddd")\ +DEF_ENC32(L2_pload##TAG##f_io, ICLASS_V2LDST" 0101 "OPC" sssss PP0ttiii iiiddddd")\ +DEF_ENC32(L2_pload##TAG##tnew_io,ICLASS_V2LDST" 0011 "OPC" sssss PP0ttiii iiiddddd")\ +DEF_ENC32(L2_pload##TAG##fnew_io,ICLASS_V2LDST" 0111 "OPC" sssss PP0ttiii iiiddddd") + +STD_PLD_IOENC(rb, "000") +STD_PLD_IOENC(rub, "001") +STD_PLD_IOENC(rh, "010") +STD_PLD_IOENC(ruh, "011") +STD_PLD_IOENC(ri, "100") +STD_PLD_IOENC(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ + + + +#define STD_PST_IOENC(TAG,OPC,SRC) \ +DEF_ENC32(S2_pstore##TAG##t_io, ICLASS_V2LDST" 0000 "OPC" sssss PPi"SRC" iiiii0vv")\ +DEF_ENC32(S2_pstore##TAG##f_io, ICLASS_V2LDST" 0100 "OPC" sssss PPi"SRC" iiiii0vv")\ +DEF_ENC32(S4_pstore##TAG##tnew_io,ICLASS_V2LDST" 0010 "OPC" sssss PPi"SRC" iiiii0vv")\ +DEF_ENC32(S4_pstore##TAG##fnew_io,ICLASS_V2LDST" 0110 "OPC" sssss PPi"SRC" iiiii0vv") + +STD_PST_IOENC(rb, "000","ttttt") +STD_PST_IOENC(rh, "010","ttttt") +STD_PST_IOENC(rf, "011","ttttt") +STD_PST_IOENC(ri, "100","ttttt") +STD_PST_IOENC(rd, "110","ttttt") +STD_PST_IOENC(rbnew, "101","00ttt") +STD_PST_IOENC(rhnew, "101","01ttt") +STD_PST_IOENC(rinew, "101","10ttt") + + + + + +/*******************************/ +/* */ +/* */ +/* V2 GP-RELATIVE LD/ST */ +/* */ +/* */ +/*******************************/ +#define STD_LD_GP(TAG,OPC) \ +DEF_ENC32(L2_load##TAG##gp, ICLASS_V2LDST" 1ii1 "OPC" iiiii PPiiiiii iiiddddd") + +STD_LD_GP(rb, "000") +STD_LD_GP(rub, "001") +STD_LD_GP(rh, "010") +STD_LD_GP(ruh, "011") +STD_LD_GP(ri, "100") +STD_LD_GP(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ + +#define STD_ST_GP(TAG,OPC,SRC) \ +DEF_ENC32(S2_store##TAG##gp, ICLASS_V2LDST" 1ii0 "OPC" iiiii PPi"SRC" iiiiiiii") + +STD_ST_GP(rb, "000","ttttt") +STD_ST_GP(rh, "010","ttttt") +STD_ST_GP(rf, "011","ttttt") +STD_ST_GP(ri, "100","ttttt") +STD_ST_GP(rd, "110","ttttt") +STD_ST_GP(rbnew,"101","00ttt") +STD_ST_GP(rhnew,"101","01ttt") +STD_ST_GP(rinew,"101","10ttt") + + + + + +/*******************************/ +/* */ +/* */ +/* V4LDST */ +/* */ +/* */ +/*******************************/ + + +DEF_CLASS32(ICLASS_V4LDST" ---- -------- PP------ --------",V4LDST) +DEF_CLASS32(ICLASS_V4LDST" 0--- -------- PP------ --------",Pred_RplusR) +DEF_CLASS32(ICLASS_V4LDST" 100- -------- PP------ --------",Pred_StoreImmed) +DEF_CLASS32(ICLASS_V4LDST" 101- -------- PP------ --------",RplusR) +DEF_CLASS32(ICLASS_V4LDST" 110- -------- PP------ --------",StoreImmed) +DEF_CLASS32(ICLASS_V4LDST" 111- -------- PP------ --------",MemOp) + + + + +/*******************************/ +/* Pred (R+R) */ +/*******************************/ + +#define STD_PLD_RRENC(TAG,OPC) \ +DEF_ENC32(L4_pload##TAG##t_rr, ICLASS_V4LDST" 00 00 "OPC" sssss PPittttt ivvddddd")\ +DEF_ENC32(L4_pload##TAG##f_rr, ICLASS_V4LDST" 00 01 "OPC" sssss PPittttt ivvddddd")\ +DEF_ENC32(L4_pload##TAG##tnew_rr,ICLASS_V4LDST" 00 10 "OPC" sssss PPittttt ivvddddd")\ +DEF_ENC32(L4_pload##TAG##fnew_rr,ICLASS_V4LDST" 00 11 "OPC" sssss PPittttt ivvddddd") + +STD_PLD_RRENC(rb, "000") +STD_PLD_RRENC(rub, "001") +STD_PLD_RRENC(rh, "010") +STD_PLD_RRENC(ruh, "011") +STD_PLD_RRENC(ri, "100") +STD_PLD_RRENC(rd, "110") + +#define STD_PST_RRENC(TAG,OPC,SRC) \ +DEF_ENC32(S4_pstore##TAG##t_rr, ICLASS_V4LDST" 01 00 "OPC" sssss PPiuuuuu ivv"SRC)\ +DEF_ENC32(S4_pstore##TAG##f_rr, ICLASS_V4LDST" 01 01 "OPC" sssss PPiuuuuu ivv"SRC)\ +DEF_ENC32(S4_pstore##TAG##tnew_rr,ICLASS_V4LDST" 01 10 "OPC" sssss PPiuuuuu ivv"SRC)\ +DEF_ENC32(S4_pstore##TAG##fnew_rr,ICLASS_V4LDST" 01 11 "OPC" sssss PPiuuuuu ivv"SRC) + +STD_PST_RRENC(rb, "000","ttttt") +STD_PST_RRENC(rh, "010","ttttt") +STD_PST_RRENC(rf, "011","ttttt") +STD_PST_RRENC(ri, "100","ttttt") +STD_PST_RRENC(rd, "110","ttttt") +STD_PST_RRENC(rbnew, "101","00ttt") +STD_PST_RRENC(rhnew, "101","01ttt") +STD_PST_RRENC(rinew, "101","10ttt") + + + +/*******************************/ +/* Pred Store immediates */ +/*******************************/ + +#define V4_PSTI(TAG,OPC) \ +DEF_ENC32(S4_storei##TAG##t_io, ICLASS_V4LDST" 100 00 "OPC" sssss PPIiiiii ivvIIIII")\ +DEF_ENC32(S4_storei##TAG##f_io, ICLASS_V4LDST" 100 01 "OPC" sssss PPIiiiii ivvIIIII")\ +DEF_ENC32(S4_storei##TAG##tnew_io, ICLASS_V4LDST" 100 10 "OPC" sssss PPIiiiii ivvIIIII")\ +DEF_ENC32(S4_storei##TAG##fnew_io, ICLASS_V4LDST" 100 11 "OPC" sssss PPIiiiii ivvIIIII") + +V4_PSTI(rb, "00") +V4_PSTI(rh, "01") +V4_PSTI(ri, "10") + + + +/*******************************/ +/* (R+R) */ +/*******************************/ + +#define STD_LD_RRENC(TAG,OPC) \ +DEF_ENC32(L4_load##TAG##_rr, ICLASS_V4LDST" 1010 "OPC" sssss PPittttt i--ddddd") + +STD_LD_RRENC(rb, "000") +STD_LD_RRENC(rub, "001") +STD_LD_RRENC(rh, "010") +STD_LD_RRENC(ruh, "011") +STD_LD_RRENC(ri, "100") +STD_LD_RRENC(rd, "110") + +#define STD_ST_RRENC(TAG,OPC,SRC) \ +DEF_ENC32(S4_store##TAG##_rr, ICLASS_V4LDST" 1011 "OPC" sssss PPiuuuuu i--"SRC) + +STD_ST_RRENC(rb, "000","ttttt") +STD_ST_RRENC(rh, "010","ttttt") +STD_ST_RRENC(rf, "011","ttttt") +STD_ST_RRENC(ri, "100","ttttt") +STD_ST_RRENC(rd, "110","ttttt") +STD_ST_RRENC(rbnew, "101","00ttt") +STD_ST_RRENC(rhnew, "101","01ttt") +STD_ST_RRENC(rinew, "101","10ttt") + + + + +/*******************************/ +/* Store immediates */ +/*******************************/ + +#define V4_STI(TAG,OPC) \ +DEF_ENC32(S4_storei##TAG##_io, ICLASS_V4LDST" 110 -- "OPC" sssss PPIiiiii iIIIIIII") + + +V4_STI(rb, "00") +V4_STI(rh, "01") +V4_STI(ri, "10") + + +/*******************************/ +/* Memops */ +/*******************************/ + +#define MEMOPENC(TAG,OPC) \ +DEF_ENC32(L4_add_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i00ttttt")\ +DEF_ENC32(L4_sub_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i01ttttt")\ +DEF_ENC32(L4_and_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i10ttttt")\ +DEF_ENC32(L4_or_##TAG##_io, ICLASS_V4LDST" 111 0- " OPC "sssss PP0iiiii i11ttttt")\ +\ +DEF_ENC32(L4_iadd_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i00IIIII")\ +DEF_ENC32(L4_isub_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i01IIIII")\ +DEF_ENC32(L4_iand_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i10IIIII")\ +DEF_ENC32(L4_ior_##TAG##_io, ICLASS_V4LDST" 111 1- " OPC "sssss PP0iiiii i11IIIII") + + + +MEMOPENC(memopw,"10") +MEMOPENC(memoph,"01") +MEMOPENC(memopb,"00") + + + + +/*******************************/ +/* */ +/* */ +/* LOAD */ +/* */ +/* */ +/*******************************/ +DEF_CLASS32(ICLASS_LD" ---- -------- PP------ --------",LD) + + +DEF_CLASS32(ICLASS_LD" 0--- -------- PP------ --------",LD_ADDR_ROFFSET) +DEF_CLASS32(ICLASS_LD" 101- -------- PP00---- --------",LD_ADDR_POST_IMMED) +DEF_CLASS32(ICLASS_LD" 101- -------- PP01---- --------",LD_ADDR_ABS_UPDATE_V4) +DEF_CLASS32(ICLASS_LD" 101- -------- PP1----- --------",LD_ADDR_POST_IMMED_PRED_V2) +DEF_CLASS32(ICLASS_LD" 110- -------- PP-0---- 0-------",LD_ADDR_POST_REG) +DEF_CLASS32(ICLASS_LD" 110- -------- PP-1---- --------",LD_ADDR_ABS_PLUS_REG_V4) +DEF_CLASS32(ICLASS_LD" 100- -------- PP----1- --------",LD_ADDR_POST_CREG_V2) +DEF_CLASS32(ICLASS_LD" 111- -------- PP------ 1-------",LD_ADDR_PRED_ABS_V4) + +DEF_FIELD32(ICLASS_LD" !!!- -------- PP------ --------",LD_Amode,"Amode") +DEF_FIELD32(ICLASS_LD" ---! !!------ PP------ --------",LD_Type,"Type") +DEF_FIELD32(ICLASS_LD" ---- --!----- PP------ --------",LD_UN,"Unsigned") + +#define STD_LD_ENC(TAG,OPC) \ +DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiddddd")\ +DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiddddd")\ +DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIddddd")\ +DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--ddddd")\ +DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIddddd")\ + + +#define STD_LDX_ENC(TAG,OPC) \ +DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiyyyyy")\ +DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiyyyyy")\ +DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIyyyyy")\ +DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--yyyyy")\ +DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIyyyyy")\ + + +#define STD_PLD_ENC(TAG,OPC) \ +DEF_ENC32(L2_pload##TAG##t_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP100tti iiiddddd")\ +DEF_ENC32(L2_pload##TAG##f_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP101tti iiiddddd")\ +DEF_ENC32(L2_pload##TAG##tnew_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP110tti iiiddddd")\ +DEF_ENC32(L2_pload##TAG##fnew_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP111tti iiiddddd")\ +DEF_ENC32(L4_pload##TAG##t_abs, ICLASS_LD" 1 11 "OPC" iiiii PP100tti 1--ddddd")\ +DEF_ENC32(L4_pload##TAG##f_abs, ICLASS_LD" 1 11 "OPC" iiiii PP101tti 1--ddddd")\ +DEF_ENC32(L4_pload##TAG##tnew_abs,ICLASS_LD" 1 11 "OPC" iiiii PP110tti 1--ddddd")\ +DEF_ENC32(L4_pload##TAG##fnew_abs,ICLASS_LD" 1 11 "OPC" iiiii PP111tti 1--ddddd") + + +/* 0 000 misc: dealloc,loadw_locked,dcfetch */ +STD_LD_ENC(rb, "1 000") +STD_LD_ENC(rub, "1 001") +STD_LD_ENC(rh, "1 010") +STD_LD_ENC(ruh, "1 011") +STD_LD_ENC(ri, "1 100") +STD_LD_ENC(rd, "1 110") /* note dest reg field LSB=0, 1 is reserved */ + +STD_PLD_ENC(rb, "1 000") +STD_PLD_ENC(rub, "1 001") +STD_PLD_ENC(rh, "1 010") +STD_PLD_ENC(ruh, "1 011") +STD_PLD_ENC(ri, "1 100") +STD_PLD_ENC(rd, "1 110") /* note dest reg field LSB=0, 1 is reserved */ + + +DEF_CLASS32( ICLASS_LD" 0--0 000----- PP------ --------",LD_MISC) +DEF_ANTICLASS32(ICLASS_LD" 0--0 000----- PP------ --------",LD_ADDR_ROFFSET) +DEF_ANTICLASS32(ICLASS_LD" 1010 000----- PP------ --------",LD_ADDR_POST_IMMED) +DEF_ANTICLASS32(ICLASS_LD" 1100 000----- PP------ --------",LD_ADDR_POST_REG) +DEF_ANTICLASS32(ICLASS_LD" 1110 000----- PP------ --------",LD_ADDR_POST_REG) + +DEF_ENC32(L2_deallocframe, ICLASS_LD" 000 0 000 sssss PP0----- ---ddddd") +DEF_ENC32(L4_return, ICLASS_LD" 011 0 000 sssss PP0000-- ---ddddd") +DEF_ENC32(L4_return_t, ICLASS_LD" 011 0 000 sssss PP0100vv ---ddddd") +DEF_ENC32(L4_return_f, ICLASS_LD" 011 0 000 sssss PP1100vv ---ddddd") +DEF_ENC32(L4_return_tnew_pt, ICLASS_LD" 011 0 000 sssss PP0110vv ---ddddd") +DEF_ENC32(L4_return_fnew_pt, ICLASS_LD" 011 0 000 sssss PP1110vv ---ddddd") +DEF_ENC32(L4_return_tnew_pnt, ICLASS_LD" 011 0 000 sssss PP0010vv ---ddddd") +DEF_ENC32(L4_return_fnew_pnt, ICLASS_LD" 011 0 000 sssss PP1010vv ---ddddd") + +DEF_ENC32(L2_loadw_locked,ICLASS_LD" 001 0 000 sssss PP00---- -00ddddd") + + + + + + +DEF_ENC32(L4_loadd_locked,ICLASS_LD" 001 0 000 sssss PP01---- -00ddddd") +DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii -01iiiii") +DEF_ENC32(Y2_dcfetchbo, ICLASS_LD" 010 0 000 sssss PP0--iii iiiiiiii") + + + + + + + + +/*******************************/ +/* */ +/* */ +/* STORE */ +/* */ +/* */ +/*******************************/ + +DEF_CLASS32(ICLASS_ST" ---- -------- PP------ --------",ST) + +DEF_FIELD32(ICLASS_ST" !!!- -------- PP------ --------",ST_Amode,"Amode") +DEF_FIELD32(ICLASS_ST" ---! !!------ PP------ --------",ST_Type,"Type") +DEF_FIELD32(ICLASS_ST" ---- --!----- PP------ --------",ST_UN,"Unsigned") + +DEF_CLASS32(ICLASS_ST" 0--1 -------- PP------ --------",ST_ADDR_ROFFSET) +DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 0-----0-",ST_ADDR_POST_IMMED) +DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 1-------",ST_ADDR_ABS_UPDATE_V4) +DEF_CLASS32(ICLASS_ST" 1011 -------- PP1----- --------",ST_ADDR_POST_IMMED_PRED_V2) +DEF_CLASS32(ICLASS_ST" 1111 -------- PP------ 1-------",ST_ADDR_PRED_ABS_V4) +DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 0-------",ST_ADDR_POST_REG) +DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 1-------",ST_ADDR_ABS_PLUS_REG_V4) +DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------1-",ST_ADDR_POST_CREG_V2) +DEF_CLASS32(ICLASS_ST" 0--0 1------- PP------ --------",ST_MISC_STORELIKE) +DEF_CLASS32(ICLASS_ST" 1--0 0------- PP------ --------",ST_MISC_BUSOP) +DEF_CLASS32(ICLASS_ST" 0--0 0------- PP------ --------",ST_MISC_CACHEOP) + + +#define STD_ST_ENC(TAG,OPC,SRC) \ +DEF_ENC32(S2_store##TAG##_io, ICLASS_ST" 0 ii "OPC" sssss PPi"SRC" iiiiiiii")\ +DEF_ENC32(S2_store##TAG##_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP0"SRC" 0iiii-0-")\ +DEF_ENC32(S4_store##TAG##_ap, ICLASS_ST" 1 01 "OPC" eeeee PP0"SRC" 1-IIIIII")\ +DEF_ENC32(S2_store##TAG##_pr, ICLASS_ST" 1 10 "OPC" xxxxx PPu"SRC" 0-------")\ +DEF_ENC32(S4_store##TAG##_ur, ICLASS_ST" 1 10 "OPC" uuuuu PPi"SRC" 1iIIIIII")\ + + +#define STD_PST_ENC(TAG,OPC,SRC) \ +DEF_ENC32(S2_pstore##TAG##t_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 0iiii0vv")\ +DEF_ENC32(S2_pstore##TAG##f_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 0iiii1vv")\ +DEF_ENC32(S2_pstore##TAG##tnew_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 1iiii0vv")\ +DEF_ENC32(S2_pstore##TAG##fnew_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP1"SRC" 1iiii1vv")\ +DEF_ENC32(S4_pstore##TAG##t_abs, ICLASS_ST" 1 11 "OPC" ---ii PP0"SRC" 1iiii0vv")\ +DEF_ENC32(S4_pstore##TAG##f_abs, ICLASS_ST" 1 11 "OPC" ---ii PP0"SRC" 1iiii1vv")\ +DEF_ENC32(S4_pstore##TAG##tnew_abs,ICLASS_ST" 1 11 "OPC" ---ii PP1"SRC" 1iiii0vv")\ +DEF_ENC32(S4_pstore##TAG##fnew_abs,ICLASS_ST" 1 11 "OPC" ---ii PP1"SRC" 1iiii1vv") + + +/* 0 0-- Store Misc */ +/* 0 1xx Available */ +STD_ST_ENC(rb, "1 000","ttttt") +STD_ST_ENC(rh, "1 010","ttttt") +STD_ST_ENC(rf, "1 011","ttttt") +STD_ST_ENC(ri, "1 100","ttttt") +STD_ST_ENC(rd, "1 110","ttttt") +STD_ST_ENC(rbnew, "1 101","00ttt") +STD_ST_ENC(rhnew, "1 101","01ttt") +STD_ST_ENC(rinew, "1 101","10ttt") + +STD_PST_ENC(rb, "1 000","ttttt") +STD_PST_ENC(rh, "1 010","ttttt") +STD_PST_ENC(rf, "1 011","ttttt") +STD_PST_ENC(ri, "1 100","ttttt") +STD_PST_ENC(rd, "1 110","ttttt") +STD_PST_ENC(rbnew, "1 101","00ttt") +STD_PST_ENC(rhnew, "1 101","01ttt") +STD_PST_ENC(rinew, "1 101","10ttt") + + + +/* User */ +/* xx - st_misc */ +/* */ +/* x bus/cache */ +/* x store/cache */ +DEF_ENC32(S2_allocframe, ICLASS_ST" 000 01 00xxxxx PP000iii iiiiiiii") +DEF_ENC32(S2_storew_locked,ICLASS_ST" 000 01 01sssss PP-ttttt ------dd") +DEF_ENC32(S4_stored_locked,ICLASS_ST" 000 01 11sssss PP0ttttt ------dd") +DEF_ENC32(Y2_dczeroa, ICLASS_ST" 000 01 10sssss PP0----- --------") + + +DEF_ENC32(Y2_barrier, ICLASS_ST" 100 00 00----- PP------ 000-----") +DEF_ENC32(Y2_syncht, ICLASS_ST" 100 00 10----- PP------ --------") + + + +DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------") +DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------") +DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------") + +/*******************************/ +/* */ +/* */ +/* JUMP */ +/* */ +/* */ +/*******************************/ + +DEF_CLASS32(ICLASS_J" ---- -------- PP------ --------",J) +DEF_CLASS32(ICLASS_J" 0--- -------- PP------ --------",JUMPR_MISC) +DEF_CLASS32(ICLASS_J" 10-- -------- PP------ --------",UCJUMP) +DEF_CLASS32(ICLASS_J" 110- -------- PP------ --------",CJUMP) +DEF_FIELD32(ICLASS_J" 110- -------- PP--!--- --------",J_DN,"Dot-new") +DEF_FIELD32(ICLASS_J" 110- -------- PP-!---- --------",J_PT,"Predict-taken") + + + +DEF_FIELDROW_DESC32(ICLASS_J" 0000 -------- PP------ --------","[#0] PC=(Rs), R31=return") +DEF_ENC32(J2_callr, ICLASS_J" 0000 101sssss PP------ --------") + +DEF_FIELDROW_DESC32(ICLASS_J" 0001 -------- PP------ --------","[#1] if (Pu) PC=(Rs), R31=return") +DEF_ENC32(J2_callrt, ICLASS_J" 0001 000sssss PP----uu --------") +DEF_ENC32(J2_callrf, ICLASS_J" 0001 001sssss PP----uu --------") + +DEF_FIELDROW_DESC32(ICLASS_J" 0010 -------- PP------ --------","[#2] PC=(Rs); ") +DEF_ENC32(J2_jumpr, ICLASS_J" 0010 100sssss PP------ --------") +DEF_ENC32(J4_hintjumpr, ICLASS_J" 0010 101sssss PP------ --------") + +DEF_FIELDROW_DESC32(ICLASS_J" 0011 -------- PP------ --------","[#3] if (Pu) PC=(Rs) ") +DEF_ENC32(J2_jumprt, ICLASS_J" 0011 010sssss PP-00-uu --------") +DEF_ENC32(J2_jumprf, ICLASS_J" 0011 011sssss PP-00-uu --------") +DEF_ENC32(J2_jumprtpt, ICLASS_J" 0011 010sssss PP-10-uu --------") +DEF_ENC32(J2_jumprfpt, ICLASS_J" 0011 011sssss PP-10-uu --------") +DEF_ENC32(J2_jumprtnew, ICLASS_J" 0011 010sssss PP-01-uu --------") +DEF_ENC32(J2_jumprfnew, ICLASS_J" 0011 011sssss PP-01-uu --------") +DEF_ENC32(J2_jumprtnewpt, ICLASS_J" 0011 010sssss PP-11-uu --------") +DEF_ENC32(J2_jumprfnewpt, ICLASS_J" 0011 011sssss PP-11-uu --------") + +DEF_FIELDROW_DESC32(ICLASS_J" 0100 -------- PP------ --------","[#4] (#u8) ") +DEF_ENC32(J2_trap0, ICLASS_J" 0100 00------ PP-iiiii ---iii--") + +DEF_FIELDROW_DESC32(ICLASS_J" 0110 -------- PP------ --------","[#6] icop(Rs) ") +DEF_ENC32(Y2_icinva, ICLASS_J" 0110 110sssss PP000--- --------") + +DEF_FIELDROW_DESC32(ICLASS_J" 0111 -------- PP------ --------","[#7] () ") +DEF_ENC32(Y2_isync, ICLASS_J" 0111 11000000 PP0---00 00000010") + +/* JUMP */ +DEF_FIELDROW_DESC32(ICLASS_J" 100- -------- PP------ --------","[#8,9] PC=(#r22)") +DEF_ENC32(J2_jump, ICLASS_J" 100i iiiiiiii PPiiiiii iiiiiii-") + +DEF_FIELDROW_DESC32(ICLASS_J" 101- -------- PP------ --------","[#10,11] PC=(#r22), R31=return") +DEF_ENC32(J2_call, ICLASS_J" 101i iiiiiiii PPiiiiii iiiiiii0") + +DEF_FIELDROW_DESC32(ICLASS_J" 1100 -------- PP------ --------","[#12] if (Pu) PC=(#r15)") +DEF_ENC32(J2_jumpt, ICLASS_J" 1100 ii0iiiii PPi00-uu iiiiiii-") +DEF_ENC32(J2_jumpf, ICLASS_J" 1100 ii1iiiii PPi00-uu iiiiiii-") +DEF_ENC32(J2_jumptpt, ICLASS_J" 1100 ii0iiiii PPi10-uu iiiiiii-") +DEF_ENC32(J2_jumpfpt, ICLASS_J" 1100 ii1iiiii PPi10-uu iiiiiii-") +DEF_ENC32(J2_jumptnew, ICLASS_J" 1100 ii0iiiii PPi01-uu iiiiiii-") +DEF_ENC32(J2_jumpfnew, ICLASS_J" 1100 ii1iiiii PPi01-uu iiiiiii-") +DEF_ENC32(J2_jumptnewpt,ICLASS_J" 1100 ii0iiiii PPi11-uu iiiiiii-") +DEF_ENC32(J2_jumpfnewpt,ICLASS_J" 1100 ii1iiiii PPi11-uu iiiiiii-") + +DEF_FIELDROW_DESC32(ICLASS_J" 1101 -------- PP------ --------","[#13] if (Pu) PC=(#r15), R31=return") +DEF_ENC32(J2_callt, ICLASS_J" 1101 ii0iiiii PPi-0-uu iiiiiii-") +DEF_ENC32(J2_callf, ICLASS_J" 1101 ii1iiiii PPi-0-uu iiiiiii-") + + + + + + + +/*******************************/ +/* */ +/* V4 */ +/* COMPOUND COMPARE-JUMPS */ +/* */ +/* */ +/*******************************/ + + +/* EJP: this has to match what we have in htmldocs.py... so I will call it CJ, we can change it */ +DEF_CLASS32(ICLASS_CJ" 0--- -------- PP------ --------",CJ) + +DEF_FIELDROW_DESC32(ICLASS_CJ" 00-- -------- -------- --------","[#0-3] pd=cmp.xx(R,#u5) ; if ([!]p0.new) jump:[h] #s9:2 ") +DEF_FIELDROW_DESC32(ICLASS_CJ" 010- -------- -------- --------","[#4,5] pd=cmp.eq(R,R) ; if ([!]p0.new) jump:[h] #s9:2 ") +DEF_FIELDROW_DESC32(ICLASS_CJ" 0110 -------- -------- --------","[#6] Rd=#u6 ; jump #s9:2 ") +DEF_FIELDROW_DESC32(ICLASS_CJ" 0111 -------- -------- --------","[#7] Rd=Rs ; jump #s9:2 ") + + +#define CMPJMPI_ENC(TAG,OPC) \ +DEF_ENC32(TAG##i_tp0_jump_t, ICLASS_CJ" 00 0 "OPC" 0iissss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_fp0_jump_t, ICLASS_CJ" 00 0 "OPC" 1iissss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_tp0_jump_nt, ICLASS_CJ" 00 0 "OPC" 0iissss PP0IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_fp0_jump_nt, ICLASS_CJ" 00 0 "OPC" 1iissss PP0IIIII iiiiiii-") \ +\ +DEF_ENC32(TAG##i_tp1_jump_t, ICLASS_CJ" 00 1 "OPC" 0iissss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_fp1_jump_t, ICLASS_CJ" 00 1 "OPC" 1iissss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_tp1_jump_nt, ICLASS_CJ" 00 1 "OPC" 0iissss PP0IIIII iiiiiii-") \ +DEF_ENC32(TAG##i_fp1_jump_nt, ICLASS_CJ" 00 1 "OPC" 1iissss PP0IIIII iiiiiii-") + +CMPJMPI_ENC(J4_cmpeq,"00") +CMPJMPI_ENC(J4_cmpgt,"01") +CMPJMPI_ENC(J4_cmpgtu,"10") + + +#define CMPJMP1I_ENC(TAG,OPC) \ +DEF_ENC32(TAG##_tp0_jump_t, ICLASS_CJ" 00 0 11 0iissss PP1---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_fp0_jump_t, ICLASS_CJ" 00 0 11 1iissss PP1---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_tp0_jump_nt, ICLASS_CJ" 00 0 11 0iissss PP0---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_fp0_jump_nt, ICLASS_CJ" 00 0 11 1iissss PP0---"OPC" iiiiiii-") \ +\ +DEF_ENC32(TAG##_tp1_jump_t, ICLASS_CJ" 00 1 11 0iissss PP1---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_fp1_jump_t, ICLASS_CJ" 00 1 11 1iissss PP1---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_tp1_jump_nt, ICLASS_CJ" 00 1 11 0iissss PP0---"OPC" iiiiiii-") \ +DEF_ENC32(TAG##_fp1_jump_nt, ICLASS_CJ" 00 1 11 1iissss PP0---"OPC" iiiiiii-") + +CMPJMP1I_ENC(J4_cmpeqn1,"00") +CMPJMP1I_ENC(J4_cmpgtn1,"01") +CMPJMP1I_ENC(J4_tstbit0,"11") + + + +#define CMPJMPR_ENC(TAG,OPC) \ +DEF_ENC32(TAG##_tp0_jump_t, ICLASS_CJ" 01 0 "OPC" 0iissss PP10tttt iiiiiii-") \ +DEF_ENC32(TAG##_fp0_jump_t, ICLASS_CJ" 01 0 "OPC" 1iissss PP10tttt iiiiiii-") \ +DEF_ENC32(TAG##_tp0_jump_nt, ICLASS_CJ" 01 0 "OPC" 0iissss PP00tttt iiiiiii-") \ +DEF_ENC32(TAG##_fp0_jump_nt, ICLASS_CJ" 01 0 "OPC" 1iissss PP00tttt iiiiiii-") \ +\ +DEF_ENC32(TAG##_tp1_jump_t, ICLASS_CJ" 01 0 "OPC" 0iissss PP11tttt iiiiiii-") \ +DEF_ENC32(TAG##_fp1_jump_t, ICLASS_CJ" 01 0 "OPC" 1iissss PP11tttt iiiiiii-") \ +DEF_ENC32(TAG##_tp1_jump_nt, ICLASS_CJ" 01 0 "OPC" 0iissss PP01tttt iiiiiii-") \ +DEF_ENC32(TAG##_fp1_jump_nt, ICLASS_CJ" 01 0 "OPC" 1iissss PP01tttt iiiiiii-") + +CMPJMPR_ENC(J4_cmpeq,"00") +CMPJMPR_ENC(J4_cmpgt,"01") +CMPJMPR_ENC(J4_cmpgtu,"10") + + +DEF_ENC32(J4_jumpseti, ICLASS_CJ" 0110 --iidddd PPIIIIII iiiiiii-") +DEF_ENC32(J4_jumpsetr, ICLASS_CJ" 0111 --iissss PP--dddd iiiiiii-") + + +DEF_EXT_SPACE(EXT_CJ, ICLASS_CJ"1 iii iiiiiiii PPiiiiii iiiiiiii") + + + +DEF_CLASS32(ICLASS_NCJ" 0--- -------- PP------ --------",NCJ) +DEF_FIELDROW_DESC32(ICLASS_NCJ" 00-- -------- -------- --------","[#0-3] if (cmp.xx(R.new,R)) jump:[h] #s9:2 ") +DEF_FIELDROW_DESC32(ICLASS_NCJ" 01-- -------- -------- --------","[#4-7] if (cmp.xx(R.new,#U5)) jump:[h] #s9:2 ") + +#define OPRJMP_ENC(TAG,OPC) \ +DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 00 "OPC" 0ii-sss PP1ttttt iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 00 "OPC" 1ii-sss PP1ttttt iiiiiii-") \ +DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 00 "OPC" 0ii-sss PP0ttttt iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 00 "OPC" 1ii-sss PP0ttttt iiiiiii-") + +OPRJMP_ENC(J4_cmpeq, "000") +OPRJMP_ENC(J4_cmpgt, "001") +OPRJMP_ENC(J4_cmpgtu, "010") +OPRJMP_ENC(J4_cmplt, "011") +OPRJMP_ENC(J4_cmpltu, "100") + + +#define OPIJMP_ENC(TAG,OPC) \ +DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 01 "OPC" 0ii-sss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 01 "OPC" 1ii-sss PP1IIIII iiiiiii-") \ +DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 0ii-sss PP0IIIII iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 1ii-sss PP0IIIII iiiiiii-") + +OPIJMP_ENC(J4_cmpeqi, "000") +OPIJMP_ENC(J4_cmpgti, "001") +OPIJMP_ENC(J4_cmpgtui, "010") + + +#define OPI1JMP_ENC(TAG,OPC) \ +DEF_ENC32(TAG##_t_jumpnv_t, ICLASS_NCJ" 01 "OPC" 0ii-sss PP1----- iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_t, ICLASS_NCJ" 01 "OPC" 1ii-sss PP1----- iiiiiii-") \ +DEF_ENC32(TAG##_t_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 0ii-sss PP0----- iiiiiii-") \ +DEF_ENC32(TAG##_f_jumpnv_nt, ICLASS_NCJ" 01 "OPC" 1ii-sss PP0----- iiiiiii-") + +OPI1JMP_ENC(J4_cmpeqn1, "100") +OPI1JMP_ENC(J4_cmpgtn1, "101") +OPI1JMP_ENC(J4_tstbit0, "011") + + +DEF_EXT_SPACE(EXT_NCJ, ICLASS_NCJ"1 iii iiiiiiii PPiiiiii iiiiiiii") + + + +/*******************************/ +/* */ +/* */ +/* CR */ +/* */ +/* */ +/*******************************/ + + + +DEF_CLASS32(ICLASS_CR" ---- -------- PP------ --------",CR) +DEF_CLASS32(ICLASS_CR" -0-- -------- PP------ --------",CRUSER) +DEF_CLASS32(ICLASS_CR" -1-- -------- PP------ --------",CRSUPER) + +DEF_FIELD32(ICLASS_CR" -!-- -------- PP------ --------",CR_sm,"Supervisor mode only") + +/* User CR ops */ + +DEF_FIELDROW_DESC32( ICLASS_CR" 0000 -------- PP------ --------","[#0] (Rs,#r8)") +DEF_ENC32(J2_loop0r, ICLASS_CR" 0000 000sssss PP-iiiii ---ii---") +DEF_ENC32(J2_loop1r, ICLASS_CR" 0000 001sssss PP-iiiii ---ii---") +DEF_ENC32(J2_ploop1sr, ICLASS_CR" 0000 101sssss PP-iiiii ---ii---") +DEF_ENC32(J2_ploop2sr, ICLASS_CR" 0000 110sssss PP-iiiii ---ii---") +DEF_ENC32(J2_ploop3sr, ICLASS_CR" 0000 111sssss PP-iiiii ---ii---") + +DEF_FIELDROW_DESC32( ICLASS_CR" 0001 -------- PP------ --------","[#1] (Rs,#r13)") +DEF_ENC32(J2_jumprz, ICLASS_CR" 0001 00isssss PPi0iiii iiiiiii-") +DEF_ENC32(J2_jumprzpt, ICLASS_CR" 0001 00isssss PPi1iiii iiiiiii-") +DEF_ENC32(J2_jumprnz, ICLASS_CR" 0001 10isssss PPi0iiii iiiiiii-") +DEF_ENC32(J2_jumprnzpt, ICLASS_CR" 0001 10isssss PPi1iiii iiiiiii-") + +DEF_ENC32(J2_jumprgtez, ICLASS_CR" 0001 01isssss PPi0iiii iiiiiii-") +DEF_ENC32(J2_jumprgtezpt,ICLASS_CR" 0001 01isssss PPi1iiii iiiiiii-") +DEF_ENC32(J2_jumprltez, ICLASS_CR" 0001 11isssss PPi0iiii iiiiiii-") +DEF_ENC32(J2_jumprltezpt,ICLASS_CR" 0001 11isssss PPi1iiii iiiiiii-") + +DEF_FIELDROW_DESC32( ICLASS_CR" 0010 -------- PP------ --------","[#2] Cd=Rs ") +DEF_ENC32(A2_tfrrcr, ICLASS_CR" 0010 001sssss PP------ ---ddddd") + +DEF_FIELDROW_DESC32( ICLASS_CR" 0011 -------- PP------ --------","[#3] Cdd=Rss ") +DEF_ENC32(A4_tfrpcp, ICLASS_CR" 0011 001sssss PP------ ---ddddd") + +DEF_FIELDROW_DESC32( ICLASS_CR" 1000 -------- PP------ --------","[#8] Rdd=Css ") +DEF_ENC32(A4_tfrcpp, ICLASS_CR" 1000 000sssss PP------ ---ddddd") + +DEF_FIELDROW_DESC32( ICLASS_CR" 1001 -------- PP------ --------","[#9] (#r8,#U10)") +DEF_ENC32(J2_ploop1si, ICLASS_CR" 1001 101IIIII PP-iiiii IIIii-II") +DEF_ENC32(J2_ploop2si, ICLASS_CR" 1001 110IIIII PP-iiiii IIIii-II") +DEF_ENC32(J2_ploop3si, ICLASS_CR" 1001 111IIIII PP-iiiii IIIii-II") +DEF_ENC32(J2_loop0i, ICLASS_CR" 1001 000IIIII PP-iiiii IIIii-II") +DEF_ENC32(J2_loop1i, ICLASS_CR" 1001 001IIIII PP-iiiii IIIii-II") + +DEF_FIELDROW_DESC32( ICLASS_CR" 1010 -------- PP------ --------","[#10] Rd=Cs ") +DEF_ENC32(A2_tfrcrr, ICLASS_CR" 1010 000sssss PP------ ---ddddd") +DEF_ENC32(C4_addipc, ICLASS_CR" 1010 01001001 PP-iiiii i--ddddd") + + +DEF_FIELDROW_DESC32( ICLASS_CR" 1011 -------- PP0----- --------","[#11] Pd=(Ps,Pt,Pu)") +DEF_ENC32(C2_and, ICLASS_CR" 1011 0000--ss PP0---tt ------dd") +DEF_ENC32(C2_or, ICLASS_CR" 1011 0010--ss PP0---tt ------dd") +DEF_ENC32(C2_xor, ICLASS_CR" 1011 0100--ss PP0---tt ------dd") +DEF_ENC32(C2_andn, ICLASS_CR" 1011 0110--ss PP0---tt ------dd") +DEF_ENC32(C2_any8, ICLASS_CR" 1011 1000--ss PP0----- ------dd") +DEF_ENC32(C2_all8, ICLASS_CR" 1011 1010--ss PP0----- ------dd") +DEF_ENC32(C2_not, ICLASS_CR" 1011 1100--ss PP0----- ------dd") +DEF_ENC32(C2_orn, ICLASS_CR" 1011 1110--ss PP0---tt ------dd") + +DEF_ENC32(C4_and_and, ICLASS_CR" 1011 0001--ss PP0---tt uu----dd") +DEF_ENC32(C4_and_or, ICLASS_CR" 1011 0011--ss PP0---tt uu----dd") +DEF_ENC32(C4_or_and, ICLASS_CR" 1011 0101--ss PP0---tt uu----dd") +DEF_ENC32(C4_or_or, ICLASS_CR" 1011 0111--ss PP0---tt uu----dd") +DEF_ENC32(C4_and_andn, ICLASS_CR" 1011 1001--ss PP0---tt uu----dd") +DEF_ENC32(C4_and_orn, ICLASS_CR" 1011 1011--ss PP0---tt uu----dd") +DEF_ENC32(C4_or_andn, ICLASS_CR" 1011 1101--ss PP0---tt uu----dd") +DEF_ENC32(C4_or_orn, ICLASS_CR" 1011 1111--ss PP0---tt uu----dd") + +DEF_ENC32(C4_fastcorner9, ICLASS_CR"1011 0000--ss PP1---tt 1--1--dd") +DEF_ENC32(C4_fastcorner9_not, ICLASS_CR"1011 0001--ss PP1---tt 1--1--dd") + + + +/*******************************/ +/* */ +/* */ +/* M */ +/* */ +/* */ +/*******************************/ + + +DEF_CLASS32(ICLASS_M" ---- -------- PP------ --------",M) +DEF_FIELD32(ICLASS_M" !!!! -------- PP------ --------",M_RegType,"Register Type") +DEF_FIELD32(ICLASS_M" ---- !!!----- PP------ --------",M_MajOp,"Major Opcode") +DEF_FIELD32(ICLASS_M" ---- -------- PP------ !!!-----",M_MinOp,"Minor Opcode") + + + +#define SP_MPY(TAG,REGTYPE,DSTCHARS,SAT,RND,UNS)\ +DEF_ENC32(TAG##_ll_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"00" DSTCHARS)\ +DEF_ENC32(TAG##_lh_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"01" DSTCHARS)\ +DEF_ENC32(TAG##_hl_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"10" DSTCHARS)\ +DEF_ENC32(TAG##_hh_s0, ICLASS_M REGTYPE "0" UNS RND"sssss PP-ttttt "SAT"11" DSTCHARS)\ +DEF_ENC32(TAG##_ll_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"00" DSTCHARS)\ +DEF_ENC32(TAG##_lh_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"01" DSTCHARS)\ +DEF_ENC32(TAG##_hl_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"10" DSTCHARS)\ +DEF_ENC32(TAG##_hh_s1, ICLASS_M REGTYPE "1" UNS RND"sssss PP-ttttt "SAT"11" DSTCHARS) + +/* Double precision */ +#define MPY_ENC(TAG,REGTYPE,DSTCHARS,SAT,RNDNAC,UNS,SHFT,VMIN2)\ +DEF_ENC32(TAG, ICLASS_M REGTYPE SHFT UNS RNDNAC"sssss PP0ttttt "SAT VMIN2 DSTCHARS) + +#define MPYI_ENC(TAG,REGTYPE,DSTCHARS,RNDNAC,UNS,SHFT)\ +DEF_ENC32(TAG, ICLASS_M REGTYPE SHFT UNS RNDNAC"sssss PP0iiiii iii" DSTCHARS) + + +DEF_FIELDROW_DESC32(ICLASS_M" 0000 -------- PP------ --------","[#0] Rd=(Rs,#u8)") +MPYI_ENC(M2_mpysip, "0000","ddddd","-","-","0" ) +MPYI_ENC(M2_mpysin, "0000","ddddd","-","-","1" ) + + +DEF_FIELDROW_DESC32(ICLASS_M" 0001 -------- PP------ --------","[#1] Rx=(Rs,#u8)") +MPYI_ENC(M2_macsip, "0001","xxxxx","-","-","0" ) +MPYI_ENC(M2_macsin, "0001","xxxxx","-","-","1" ) + + +DEF_FIELDROW_DESC32(ICLASS_M" 0010 -------- PP------ --------","[#2] Rx=(Rs,#s8)") +MPYI_ENC(M2_accii, "0010","xxxxx","-","-","0" ) +MPYI_ENC(M2_naccii, "0010","xxxxx","-","-","1" ) + + +DEF_FIELDROW_DESC32(ICLASS_M" 0011 -------- PP------ --------","[#3] Ry=(Ru,(Rs,Ry)) ") +DEF_ENC32(M4_mpyrr_addr,ICLASS_M" 0011 000sssss PP-yyyyy ---uuuuu") + + +DEF_FIELDROW_DESC32(ICLASS_M" 0100 -------- PP------ --------","[#4] Rdd=(Rs,Rt)") +DEF_FIELD32(ICLASS_M" 0100 -------- PP------ --!-----",Ma_tH,"Rt is High") /*Rt high */ +DEF_FIELD32(ICLASS_M" 0100 -------- PP------ -!------",Ma_sH,"Rs is High") /* Rs high */ +SP_MPY(M2_mpyd, "0100","ddddd","-","0","0") +SP_MPY(M2_mpyd_rnd, "0100","ddddd","-","1","0") +SP_MPY(M2_mpyud, "0100","ddddd","-","0","1") + + +DEF_FIELDROW_DESC32(ICLASS_M" 0101 -------- PP------ --------","[#5] Rdd=(Rs,Rt)") +MPY_ENC(M2_dpmpyss_s0, "0101","ddddd","0","0","0","0","00") +MPY_ENC(M2_dpmpyuu_s0, "0101","ddddd","0","0","1","0","00") +MPY_ENC(M2_vmpy2s_s0, "0101","ddddd","1","0","0","0","01") +MPY_ENC(M2_vmpy2s_s1, "0101","ddddd","1","0","0","1","01") +MPY_ENC(M2_cmpyi_s0, "0101","ddddd","0","0","0","0","01") +MPY_ENC(M2_cmpyr_s0, "0101","ddddd","0","0","0","0","10") +MPY_ENC(M2_cmpys_s0, "0101","ddddd","1","0","0","0","10") +MPY_ENC(M2_cmpys_s1, "0101","ddddd","1","0","0","1","10") +MPY_ENC(M2_cmpysc_s0, "0101","ddddd","1","0","1","0","10") +MPY_ENC(M2_cmpysc_s1, "0101","ddddd","1","0","1","1","10") +MPY_ENC(M2_vmpy2su_s0, "0101","ddddd","1","0","0","0","11") +MPY_ENC(M2_vmpy2su_s1, "0101","ddddd","1","0","0","1","11") +MPY_ENC(M4_pmpyw, "0101","ddddd","1","0","1","0","11") +MPY_ENC(M4_vpmpyh, "0101","ddddd","1","0","1","1","11") +MPY_ENC(M5_vmpybuu, "0101","ddddd","0","0","0","1","01") +MPY_ENC(M5_vmpybsu, "0101","ddddd","0","0","1","0","01") + + + + +DEF_FIELDROW_DESC32(ICLASS_M" 0110 -------- PP------ --------","[#6] Rxx=(Rs,Rt)") +DEF_FIELD32(ICLASS_M" 0110 -------- PP------ --!-----",Mb_tH,"Rt is High") /*Rt high */ +DEF_FIELD32(ICLASS_M" 0110 -------- PP------ -!------",Mb_sH,"Rs is High") /* Rs high */ +SP_MPY(M2_mpyd_acc, "0110","xxxxx","0","0","0") +SP_MPY(M2_mpyud_acc, "0110","xxxxx","0","0","1") +SP_MPY(M2_mpyd_nac, "0110","xxxxx","0","1","0") +SP_MPY(M2_mpyud_nac, "0110","xxxxx","0","1","1") + + +DEF_FIELDROW_DESC32(ICLASS_M" 0111 -------- PP------ --------","[#7] Rxx=(Rs,Rt)") +MPY_ENC(M2_dpmpyss_acc_s0, "0111","xxxxx","0","0","0","0","00") +MPY_ENC(M2_dpmpyss_nac_s0, "0111","xxxxx","0","1","0","0","00") +MPY_ENC(M2_dpmpyuu_acc_s0, "0111","xxxxx","0","0","1","0","00") +MPY_ENC(M2_dpmpyuu_nac_s0, "0111","xxxxx","0","1","1","0","00") +MPY_ENC(M2_vmac2s_s0, "0111","xxxxx","1","0","0","0","01") +MPY_ENC(M2_vmac2s_s1, "0111","xxxxx","1","0","0","1","01") +MPY_ENC(M2_cmaci_s0, "0111","xxxxx","0","0","0","0","01") +MPY_ENC(M2_cmacr_s0, "0111","xxxxx","0","0","0","0","10") +MPY_ENC(M2_cmacs_s0, "0111","xxxxx","1","0","0","0","10") +MPY_ENC(M2_cmacs_s1, "0111","xxxxx","1","0","0","1","10") +MPY_ENC(M2_cmacsc_s0, "0111","xxxxx","1","0","1","0","10") +MPY_ENC(M2_cmacsc_s1, "0111","xxxxx","1","0","1","1","10") +MPY_ENC(M2_vmac2, "0111","xxxxx","0","1","0","0","01") +MPY_ENC(M2_cnacs_s0, "0111","xxxxx","1","0","0","0","11") +MPY_ENC(M2_cnacs_s1, "0111","xxxxx","1","0","0","1","11") +MPY_ENC(M2_cnacsc_s0, "0111","xxxxx","1","0","1","0","11") +MPY_ENC(M2_cnacsc_s1, "0111","xxxxx","1","0","1","1","11") +MPY_ENC(M2_vmac2su_s0, "0111","xxxxx","1","1","1","0","01") +MPY_ENC(M2_vmac2su_s1, "0111","xxxxx","1","1","1","1","01") +MPY_ENC(M4_pmpyw_acc, "0111","xxxxx","1","1","0","0","11") +MPY_ENC(M4_vpmpyh_acc, "0111","xxxxx","1","1","0","1","11") +MPY_ENC(M5_vmacbuu, "0111","xxxxx","0","0","0","1","01") +MPY_ENC(M5_vmacbsu, "0111","xxxxx","0","0","1","1","01") + + + + + +DEF_FIELDROW_DESC32(ICLASS_M" 1000 -------- PP------ --------","[#8] Rdd=(Rss,Rtt)") +MPY_ENC(M2_vrcmpyi_s0, "1000","ddddd","0","0","0","0","00") +MPY_ENC(M2_vdmpys_s0, "1000","ddddd","1","0","0","0","00") +MPY_ENC(M2_vdmpys_s1, "1000","ddddd","1","0","0","1","00") +MPY_ENC(M2_vrcmpyi_s0c, "1000","ddddd","0","0","1","0","00") +MPY_ENC(M2_vabsdiffw, "1000","ddddd","0","1","0","0","00") +MPY_ENC(M6_vabsdiffub, "1000","ddddd","0","1","0","1","00") +MPY_ENC(M2_vabsdiffh, "1000","ddddd","0","1","1","0","00") +MPY_ENC(M6_vabsdiffb, "1000","ddddd","0","1","1","1","00") +MPY_ENC(M2_vrcmpys_s1_h, "1000","ddddd","1","1","0","1","00") +MPY_ENC(M2_vrcmpys_s1_l, "1000","ddddd","1","1","1","1","00") +MPY_ENC(M2_vrcmpyr_s0c, "1000","ddddd","0","1","1","0","01") +MPY_ENC(M2_vrcmpyr_s0, "1000","ddddd","0","0","0","0","01") +MPY_ENC(A2_vraddub, "1000","ddddd","0","0","1","0","01") +MPY_ENC(M2_mmpyl_s0, "1000","ddddd","1","0","0","0","01") +MPY_ENC(M2_mmpyl_s1, "1000","ddddd","1","0","0","1","01") +MPY_ENC(M2_mmpyl_rs0, "1000","ddddd","1","1","0","0","01") +MPY_ENC(M2_mmpyl_rs1, "1000","ddddd","1","1","0","1","01") +MPY_ENC(M2_mmpyul_s0, "1000","ddddd","1","0","1","0","01") +MPY_ENC(M2_mmpyul_s1, "1000","ddddd","1","0","1","1","01") +MPY_ENC(M2_mmpyul_rs0, "1000","ddddd","1","1","1","0","01") +MPY_ENC(M2_mmpyul_rs1, "1000","ddddd","1","1","1","1","01") +MPY_ENC(M2_vrmpy_s0, "1000","ddddd","0","0","0","0","10") +MPY_ENC(A2_vrsadub, "1000","ddddd","0","0","1","0","10") +MPY_ENC(M2_vmpy2es_s0, "1000","ddddd","1","0","0","0","10") +MPY_ENC(M2_vmpy2es_s1, "1000","ddddd","1","0","0","1","10") +MPY_ENC(M2_vcmpy_s0_sat_i, "1000","ddddd","1","0","1","0","10") +MPY_ENC(M2_vcmpy_s0_sat_r, "1000","ddddd","1","1","0","0","10") +MPY_ENC(M2_vcmpy_s1_sat_i, "1000","ddddd","1","0","1","1","10") +MPY_ENC(M2_vcmpy_s1_sat_r, "1000","ddddd","1","1","0","1","10") + +MPY_ENC(M2_mmpyh_s0, "1000","ddddd","1","0","0","0","11") +MPY_ENC(M2_mmpyh_s1, "1000","ddddd","1","0","0","1","11") +MPY_ENC(M2_mmpyh_rs0, "1000","ddddd","1","1","0","0","11") +MPY_ENC(M2_mmpyh_rs1, "1000","ddddd","1","1","0","1","11") +MPY_ENC(M2_mmpyuh_s0, "1000","ddddd","1","0","1","0","11") +MPY_ENC(M2_mmpyuh_s1, "1000","ddddd","1","0","1","1","11") +MPY_ENC(M2_mmpyuh_rs0, "1000","ddddd","1","1","1","0","11") +MPY_ENC(M2_mmpyuh_rs1, "1000","ddddd","1","1","1","1","11") + +MPY_ENC(M4_vrmpyeh_s0, "1000","ddddd","1","0","1","0","00") +MPY_ENC(M4_vrmpyeh_s1, "1000","ddddd","1","0","1","1","00") +MPY_ENC(M4_vrmpyoh_s0, "1000","ddddd","0","1","0","0","10") +MPY_ENC(M4_vrmpyoh_s1, "1000","ddddd","0","1","0","1","10") +MPY_ENC(M5_vrmpybuu, "1000","ddddd","0","0","0","1","01") +MPY_ENC(M5_vrmpybsu, "1000","ddddd","0","0","1","1","01") +MPY_ENC(M5_vdmpybsu, "1000","ddddd","0","1","0","1","01") + +MPY_ENC(F2_dfadd, "1000","ddddd","0","0","0","0","11") +MPY_ENC(F2_dfsub, "1000","ddddd","0","0","0","1","11") +MPY_ENC(F2_dfmpyfix, "1000","ddddd","0","0","1","0","11") +MPY_ENC(F2_dfmin, "1000","ddddd","0","0","1","1","11") +MPY_ENC(F2_dfmax, "1000","ddddd","0","1","0","0","11") +MPY_ENC(F2_dfmpyll, "1000","ddddd","0","1","0","1","11") +#ifdef ADD_DP_OPS +MPY_ENC(F2_dfdivcheat, "1000","ddddd","0","0","0","1","00") + +MPY_ENC(F2_dffixupn, "1000","ddddd","0","1","0","1","11") +MPY_ENC(F2_dffixupd, "1000","ddddd","0","1","1","0","11") +MPY_ENC(F2_dfrecipa, "1000","ddddd","0","1","1","1","ee") +#endif + +MPY_ENC(M7_dcmpyrw, "1000","ddddd","0","0","0","1","10") +MPY_ENC(M7_dcmpyrwc, "1000","ddddd","0","0","1","1","10") +MPY_ENC(M7_dcmpyiw, "1000","ddddd","0","1","1","0","10") +MPY_ENC(M7_dcmpyiwc, "1000","ddddd","0","1","1","1","10") + + + +DEF_FIELDROW_DESC32(ICLASS_M" 1001 -------- PP------ --------","[#9] Rd=(Rss,Rtt)") +MPY_ENC(M2_vdmpyrs_s0, "1001","ddddd","0","0","0","0","00") +MPY_ENC(M2_vdmpyrs_s1, "1001","ddddd","0","0","0","1","00") + +MPY_ENC(M7_wcmpyrw, "1001","ddddd","0","0","1","0","00") +MPY_ENC(M7_wcmpyrw_rnd, "1001","ddddd","0","0","1","1","00") +MPY_ENC(M7_wcmpyiw, "1001","ddddd","0","1","0","0","00") +MPY_ENC(M7_wcmpyiw_rnd, "1001","ddddd","0","1","0","1","00") + +MPY_ENC(M7_wcmpyrwc, "1001","ddddd","0","1","1","0","00") +MPY_ENC(M7_wcmpyrwc_rnd, "1001","ddddd","0","1","1","1","00") +MPY_ENC(M7_wcmpyiwc, "1001","ddddd","1","0","0","0","00") +MPY_ENC(M7_wcmpyiwc_rnd, "1001","ddddd","1","0","0","1","00") + + + +MPY_ENC(M2_vradduh, "1001","ddddd","-","-","-","0","01") +MPY_ENC(M2_vrcmpys_s1rp_h, "1001","ddddd","1","1","-","1","10") +MPY_ENC(M2_vrcmpys_s1rp_l, "1001","ddddd","1","1","-","1","11") +MPY_ENC(M2_vraddh, "1001","ddddd","1","1","-","0","11") + + +DEF_FIELDROW_DESC32(ICLASS_M" 1010 -------- PP------ --------","[#10] Rxx=(Rss,Rtt)") +MPY_ENC(M2_vrcmaci_s0, "1010","xxxxx","0","0","0","0","00") +MPY_ENC(M2_vdmacs_s0, "1010","xxxxx","1","0","0","0","00") +MPY_ENC(M2_vdmacs_s1, "1010","xxxxx","1","0","0","1","00") +MPY_ENC(M2_vrcmaci_s0c, "1010","xxxxx","0","0","1","0","00") +MPY_ENC(M2_vcmac_s0_sat_i, "1010","xxxxx","1","0","1","0","00") +MPY_ENC(M2_vcmac_s0_sat_r, "1010","xxxxx","1","1","0","0","00") +MPY_ENC(M2_vrcmpys_acc_s1_h, "1010","xxxxx","1","1","0","1","00") +MPY_ENC(M2_vrcmpys_acc_s1_l, "1010","xxxxx","1","1","1","1","00") +MPY_ENC(M2_vrcmacr_s0, "1010","xxxxx","0","0","0","0","01") +MPY_ENC(A2_vraddub_acc, "1010","xxxxx","0","0","1","0","01") +MPY_ENC(M2_mmacls_s0, "1010","xxxxx","1","0","0","0","01") +MPY_ENC(M2_mmacls_s1, "1010","xxxxx","1","0","0","1","01") +MPY_ENC(M2_mmacls_rs0, "1010","xxxxx","1","1","0","0","01") +MPY_ENC(M2_mmacls_rs1, "1010","xxxxx","1","1","0","1","01") +MPY_ENC(M2_mmaculs_s0, "1010","xxxxx","1","0","1","0","01") +MPY_ENC(M2_mmaculs_s1, "1010","xxxxx","1","0","1","1","01") +MPY_ENC(M2_mmaculs_rs0, "1010","xxxxx","1","1","1","0","01") +MPY_ENC(M2_mmaculs_rs1, "1010","xxxxx","1","1","1","1","01") +MPY_ENC(M2_vrcmacr_s0c, "1010","xxxxx","0","1","1","0","01") +MPY_ENC(M2_vrmac_s0, "1010","xxxxx","0","0","0","0","10") +MPY_ENC(A2_vrsadub_acc, "1010","xxxxx","0","0","1","0","10") +MPY_ENC(M2_vmac2es_s0, "1010","xxxxx","1","0","0","0","10") +MPY_ENC(M2_vmac2es_s1, "1010","xxxxx","1","0","0","1","10") +MPY_ENC(M2_vmac2es, "1010","xxxxx","0","1","0","0","10") +MPY_ENC(M2_mmachs_s0, "1010","xxxxx","1","0","0","0","11") +MPY_ENC(M2_mmachs_s1, "1010","xxxxx","1","0","0","1","11") +MPY_ENC(M2_mmachs_rs0, "1010","xxxxx","1","1","0","0","11") +MPY_ENC(M2_mmachs_rs1, "1010","xxxxx","1","1","0","1","11") +MPY_ENC(M2_mmacuhs_s0, "1010","xxxxx","1","0","1","0","11") +MPY_ENC(M2_mmacuhs_s1, "1010","xxxxx","1","0","1","1","11") +MPY_ENC(M2_mmacuhs_rs0, "1010","xxxxx","1","1","1","0","11") +MPY_ENC(M2_mmacuhs_rs1, "1010","xxxxx","1","1","1","1","11") +MPY_ENC(M4_vrmpyeh_acc_s0, "1010","xxxxx","1","1","0","0","10") +MPY_ENC(M4_vrmpyeh_acc_s1, "1010","xxxxx","1","1","0","1","10") +MPY_ENC(M4_vrmpyoh_acc_s0, "1010","xxxxx","1","1","1","0","10") +MPY_ENC(M4_vrmpyoh_acc_s1, "1010","xxxxx","1","1","1","1","10") +MPY_ENC(M5_vrmacbuu, "1010","xxxxx","0","0","0","1","01") +MPY_ENC(M5_vrmacbsu, "1010","xxxxx","0","0","1","1","01") +MPY_ENC(M5_vdmacbsu, "1010","xxxxx","0","1","0","0","01") + +MPY_ENC(F2_dfmpylh, "1010","xxxxx","0","0","0","0","11") +MPY_ENC(F2_dfmpyhh, "1010","xxxxx","0","0","0","1","11") +#ifdef ADD_DP_OPS +MPY_ENC(F2_dfmpyhh, "1010","xxxxx","0","0","1","0","11") +MPY_ENC(F2_dffma, "1010","xxxxx","0","0","0","0","11") +MPY_ENC(F2_dffms, "1010","xxxxx","0","0","0","1","11") + +MPY_ENC(F2_dffma_lib, "1010","xxxxx","0","0","1","0","11") +MPY_ENC(F2_dffms_lib, "1010","xxxxx","0","0","1","1","11") +MPY_ENC(F2_dffma_sc, "1010","xxxxx","0","1","1","1","uu") +#endif + + +MPY_ENC(M7_dcmpyrw_acc, "1010","xxxxx","0","0","0","1","10") +MPY_ENC(M7_dcmpyrwc_acc, "1010","xxxxx","0","0","1","1","10") +MPY_ENC(M7_dcmpyiw_acc, "1010","xxxxx","0","1","1","0","10") +MPY_ENC(M7_dcmpyiwc_acc, "1010","xxxxx","1","0","1","0","10") + + + + +/* +*/ + +DEF_FIELDROW_DESC32(ICLASS_M" 1011 -------- PP------ --------","[#11] Reserved") +MPY_ENC(F2_sfadd, "1011","ddddd","0","0","0","0","00") +MPY_ENC(F2_sfsub, "1011","ddddd","0","0","0","0","01") +MPY_ENC(F2_sfmax, "1011","ddddd","0","0","0","1","00") +MPY_ENC(F2_sfmin, "1011","ddddd","0","0","0","1","01") +MPY_ENC(F2_sfmpy, "1011","ddddd","0","0","1","0","00") +MPY_ENC(F2_sffixupn, "1011","ddddd","0","0","1","1","00") +MPY_ENC(F2_sffixupd, "1011","ddddd","0","0","1","1","01") + +DEF_FIELDROW_DESC32(ICLASS_M" 1100 -------- PP------ --------","[#12] Rd=(Rs,Rt)") +DEF_FIELD32(ICLASS_M" 1100 -------- PP------ --!-----",Mc_tH,"Rt is High") /*Rt high */ +DEF_FIELD32(ICLASS_M" 1100 -------- PP------ -!------",Mc_sH,"Rs is High") /* Rs high */ +SP_MPY(M2_mpy, "1100","ddddd","0","0","0") +SP_MPY(M2_mpy_sat, "1100","ddddd","1","0","0") +SP_MPY(M2_mpy_rnd, "1100","ddddd","0","1","0") +SP_MPY(M2_mpy_sat_rnd, "1100","ddddd","1","1","0") +SP_MPY(M2_mpyu, "1100","ddddd","0","0","1") + +DEF_FIELDROW_DESC32(ICLASS_M" 1101 -------- PP------ --------","[#13] Rd=(Rs,Rt)") +/* EJP: same as mpyi MPY_ENC(M2_mpyui, "1101","ddddd","0","0","1","0","00") */ +MPY_ENC(M2_mpyi, "1101","ddddd","0","0","0","0","00") +MPY_ENC(M2_mpy_up, "1101","ddddd","0","0","0","0","01") +MPY_ENC(M2_mpyu_up, "1101","ddddd","0","0","1","0","01") +MPY_ENC(M2_dpmpyss_rnd_s0, "1101","ddddd","0","1","0","0","01") +MPY_ENC(M2_cmpyrs_s0, "1101","ddddd","1","1","0","0","10") +MPY_ENC(M2_cmpyrs_s1, "1101","ddddd","1","1","0","1","10") +MPY_ENC(M2_cmpyrsc_s0, "1101","ddddd","1","1","1","0","10") +MPY_ENC(M2_cmpyrsc_s1, "1101","ddddd","1","1","1","1","10") +MPY_ENC(M2_vmpy2s_s0pack, "1101","ddddd","1","1","0","0","11") +MPY_ENC(M2_vmpy2s_s1pack, "1101","ddddd","1","1","0","1","11") +MPY_ENC(M2_hmmpyh_rs1, "1101","ddddd","1","1","0","1","00") +MPY_ENC(M2_hmmpyl_rs1, "1101","ddddd","1","1","1","1","00") + +MPY_ENC(M2_hmmpyh_s1, "1101","ddddd","0","1","0","1","00") +MPY_ENC(M2_hmmpyl_s1, "1101","ddddd","0","1","0","1","01") +MPY_ENC(M2_mpy_up_s1, "1101","ddddd","0","1","0","1","10") +MPY_ENC(M2_mpy_up_s1_sat, "1101","ddddd","0","1","1","1","00") +MPY_ENC(M2_mpysu_up, "1101","ddddd","0","1","1","0","01") + + +DEF_FIELDROW_DESC32(ICLASS_M" 1110 -------- PP------ --------","[#14] Rx=(Rs,Rt)") +DEF_FIELD32(ICLASS_M" 1110 -------- PP------ --!-----",Md_tH,"Rt is High") /*Rt high */ +DEF_FIELD32(ICLASS_M" 1110 -------- PP------ -!------",Md_sH,"Rs is High") /* Rs high */ +SP_MPY(M2_mpyu_acc, "1110","xxxxx","0","0","1") +SP_MPY(M2_mpy_acc, "1110","xxxxx","0","0","0") +SP_MPY(M2_mpy_acc_sat, "1110","xxxxx","1","0","0") +SP_MPY(M2_mpyu_nac, "1110","xxxxx","0","1","1") +SP_MPY(M2_mpy_nac, "1110","xxxxx","0","1","0") +SP_MPY(M2_mpy_nac_sat, "1110","xxxxx","1","1","0") + + +DEF_FIELDROW_DESC32(ICLASS_M" 1111 -------- PP------ --------","[#15] Rx=(Rs,Rt)") +MPY_ENC(M2_maci, "1111","xxxxx","0","0","0","0","00") +MPY_ENC(M2_mnaci, "1111","xxxxx","0","0","0","1","00") +MPY_ENC(M2_acci, "1111","xxxxx","0","0","0","0","01") +MPY_ENC(M2_nacci, "1111","xxxxx","0","0","0","1","01") +MPY_ENC(M2_xor_xacc, "1111","xxxxx","0","0","0","1","11") +MPY_ENC(M2_subacc, "1111","xxxxx","0","0","0","0","11") + +MPY_ENC(M4_mac_up_s1_sat, "1111","xxxxx","0","1","1","0","00") +MPY_ENC(M4_nac_up_s1_sat, "1111","xxxxx","0","1","1","0","01") + +MPY_ENC(M4_and_and, "1111","xxxxx","0","0","1","0","00") +MPY_ENC(M4_and_or, "1111","xxxxx","0","0","1","0","01") +MPY_ENC(M4_and_xor, "1111","xxxxx","0","0","1","0","10") +MPY_ENC(M4_or_and, "1111","xxxxx","0","0","1","0","11") +MPY_ENC(M4_or_or, "1111","xxxxx","0","0","1","1","00") +MPY_ENC(M4_or_xor, "1111","xxxxx","0","0","1","1","01") +MPY_ENC(M4_xor_and, "1111","xxxxx","0","0","1","1","10") +MPY_ENC(M4_xor_or, "1111","xxxxx","0","0","1","1","11") + +MPY_ENC(M4_or_andn, "1111","xxxxx","0","1","0","0","00") +MPY_ENC(M4_and_andn, "1111","xxxxx","0","1","0","0","01") +MPY_ENC(M4_xor_andn, "1111","xxxxx","0","1","0","0","10") + +MPY_ENC(F2_sffma, "1111","xxxxx","1","0","0","0","00") +MPY_ENC(F2_sffms, "1111","xxxxx","1","0","0","0","01") + +MPY_ENC(F2_sffma_lib, "1111","xxxxx","1","0","0","0","10") +MPY_ENC(F2_sffms_lib, "1111","xxxxx","1","0","0","0","11") + +MPY_ENC(F2_sffma_sc, "1111","xxxxx","1","1","1","0","uu") + + +/*******************************/ +/* */ +/* */ +/* ALU32_2op */ +/* */ +/* */ +/*******************************/ +DEF_CLASS32(ICLASS_ADDI" ---- -------- PP------ --------",ALU32_ADDI) + +DEF_CLASS32(ICLASS_ALU2op" ---- -------- PP------ --------",ALU32_2op) +DEF_FIELD32(ICLASS_ALU2op" !--- -------- PP------ --------",A2_Rs,"No Rs read") +DEF_FIELD32(ICLASS_ALU2op" -!!! -------- PP------ --------",A2_MajOp,"Major Opcode") +DEF_FIELD32(ICLASS_ALU2op" ---- !!!----- PP------ --------",A2_MinOp,"Minor Opcode") + +DEF_FIELD32(ICLASS_ALU3op" -!!! -------- PP------ --------",A3_MajOp,"Major Opcode") +DEF_FIELD32(ICLASS_ALU3op" ---- !!!----- PP------ --------",A3_MinOp,"Minor Opcode") +DEF_CLASS32(ICLASS_ALU3op" ---- -------- PP------ --------",ALU32_3op) +DEF_FIELD32(ICLASS_ALU3op" !--- -------- PP------ --------",A3_P,"Predicated") +DEF_FIELD32(ICLASS_ALU3op" ---- -------- PP!----- --------",A3_DN,"Dot-new") +DEF_FIELD32(ICLASS_ALU3op" ---- -------- PP------ !-------",A3_PS,"Predicate sense") + + +/*************************/ +/* Our good friend addi */ +/*************************/ +DEF_ENC32(A2_addi, ICLASS_ADDI" iiii iiisssss PPiiiiii iiiddddd") + + +/*******************************/ +/* Standard ALU32 insns */ +/*******************************/ + +#define ALU32_IRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"iiiii "VMIN3 DSTCHARS) + +#define ALU32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) + +#define CONDA32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG##t, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-00uu "VMIN3 DSTCHARS)\ +DEF_ENC32(TAG##f, ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-10uu "VMIN3 DSTCHARS)\ +DEF_ENC32(TAG##tnew,ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-01uu "VMIN3 DSTCHARS)\ +DEF_ENC32(TAG##fnew,ICLASS_ALU2op" "MAJ4" "MIN3"sssss PP"SMOD1"-11uu "VMIN3 DSTCHARS) + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0000 -------- PP------ --------","[#0] (Pu) Rd=(Rs)") +DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP!----- --------",A32a_C,"Conditional") +DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP--!--- --------",A32a_S,"Predicate sense") +DEF_FIELD32( ICLASS_ALU2op" 0000 -------- PP---!-- --------",A32a_dn,"Dot-new") + +ALU32_RR_ENC(A2_aslh, "0000","000","0","---","ddddd") +ALU32_RR_ENC(A2_asrh, "0000","001","0","---","ddddd") +ALU32_RR_ENC(A2_tfr, "0000","011","0","---","ddddd") +ALU32_RR_ENC(A2_sxtb, "0000","101","0","---","ddddd") +ALU32_RR_ENC(A2_zxth, "0000","110","0","---","ddddd") +ALU32_RR_ENC(A2_sxth, "0000","111","0","---","ddddd") + +CONDA32_RR_ENC(A4_paslh, "0000","000","1","---","ddddd") +CONDA32_RR_ENC(A4_pasrh, "0000","001","1","---","ddddd") +CONDA32_RR_ENC(A4_pzxtb, "0000","100","1","---","ddddd") +CONDA32_RR_ENC(A4_psxtb, "0000","101","1","---","ddddd") +CONDA32_RR_ENC(A4_pzxth, "0000","110","1","---","ddddd") +CONDA32_RR_ENC(A4_psxth, "0000","111","1","---","ddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0001 -------- PP------ --------","[#1] Rx=(#u16)") +DEF_ENC32(A2_tfril, ICLASS_ALU2op" 0001 ii1xxxxx PPiiiiii iiiiiiii") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0010 -------- PP------ --------","[#2] Rx=(#u16)") +DEF_ENC32(A2_tfrih, ICLASS_ALU2op" 0010 ii1xxxxx PPiiiiii iiiiiiii") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0011 -------- PP------ --------","[#3] Rd=(Pu,Rs,#s8)") +DEF_ENC32(C2_muxir, ICLASS_ALU2op" 0011 0uusssss PP0iiiii iiiddddd") +DEF_ENC32(C2_muxri, ICLASS_ALU2op" 0011 1uusssss PP0iiiii iiiddddd") + +DEF_ENC32(A4_combineri, ICLASS_ALU2op" 0011 -00sssss PP1iiiii iiiddddd") /* Rdd = (Rs,#s8) */ +DEF_ENC32(A4_combineir, ICLASS_ALU2op" 0011 -01sssss PP1iiiii iiiddddd") /* Rdd = (Rs,#s8) */ +DEF_ENC32(A4_rcmpeqi, ICLASS_ALU2op" 0011 -10sssss PP1iiiii iiiddddd") /* Rd = (Rs,#s8) */ +DEF_ENC32(A4_rcmpneqi, ICLASS_ALU2op" 0011 -11sssss PP1iiiii iiiddddd") /* Rd = (Rs,#s8) */ + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0100 -------- PP------ --------","[#4] (Pu) Rd=(Rs,#s8)") +DEF_FIELD32( ICLASS_ALU2op" 0100 -------- PP!----- --------",A32a_DN,"Dot-new") +DEF_FIELD32( ICLASS_ALU2op" 0100 !------- PP------ --------",A32a_PS,"Predicate sense") +DEF_ENC32(A2_paddit, ICLASS_ALU2op" 0100 0uusssss PP0iiiii iiiddddd") +DEF_ENC32(A2_padditnew, ICLASS_ALU2op" 0100 0uusssss PP1iiiii iiiddddd") +DEF_ENC32(A2_paddif, ICLASS_ALU2op" 0100 1uusssss PP0iiiii iiiddddd") +DEF_ENC32(A2_paddifnew, ICLASS_ALU2op" 0100 1uusssss PP1iiiii iiiddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0101 -------- PP------ --------","[#5] Pd=(Rs,#s10)") +DEF_ENC32(C2_cmpeqi, ICLASS_ALU2op" 0101 00isssss PPiiiiii iii000dd") +DEF_ENC32(C2_cmpgti, ICLASS_ALU2op" 0101 01isssss PPiiiiii iii000dd") +DEF_ENC32(C2_cmpgtui, ICLASS_ALU2op" 0101 100sssss PPiiiiii iii000dd") + +DEF_ENC32(C4_cmpneqi, ICLASS_ALU2op" 0101 00isssss PPiiiiii iii100dd") +DEF_ENC32(C4_cmpltei, ICLASS_ALU2op" 0101 01isssss PPiiiiii iii100dd") +DEF_ENC32(C4_cmplteui, ICLASS_ALU2op" 0101 100sssss PPiiiiii iii100dd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0110 -------- PP------ --------","[#6] Rd=(Rs,#s10)") +ALU32_IRR_ENC(A2_andir, "0110","00i","i","iii","ddddd") +ALU32_IRR_ENC(A2_subri, "0110","01i","i","iii","ddddd") +ALU32_IRR_ENC(A2_orir, "0110","10i","i","iii","ddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 0111 -------- PP------ --------","[#7] Reserved") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1000 -------- PP------ --------","[#8] Rd=#s16") +DEF_ENC32(A2_tfrsi, ICLASS_ALU2op" 1000 ii-iiiii PPiiiiii iiiddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1001 -------- PP------ --------","[#9] Reserved") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 101- -------- PP------ --------","[#10,#11] Rd=(Pu,#s8,#S8)") +DEF_ENC32(C2_muxii, ICLASS_ALU2op" 101u uIIIIIII PPIiiiii iiiddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1100 -------- PP------ --------","[#12] Rdd=(#s8,#S8)") +DEF_ENC32(A2_combineii, ICLASS_ALU2op" 1100 0IIIIIII PPIiiiii iiiddddd") +DEF_ENC32(A4_combineii, ICLASS_ALU2op" 1100 1--IIIII PPIiiiii iiiddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1101 -------- PP------ --------","[#13] Reserved") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1110 -------- PP------ --------","[#14] (Pu) Rd=#s12") +DEF_FIELD32( ICLASS_ALU2op" 1110 ---0---- PP!----- --------",A32c_DN,"Dot-new") +DEF_FIELD32( ICLASS_ALU2op" 1110 !--0---- PP------ --------",A32c_PS,"Predicate sense") +DEF_ENC32(C2_cmovenewit,ICLASS_ALU2op" 1110 0uu0iiii PP1iiiii iiiddddd") +DEF_ENC32(C2_cmovenewif,ICLASS_ALU2op" 1110 1uu0iiii PP1iiiii iiiddddd") +DEF_ENC32(C2_cmoveit, ICLASS_ALU2op" 1110 0uu0iiii PP0iiiii iiiddddd") +DEF_ENC32(C2_cmoveif, ICLASS_ALU2op" 1110 1uu0iiii PP0iiiii iiiddddd") + + +DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1111 -------- PP------ --------","[#15] nop") +DEF_ENC32(A2_nop, ICLASS_ALU2op" 1111 -------- PP------ --------") + + + + + + + + + + + + +/*******************************/ +/* */ +/* */ +/* ALU32_3op */ +/* */ +/* */ +/*******************************/ + + +#define V2A32_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG, ICLASS_ALU3op" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) + +#define V2A32_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG, ICLASS_ALU3op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0000 -------- PP------ --------","[#0] Reserved") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0001 -------- PP------ --------","[#1] Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_and, "0001","000","-","---","ddddd") +V2A32_RRR_ENC(A2_or, "0001","001","-","---","ddddd") +V2A32_RRR_ENC(A2_xor, "0001","011","-","---","ddddd") +V2A32_RRR_ENC(A4_andn, "0001","100","-","---","ddddd") +V2A32_RRR_ENC(A4_orn, "0001","101","-","---","ddddd") + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0010 -------- PP------ --------","[#2] Pd=(Rs,Rt)") +V2A32_RRR_ENC(C2_cmpeq, "0010","-00","-","---","000dd") +V2A32_RRR_ENC(C2_cmpgt, "0010","-10","-","---","000dd") +V2A32_RRR_ENC(C2_cmpgtu, "0010","-11","-","---","000dd") + +V2A32_RRR_ENC(C4_cmpneq, "0010","-00","-","---","100dd") +V2A32_RRR_ENC(C4_cmplte, "0010","-10","-","---","100dd") +V2A32_RRR_ENC(C4_cmplteu, "0010","-11","-","---","100dd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0011 -------- PP------ --------","[#3] Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_add, "0011","000","-","---","ddddd") +V2A32_RRR_ENC(A2_sub, "0011","001","-","---","ddddd") +V2A32_RRR_ENC(A2_combine_hh, "0011","100","-","---","ddddd") +V2A32_RRR_ENC(A2_combine_hl, "0011","101","-","---","ddddd") +V2A32_RRR_ENC(A2_combine_lh, "0011","110","-","---","ddddd") +V2A32_RRR_ENC(A2_combine_ll, "0011","111","-","---","ddddd") +V2A32_RRR_ENC(A4_rcmpeq, "0011","010","-","---","ddddd") +V2A32_RRR_ENC(A4_rcmpneq, "0011","011","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0100 -------- PP------ --------","[#4] Rd=(Pu,Rs,Rt)") +V2A32_RRR_ENC(C2_mux, "0100","---","-","-uu","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0101 -------- PP------ --------","[#5] Rdd=(Rs,Rt)") +V2A32_RRR_ENC(A2_combinew, "0101","0--","-","---","ddddd") +V2A32_RRR_ENC(S2_packhl, "0101","1--","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0110 -------- PP------ --------","[#6] Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_svaddh, "0110","000","-","---","ddddd") +V2A32_RRR_ENC(A2_svaddhs, "0110","001","-","---","ddddd") +V2A32_RRR_ENC(A2_svadduhs, "0110","011","-","---","ddddd") +V2A32_RRR_ENC(A2_svsubh, "0110","100","-","---","ddddd") +V2A32_RRR_ENC(A2_svsubhs, "0110","101","-","---","ddddd") +V2A32_RRR_ENC(A2_svsubuhs, "0110","111","-","---","ddddd") +V2A32_RRR_ENC(A2_addsat, "0110","010","-","---","ddddd") +V2A32_RRR_ENC(A2_subsat, "0110","110","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 0111 -------- PP------ --------","[#7] Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_svavgh, "0111","-00","-","---","ddddd") +V2A32_RRR_ENC(A2_svavghs, "0111","-01","-","---","ddddd") +V2A32_RRR_ENC(A2_svnavgh, "0111","-11","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1000 -------- PP------ --------","[#8] Reserved") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1001 -------- PP------ --------","[#9] (Pu) Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_pandt, "1001","-00","0","0uu","ddddd") +V2A32_RRR_ENC(A2_pandtnew, "1001","-00","1","0uu","ddddd") +V2A32_RRR_ENC(A2_pandf, "1001","-00","0","1uu","ddddd") +V2A32_RRR_ENC(A2_pandfnew, "1001","-00","1","1uu","ddddd") +V2A32_RRR_ENC(A2_port, "1001","-01","0","0uu","ddddd") +V2A32_RRR_ENC(A2_portnew, "1001","-01","1","0uu","ddddd") +V2A32_RRR_ENC(A2_porf, "1001","-01","0","1uu","ddddd") +V2A32_RRR_ENC(A2_porfnew, "1001","-01","1","1uu","ddddd") +V2A32_RRR_ENC(A2_pxort, "1001","-11","0","0uu","ddddd") +V2A32_RRR_ENC(A2_pxortnew, "1001","-11","1","0uu","ddddd") +V2A32_RRR_ENC(A2_pxorf, "1001","-11","0","1uu","ddddd") +V2A32_RRR_ENC(A2_pxorfnew, "1001","-11","1","1uu","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1010 -------- PP------ --------","[#10] Reserved") + + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1011 -------- PP------ --------","[#11] (Pu) Rd=(Rs,Rt)") +V2A32_RRR_ENC(A2_paddt, "1011","0-0","0","0uu","ddddd") +V2A32_RRR_ENC(A2_paddtnew, "1011","0-0","1","0uu","ddddd") +V2A32_RRR_ENC(A2_paddf, "1011","0-0","0","1uu","ddddd") +V2A32_RRR_ENC(A2_paddfnew, "1011","0-0","1","1uu","ddddd") +V2A32_RRR_ENC(A2_psubt, "1011","0-1","0","0uu","ddddd") +V2A32_RRR_ENC(A2_psubtnew, "1011","0-1","1","0uu","ddddd") +V2A32_RRR_ENC(A2_psubf, "1011","0-1","0","1uu","ddddd") +V2A32_RRR_ENC(A2_psubfnew, "1011","0-1","1","1uu","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1100 -------- PP------ --------","[#12] Reserved") + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1101 -------- PP------ --------","[#13] (Pu) Rdd=(Rs,Rt)") +V2A32_RRR_ENC(C2_ccombinewnewt, "1101","000","1","0uu","ddddd") +V2A32_RRR_ENC(C2_ccombinewnewf, "1101","000","1","1uu","ddddd") +V2A32_RRR_ENC(C2_ccombinewt, "1101","000","0","0uu","ddddd") +V2A32_RRR_ENC(C2_ccombinewf, "1101","000","0","1uu","ddddd") + + + + + + +DEF_FIELDROW_DESC32(ICLASS_ALU3op" 1110 -------- PP------ --------","[#14] Reserved") + + + + + + + + + +/*******************************/ +/* */ +/* */ +/* S */ +/* */ +/* */ +/*******************************/ + +DEF_CLASS32(ICLASS_S2op" ---- -------- PP------ --------",S_2op) +DEF_FIELD32(ICLASS_S2op" !!!! -------- PP------ --------",STYPEB_RegType,"Register Type") +DEF_FIELD32(ICLASS_S2op" ---- !!------ PP------ --------",S2_MajOp,"Major Opcode") +DEF_FIELD32(ICLASS_S2op" ---- -------- PP------ !!!-----",S2_MinOp,"Minor Opcode") + +DEF_CLASS32(ICLASS_S3op" ---- -------- PP------ --------",S_3op) +DEF_FIELD32(ICLASS_S3op" !!!! -------- PP------ --------",STYPEA_RegType,"Register Type") +DEF_FIELD32(ICLASS_S3op" ---- !!------ PP------ --------",S3_Maj,"Major Opcode") +DEF_FIELD32(ICLASS_S3op" ---- -------- PP------ !!------",S3_Min,"Minor Opcode") + + +#define SH_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) + +#define SH_RRRiENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"iiiii PP"SMOD1"ttttt "VMIN3 DSTCHARS) + +#define SH_RRR_ENCX(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"xxxxx "VMIN3 DSTCHARS) + +#define SH3_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) + +#define SH_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S3op" "MAJ4" "MIN3"---ss PP"SMOD1"---tt "VMIN3 DSTCHARS) + +#define SH2_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3"sssss PP"SMOD1"----- "VMIN3 DSTCHARS) + +#define SH2_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3"---ss PP"SMOD1"---tt "VMIN3 DSTCHARS) + +#define SH_RRI4_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PP00iiii " VMIN3 DSTCHARS) + +#define SH_RRI5_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PP0iiiii " VMIN3 DSTCHARS) + +#define SH_RRI6_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \ +DEF_ENC32(TAG,ICLASS_S2op" "MAJ4" "MIN3 "sssss PPiiiiii " VMIN3 DSTCHARS) + +#define RSHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DMOD1,DSTCHARS) \ +SH_RRR_ENC(S2_asr_r_##TAGEND,MAJ4,MIN3,SMOD1,"00"DMOD1,DSTCHARS) \ +SH_RRR_ENC(S2_lsr_r_##TAGEND,MAJ4,MIN3,SMOD1,"01"DMOD1,DSTCHARS) \ +SH_RRR_ENC(S2_asl_r_##TAGEND,MAJ4,MIN3,SMOD1,"10"DMOD1,DSTCHARS) \ +SH_RRR_ENC(S2_lsl_r_##TAGEND,MAJ4,MIN3,SMOD1,"11"DMOD1,DSTCHARS) + + +#define I5SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI5_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ +SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ +SH_RRI5_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) + +#define I5SHIFTTYPES_NOROL(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI5_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ +SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) + +#define I5SHIFTTYPES_NOASR(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI5_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ +SH_RRI5_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) + +#define I4SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI4_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ +SH_RRI4_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI4_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) + +#define I5ASHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI5_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) + +#define I4ASHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI4_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) + +#define I6SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI6_ENC(S2_asr_i_##TAGEND,MAJ4,MIN3,SMOD1 "00",DSTCHARS) \ +SH_RRI6_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI6_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ +SH_RRI6_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) \ + +#define I6SHIFTTYPES_NOASR(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \ +SH_RRI6_ENC(S2_lsr_i_##TAGEND,MAJ4,MIN3,SMOD1 "01",DSTCHARS) \ +SH_RRI6_ENC(S2_asl_i_##TAGEND,MAJ4,MIN3,SMOD1 "10",DSTCHARS) \ +SH_RRI6_ENC(S6_rol_i_##TAGEND,MAJ4,MIN3,SMOD1 "11",DSTCHARS) + + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0000 -------- PP------ --------","[#0] Rdd=(Rss,#u6)") +/* EJP: there is actually quite a bit of space here, look at the reserved bits */ +I6SHIFTTYPES(p, "0000","000","0","ddddd") +I5SHIFTTYPES_NOROL(vw, "0000","010","0","ddddd") +I4SHIFTTYPES(vh, "0000","100","0","ddddd") + + + +/* False assume an immediate */ +SH2_RR_ENC(S2_vsathub_nopack, "0000","000","-","1 00","ddddd") +SH2_RR_ENC(S2_vsatwuh_nopack, "0000","000","-","1 01","ddddd") +SH2_RR_ENC(S2_vsatwh_nopack, "0000","000","-","1 10","ddddd") +SH2_RR_ENC(S2_vsathb_nopack, "0000","000","-","1 11","ddddd") + +SH_RRI4_ENC(S5_vasrhrnd, "0000","001", "0 00","ddddd") + +SH2_RR_ENC(A2_vabsh, "0000","010","-","1 00","ddddd") +SH2_RR_ENC(A2_vabshsat, "0000","010","-","1 01","ddddd") +SH2_RR_ENC(A2_vabsw, "0000","010","-","1 10","ddddd") +SH2_RR_ENC(A2_vabswsat, "0000","010","-","1 11","ddddd") + +SH2_RR_ENC(A2_notp, "0000","100","-","1 00","ddddd") +SH2_RR_ENC(A2_negp, "0000","100","-","1 01","ddddd") +SH2_RR_ENC(A2_absp, "0000","100","-","1 10","ddddd") +SH2_RR_ENC(A2_vconj, "0000","100","-","1 11","ddddd") + +SH2_RR_ENC(S2_deinterleave, "0000","110","-","1 00","ddddd") +SH2_RR_ENC(S2_interleave, "0000","110","-","1 01","ddddd") +SH2_RR_ENC(S2_brevp, "0000","110","-","1 10","ddddd") +SH_RRI6_ENC(S2_asr_i_p_rnd, "0000","110", "1 11","ddddd") + +SH2_RR_ENC(F2_conv_df2d, "0000","111","0","0 00","ddddd") +SH2_RR_ENC(F2_conv_df2ud, "0000","111","0","0 01","ddddd") +SH2_RR_ENC(F2_conv_ud2df, "0000","111","0","0 10","ddddd") +SH2_RR_ENC(F2_conv_d2df, "0000","111","0","0 11","ddddd") +#ifdef ADD_DP_OPS +SH2_RR_ENC(F2_dffixupr, "0000","111","0","1 00","ddddd") +SH2_RR_ENC(F2_dfsqrtcheat, "0000","111","0","1 01","ddddd") +#endif +SH2_RR_ENC(F2_conv_df2d_chop, "0000","111","0","1 10","ddddd") +SH2_RR_ENC(F2_conv_df2ud_chop,"0000","111","0","1 11","ddddd") +#ifdef ADD_DP_OPS +SH2_RR_ENC(F2_dfinvsqrta, "0000","111","1","0 ee","ddddd") +#endif + + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0001 -------- PP------ --------","[#1] Rdd=(Rss,#u6,#U6)") +DEF_ENC32(S2_extractup,ICLASS_S2op" 0001 IIIsssss PPiiiiii IIIddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0010 -------- PP------ --------","[#2] Rxx=(Rss,#u6)") +I6SHIFTTYPES(p_nac, "0010","00-","0","xxxxx") +I6SHIFTTYPES(p_acc, "0010","00-","1","xxxxx") +I6SHIFTTYPES(p_and, "0010","01-","0","xxxxx") +I6SHIFTTYPES(p_or, "0010","01-","1","xxxxx") +I6SHIFTTYPES_NOASR(p_xacc, "0010","10-","0","xxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0011 -------- PP------ --------","[#3] Rxx=(Rss,#u6,#U6)") +DEF_ENC32(S2_insertp,ICLASS_S2op" 0011 IIIsssss PPiiiiii IIIxxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0100 -------- PP------ --------","[#4] Rdd=(Rs)") +SH2_RR_ENC(S2_vsxtbh, "0100","00-","-","00-","ddddd") +SH2_RR_ENC(S2_vzxtbh, "0100","00-","-","01-","ddddd") +SH2_RR_ENC(S2_vsxthw, "0100","00-","-","10-","ddddd") +SH2_RR_ENC(S2_vzxthw, "0100","00-","-","11-","ddddd") +SH2_RR_ENC(A2_sxtw, "0100","01-","-","00-","ddddd") +SH2_RR_ENC(S2_vsplatrh, "0100","01-","-","01-","ddddd") +SH2_RR_ENC(S6_vsplatrbp, "0100","01-","-","10-","ddddd") + +SH2_RR_ENC(F2_conv_sf2df, "0100","1--","-","000","ddddd") +SH2_RR_ENC(F2_conv_uw2df, "0100","1--","-","001","ddddd") +SH2_RR_ENC(F2_conv_w2df, "0100","1--","-","010","ddddd") +SH2_RR_ENC(F2_conv_sf2ud, "0100","1--","-","011","ddddd") +SH2_RR_ENC(F2_conv_sf2d, "0100","1--","-","100","ddddd") +SH2_RR_ENC(F2_conv_sf2ud_chop, "0100","1--","-","101","ddddd") +SH2_RR_ENC(F2_conv_sf2d_chop, "0100","1--","-","110","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0101 -------- PP------ --------","[#5] Pd=(Rs,#u6)") +DEF_ENC32(S2_tstbit_i,ICLASS_S2op" 0101 000sssss PP0iiiii ------dd") +DEF_ENC32(C2_tfrrp, ICLASS_S2op" 0101 010sssss PP------ ------dd") +DEF_ENC32(C2_bitsclri,ICLASS_S2op" 0101 100sssss PPiiiiii ------dd") +DEF_ENC32(S4_ntstbit_i,ICLASS_S2op"0101 001sssss PP0iiiii ------dd") +DEF_ENC32(C4_nbitsclri,ICLASS_S2op"0101 101sssss PPiiiiii ------dd") +DEF_ENC32(F2_sfclass, ICLASS_S2op"0101 111sssss PP0iiiii ------dd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0110 -------- PP------ --------","[#6] Rdd=(Pt)") +DEF_ENC32(C2_mask, ICLASS_S2op" 0110 --- ----- PP----tt --- ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 0111 -------- PP------ --------","[#7] Rx=(Rs,#u4,#S6)") +DEF_ENC32(S2_tableidxb,ICLASS_S2op" 0111 00isssss PPIIIIII iiixxxxx") +DEF_ENC32(S2_tableidxh,ICLASS_S2op" 0111 01isssss PPIIIIII iiixxxxx") +DEF_ENC32(S2_tableidxw,ICLASS_S2op" 0111 10isssss PPIIIIII iiixxxxx") +DEF_ENC32(S2_tableidxd,ICLASS_S2op" 0111 11isssss PPIIIIII iiixxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1000 -------- PP------ --------","[#8] Rd=(Rss,#u6)") +SH2_RR_ENC(S2_vsathub, "1000","000","-","000","ddddd") +SH2_RR_ENC(S2_vsatwh, "1000","000","-","010","ddddd") +SH2_RR_ENC(S2_vsatwuh, "1000","000","-","100","ddddd") +SH2_RR_ENC(S2_vsathb, "1000","000","-","110","ddddd") +SH2_RR_ENC(S2_clbp, "1000","010","-","000","ddddd") +SH2_RR_ENC(S2_cl0p, "1000","010","-","010","ddddd") +SH2_RR_ENC(S2_cl1p, "1000","010","-","100","ddddd") +SH2_RR_ENC(S2_ct0p, "1000","111","-","010","ddddd") +SH2_RR_ENC(S2_ct1p, "1000","111","-","100","ddddd") +SH2_RR_ENC(S2_vtrunohb, "1000","100","-","000","ddddd") +SH2_RR_ENC(S2_vtrunehb, "1000","100","-","010","ddddd") +SH2_RR_ENC(S2_vrndpackwh, "1000","100","-","100","ddddd") +SH2_RR_ENC(S2_vrndpackwhs, "1000","100","-","110","ddddd") +SH2_RR_ENC(A2_sat, "1000","110","-","000","ddddd") +SH2_RR_ENC(A2_roundsat, "1000","110","-","001","ddddd") +SH_RRI5_ENC(S2_asr_i_svw_trun, "1000","110", "010","ddddd") +SH_RRI5_ENC(A4_bitspliti, "1000","110", "100","ddddd") + +SH_RRI5_ENC(A7_clip, "1000","110", "101","ddddd") +SH_RRI5_ENC(A7_vclip, "1000","110", "110","ddddd") + + +SH2_RR_ENC(S4_clbpnorm, "1000","011","-","000","ddddd") +SH_RRI6_ENC(S4_clbpaddi, "1000","011", "010","ddddd") +SH2_RR_ENC(S5_popcountp, "1000","011","-","011","ddddd") + +SH_RRI4_ENC(S5_asrhub_rnd_sat, "1000","011", "100","ddddd") +SH_RRI4_ENC(S5_asrhub_sat, "1000","011", "101","ddddd") + +SH2_RR_ENC(F2_conv_df2sf, "1000","000","-","001","ddddd") +SH2_RR_ENC(F2_conv_ud2sf, "1000","001","-","001","ddddd") +SH2_RR_ENC(F2_conv_d2sf, "1000","010","-","001","ddddd") +SH2_RR_ENC(F2_conv_df2uw, "1000","011","-","001","ddddd") +SH2_RR_ENC(F2_conv_df2w, "1000","100","-","001","ddddd") +SH2_RR_ENC(F2_conv_df2uw_chop, "1000","101","-","001","ddddd") +SH2_RR_ENC(F2_conv_df2w_chop, "1000","111","-","001","ddddd") + + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1001 -------- PP------ --------","[#9] Rd=(Ps,Pt)") +DEF_ENC32(C2_vitpack, ICLASS_S2op" 1001 -00 ---ss PP----tt --- ddddd") +DEF_ENC32(C2_tfrpr, ICLASS_S2op" 1001 -1- ---ss PP------ --- ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1010 -------- PP------ --------","[#10] Rdd=(Rss,#u6,#U6)") +DEF_ENC32(S4_extractp,ICLASS_S2op" 1010 IIIsssss PPiiiiii IIIddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1011 -------- PP------ --------","[#11] Rd=(Rs)") +SH2_RR_ENC(F2_conv_uw2sf, "1011","001","-","000","ddddd") +SH2_RR_ENC(F2_conv_w2sf, "1011","010","-","000","ddddd") +SH2_RR_ENC(F2_conv_sf2uw, "1011","011","-","000","ddddd") +SH2_RR_ENC(F2_conv_sf2w, "1011","100","-","000","ddddd") +SH2_RR_ENC(F2_conv_sf2uw_chop, "1011","011","-","001","ddddd") +SH2_RR_ENC(F2_conv_sf2w_chop, "1011","100","-","001","ddddd") +SH2_RR_ENC(F2_sffixupr, "1011","101","-","000","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1100 -------- PP------ --------","[#12] Rd=(Rs,#u6)") +I5SHIFTTYPES(r, "1100","000", "0 ","ddddd") +SH_RRI5_ENC(S2_asl_i_r_sat, "1100","010", "010","ddddd") +SH_RRI5_ENC(S2_asr_i_r_rnd, "1100","010", "000","ddddd") + +SH2_RR_ENC(S2_svsathb, "1100","10-","-", "00-","ddddd") +SH2_RR_ENC(S2_svsathub, "1100","10-","-", "01-","ddddd") + +SH_RRI5_ENC(A4_cround_ri, "1100","111", "00-","ddddd") +SH_RRI6_ENC(A7_croundd_ri, "1100","111", "01-","ddddd") +SH_RRI5_ENC(A4_round_ri, "1100","111", "10-","ddddd") +SH_RRI5_ENC(A4_round_ri_sat, "1100","111", "11-","ddddd") + +DEF_ENC32(S2_setbit_i, ICLASS_S2op" 1100 110sssss PP0iiiii 000ddddd") +DEF_ENC32(S2_clrbit_i, ICLASS_S2op" 1100 110sssss PP0iiiii 001ddddd") +DEF_ENC32(S2_togglebit_i,ICLASS_S2op" 1100 110sssss PP0iiiii 010ddddd") +DEF_ENC32(S4_lsli ,ICLASS_S2op" 1100 110sssss PPiiiiii 011ddddd") + +DEF_ENC32(S4_clbaddi ,ICLASS_S2op" 1100 001sssss PPiiiiii 000ddddd") + + + +/* False read #u6 */ +SH2_RR_ENC(S2_clb, "1100","000","-","1 00","ddddd") +SH2_RR_ENC(S2_cl0, "1100","000","-","1 01","ddddd") +SH2_RR_ENC(S2_cl1, "1100","000","-","1 10","ddddd") +SH2_RR_ENC(S2_clbnorm, "1100","000","-","1 11","ddddd") +SH2_RR_ENC(S2_ct0, "1100","010","-","1 00","ddddd") +SH2_RR_ENC(S2_ct1, "1100","010","-","1 01","ddddd") +SH2_RR_ENC(S2_brev, "1100","010","-","1 10","ddddd") +SH2_RR_ENC(S2_vsplatrb, "1100","010","-","1 11","ddddd") +SH2_RR_ENC(A2_abs, "1100","100","-","1 00","ddddd") +SH2_RR_ENC(A2_abssat, "1100","100","-","1 01","ddddd") +SH2_RR_ENC(A2_negsat, "1100","100","-","1 10","ddddd") +SH2_RR_ENC(A2_swiz, "1100","100","-","1 11","ddddd") +SH2_RR_ENC(A2_sath, "1100","110","-","1 00","ddddd") +SH2_RR_ENC(A2_satuh, "1100","110","-","1 01","ddddd") +SH2_RR_ENC(A2_satub, "1100","110","-","1 10","ddddd") +SH2_RR_ENC(A2_satb, "1100","110","-","1 11","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1101 -------- PP------ --------","[#13] Rd=(Rs,#u6,#U6)") +DEF_ENC32(S2_extractu, ICLASS_S2op" 1101 0IIsssss PP0iiiii IIIddddd") +DEF_ENC32(S4_extract, ICLASS_S2op" 1101 1IIsssss PP0iiiii IIIddddd") +DEF_ENC32(S2_mask, ICLASS_S2op" 1101 0II----- PP1iiiii IIIddddd") + + + + + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1110 -------- PP------ --------","[#14] Rx=(Rs,#u6)") +I5SHIFTTYPES(r_nac, "1110","00-","0","xxxxx") +I5SHIFTTYPES(r_acc, "1110","00-","1","xxxxx") +I5SHIFTTYPES(r_and, "1110","01-","0","xxxxx") +I5SHIFTTYPES(r_or, "1110","01-","1","xxxxx") +I5SHIFTTYPES_NOASR(r_xacc,"1110","10-","0","xxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S2op" 1111 -------- PP------ --------","[#15] Rs=(Rs,#u6,#U6)") +DEF_ENC32(S2_insert, ICLASS_S2op" 1111 0IIsssss PP0iiiii IIIxxxxx") + + + + + +/*************************/ +/* S_3_operand */ +/*************************/ + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0000 -------- PP------ --------","[#0] Rdd=(Rss,Rtt,#u3)") +SH_RRR_ENC(S2_valignib, "0000","0--","-","iii","ddddd") +SH_RRR_ENC(S2_vspliceib, "0000","1--","-","iii","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0001 -------- PP------ --------","[#1] Rdd=(Rss,Rtt)") +SH_RRR_ENC(S2_extractup_rp, "0001","00-","-","00-","ddddd") +SH_RRR_ENC(S2_shuffeb, "0001","00-","-","01-","ddddd") +SH_RRR_ENC(S2_shuffob, "0001","00-","-","10-","ddddd") +SH_RRR_ENC(S2_shuffeh, "0001","00-","-","11-","ddddd") + +SH_RRR_ENC(S2_shuffoh, "0001","10-","-","000","ddddd") +SH_RRR_ENC(S2_vtrunewh, "0001","10-","-","010","ddddd") +SH_RRR_ENC(S6_vtrunehb_ppp, "0001","10-","-","011","ddddd") +SH_RRR_ENC(S2_vtrunowh, "0001","10-","-","100","ddddd") +SH_RRR_ENC(S6_vtrunohb_ppp, "0001","10-","-","101","ddddd") +SH_RRR_ENC(S2_lfsp, "0001","10-","-","110","ddddd") + +SH_RRR_ENC(S4_vxaddsubw, "0001","01-","-","000","ddddd") +SH_RRR_ENC(A5_vaddhubs, "0001","01-","-","001","ddddd") +SH_RRR_ENC(S4_vxsubaddw, "0001","01-","-","010","ddddd") +SH_RRR_ENC(S4_vxaddsubh, "0001","01-","-","100","ddddd") +SH_RRR_ENC(S4_vxsubaddh, "0001","01-","-","110","ddddd") + +SH_RRR_ENC(S4_vxaddsubhr, "0001","11-","-","00-","ddddd") +SH_RRR_ENC(S4_vxsubaddhr, "0001","11-","-","01-","ddddd") +SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rdd=(Rss,Rtt,Pu)") +SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") +SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0011 -------- PP------ --------","[#3] Rdd=(Rss,Rt)") +RSHIFTTYPES(vw, "0011","00-","-","-","ddddd") +RSHIFTTYPES(vh, "0011","01-","-","-","ddddd") +RSHIFTTYPES(p, "0011","10-","-","-","ddddd") +SH_RRR_ENC(S2_vcrotate, "0011","11-","-","00-","ddddd") +SH_RRR_ENC(S2_vcnegh, "0011","11-","-","01-","ddddd") +SH_RRR_ENC(S4_vrcrotate, "0011","11-","i","11i","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0100 -------- PP------ --------","[#4] Rd=(Rs,Rt,#u3)") +DEF_ENC32(S2_addasl_rrri, ICLASS_S3op" 0100 000 sssss PP0ttttt iiiddddd") + + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0101 -------- PP------ --------","[#5] Rd=(Rss,Rt)") +SH_RRR_ENC(S2_asr_r_svw_trun, "0101","---","-","010","ddddd") +SH_RRR_ENC(M4_cmpyi_wh, "0101","---","-","100","ddddd") +SH_RRR_ENC(M4_cmpyr_wh, "0101","---","-","110","ddddd") +SH_RRR_ENC(M4_cmpyi_whc, "0101","---","-","101","ddddd") +SH_RRR_ENC(M4_cmpyr_whc, "0101","---","-","111","ddddd") + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0110 -------- PP------ --------","[#6] Rd=(Rs,Rt)") +SH_RRR_ENC(S2_asr_r_r_sat, "0110","00-","-","00-","ddddd") \ +SH_RRR_ENC(S2_asl_r_r_sat, "0110","00-","-","10-","ddddd") + +RSHIFTTYPES(r, "0110","01-","-","-","ddddd") + +SH_RRR_ENC(S2_setbit_r, "0110","10-","-","00-","ddddd") +SH_RRR_ENC(S2_clrbit_r, "0110","10-","-","01-","ddddd") +SH_RRR_ENC(S2_togglebit_r, "0110","10-","-","10-","ddddd") +SH_RRRiENC(S4_lsli, "0110","10-","-","11i","ddddd") + +SH_RRR_ENC(A4_cround_rr, "0110","11-","-","00-","ddddd") +SH_RRR_ENC(A7_croundd_rr, "0110","11-","-","01-","ddddd") +SH_RRR_ENC(A4_round_rr, "0110","11-","-","10-","ddddd") +SH_RRR_ENC(A4_round_rr_sat, "0110","11-","-","11-","ddddd") + + + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 0111 -------- PP------ --------","[#7] Pd=(Rs,Rt)") +SH_RRR_ENC(S2_tstbit_r, "0111","000","-","---","---dd") +SH_RRR_ENC(C2_bitsset, "0111","010","-","---","---dd") +SH_RRR_ENC(C2_bitsclr, "0111","100","-","---","---dd") +SH_RRR_ENC(A4_cmpheq, "0111","110","-","011","---dd") +SH_RRR_ENC(A4_cmphgt, "0111","110","-","100","---dd") +SH_RRR_ENC(A4_cmphgtu, "0111","110","-","101","---dd") +SH_RRR_ENC(A4_cmpbeq, "0111","110","-","110","---dd") +SH_RRR_ENC(A4_cmpbgtu, "0111","110","-","111","---dd") +SH_RRR_ENC(A4_cmpbgt, "0111","110","-","010","---dd") +SH_RRR_ENC(S4_ntstbit_r, "0111","001","-","---","---dd") +SH_RRR_ENC(C4_nbitsset, "0111","011","-","---","---dd") +SH_RRR_ENC(C4_nbitsclr, "0111","101","-","---","---dd") + +SH_RRR_ENC(F2_sfcmpge, "0111","111","-","000","---dd") +SH_RRR_ENC(F2_sfcmpuo, "0111","111","-","001","---dd") +SH_RRR_ENC(F2_sfcmpeq, "0111","111","-","011","---dd") +SH_RRR_ENC(F2_sfcmpgt, "0111","111","-","100","---dd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1000 -------- PP------ --------","[#8] Rx=(Rs,Rtt)") +SH_RRR_ENC(S2_insert_rp, "1000","---","-","---","xxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1001 -------- PP------ --------","[#9] Rd=(Rs,Rtt)") +SH_RRR_ENC(S2_extractu_rp, "1001","00-","-","00-","ddddd") +SH_RRR_ENC(S4_extract_rp, "1001","00-","-","01-","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1010 -------- PP------ --------","[#10] Rxx=(Rss,Rtt)") +SH_RRR_ENC(S2_insertp_rp, "1010","0--","0","---","xxxxx") +SH_RRR_ENC(M4_xor_xacc, "1010","10-","0","000","xxxxx") + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1011 -------- PP------ --------","[#11] Rxx=(Rss,Rt)") +RSHIFTTYPES(p_or, "1011","000","-","-","xxxxx") +RSHIFTTYPES(p_and, "1011","010","-","-","xxxxx") +RSHIFTTYPES(p_nac, "1011","100","-","-","xxxxx") +RSHIFTTYPES(p_acc, "1011","110","-","-","xxxxx") +RSHIFTTYPES(p_xor, "1011","011","-","-","xxxxx") + +SH_RRR_ENCX(A4_vrmaxh, "1011","001","0","001","uuuuu") +SH_RRR_ENCX(A4_vrmaxuh, "1011","001","1","001","uuuuu") +SH_RRR_ENCX(A4_vrmaxw, "1011","001","0","010","uuuuu") +SH_RRR_ENCX(A4_vrmaxuw, "1011","001","1","010","uuuuu") + +SH_RRR_ENCX(A4_vrminh, "1011","001","0","101","uuuuu") +SH_RRR_ENCX(A4_vrminuh, "1011","001","1","101","uuuuu") +SH_RRR_ENCX(A4_vrminw, "1011","001","0","110","uuuuu") +SH_RRR_ENCX(A4_vrminuw, "1011","001","1","110","uuuuu") + +SH_RRR_ENC(S2_vrcnegh, "1011","001","1","111","xxxxx") + +SH_RRR_ENC(S4_vrcrotate_acc, "1011","101","i","--i","xxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1100 -------- PP------ --------","[#12] Rx=(Rs,Rt)") +RSHIFTTYPES(r_or, "1100","00-","-","-","xxxxx") +RSHIFTTYPES(r_and, "1100","01-","-","-","xxxxx") +RSHIFTTYPES(r_nac, "1100","10-","-","-","xxxxx") +RSHIFTTYPES(r_acc, "1100","11-","-","-","xxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1101 -------- PP------ --------","[#13] Reserved") +DEF_FIELDROW_DESC32(ICLASS_S3op" 1110 -------- PP------ --------","[#14] Reserved") + + +DEF_FIELDROW_DESC32(ICLASS_S3op" 1111 -------- PP------ --------","[#14] User Instruction") + + + + + + + + + + + + + +/*******************************/ +/* */ +/* */ +/* ALU64 */ +/* */ +/* */ +/*******************************/ +DEF_CLASS32(ICLASS_ALU64" ---- -------- PP------ --------",ALU64) +DEF_FIELD32(ICLASS_ALU64" !!!! -------- PP------ --------",ALU64_RegType,"Register Type") +DEF_FIELD32(ICLASS_ALU64" 0--- !!!----- PP------ --------",A_MajOp,"Major Opcode") +DEF_FIELD32(ICLASS_ALU64" 0--- -------- PP------ !!!-----",A_MinOp,"Minor Opcode") +DEF_FIELD32(ICLASS_ALU64" 11-- -------- PP------ ---!!!!!",A_MajOp,"Major Opcode") + + + +#define ALU64_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +DEF_ENC32(TAG, ICLASS_ALU64" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) + +#define LEGACY_ALU64_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS)\ +LEGACY_DEF_ENC32(TAG, ICLASS_ALU64" "MAJ4" "MIN3"sssss PP"SMOD1"ttttt "VMIN3 DSTCHARS) + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0000 -------- PP------ --------","[#0] Rd=(Rss,Rtt)") +ALU64_RRR_ENC(S2_parityp, "0000","---","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0001 -------- PP------ --------","[#1] Rdd=(Pu,Rss,Rtt)") +ALU64_RRR_ENC(C2_vmux, "0001","---","-","-uu","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0010 -------- PP------ --------","[#2] Pd=(Rss,Rtt)") +ALU64_RRR_ENC(A2_vcmpweq, "0010","0--","0","000","---dd") +ALU64_RRR_ENC(A2_vcmpwgt, "0010","0--","0","001","---dd") +ALU64_RRR_ENC(A2_vcmpwgtu, "0010","0--","0","010","---dd") +ALU64_RRR_ENC(A2_vcmpheq, "0010","0--","0","011","---dd") +ALU64_RRR_ENC(A2_vcmphgt, "0010","0--","0","100","---dd") +ALU64_RRR_ENC(A2_vcmphgtu, "0010","0--","0","101","---dd") +ALU64_RRR_ENC(A2_vcmpbeq, "0010","0--","0","110","---dd") +ALU64_RRR_ENC(A2_vcmpbgtu, "0010","0--","0","111","---dd") + +ALU64_RRR_ENC(A4_vcmpbeq_any, "0010","0--","1","000","---dd") +ALU64_RRR_ENC(A6_vcmpbeq_notany, "0010","0--","1","001","---dd") +ALU64_RRR_ENC(A4_vcmpbgt, "0010","0--","1","010","---dd") +ALU64_RRR_ENC(A4_tlbmatch, "0010","0--","1","011","---dd") +ALU64_RRR_ENC(A4_boundscheck_lo, "0010","0--","1","100","---dd") +ALU64_RRR_ENC(A4_boundscheck_hi, "0010","0--","1","101","---dd") + +ALU64_RRR_ENC(C2_cmpeqp, "0010","100","-","000","---dd") +ALU64_RRR_ENC(C2_cmpgtp, "0010","100","-","010","---dd") +ALU64_RRR_ENC(C2_cmpgtup, "0010","100","-","100","---dd") + +ALU64_RRR_ENC(F2_dfcmpeq, "0010","111","-","000","---dd") +ALU64_RRR_ENC(F2_dfcmpgt, "0010","111","-","001","---dd") +ALU64_RRR_ENC(F2_dfcmpge, "0010","111","-","010","---dd") +ALU64_RRR_ENC(F2_dfcmpuo, "0010","111","-","011","---dd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0011 -------- PP------ --------","[#3] Rdd=(Rss,Rtt)") +ALU64_RRR_ENC(A2_vaddub, "0011","000","-","000","ddddd") +ALU64_RRR_ENC(A2_vaddubs, "0011","000","-","001","ddddd") +ALU64_RRR_ENC(A2_vaddh, "0011","000","-","010","ddddd") +ALU64_RRR_ENC(A2_vaddhs, "0011","000","-","011","ddddd") +ALU64_RRR_ENC(A2_vadduhs, "0011","000","-","100","ddddd") +ALU64_RRR_ENC(A2_vaddw, "0011","000","-","101","ddddd") +ALU64_RRR_ENC(A2_vaddws, "0011","000","-","110","ddddd") +ALU64_RRR_ENC(A2_addp, "0011","000","-","111","ddddd") + +ALU64_RRR_ENC(A2_vsubub, "0011","001","-","000","ddddd") +ALU64_RRR_ENC(A2_vsububs, "0011","001","-","001","ddddd") +ALU64_RRR_ENC(A2_vsubh, "0011","001","-","010","ddddd") +ALU64_RRR_ENC(A2_vsubhs, "0011","001","-","011","ddddd") +ALU64_RRR_ENC(A2_vsubuhs, "0011","001","-","100","ddddd") +ALU64_RRR_ENC(A2_vsubw, "0011","001","-","101","ddddd") +ALU64_RRR_ENC(A2_vsubws, "0011","001","-","110","ddddd") +ALU64_RRR_ENC(A2_subp, "0011","001","-","111","ddddd") + +ALU64_RRR_ENC(A2_vavgub, "0011","010","-","000","ddddd") +ALU64_RRR_ENC(A2_vavgubr, "0011","010","-","001","ddddd") +ALU64_RRR_ENC(A2_vavgh, "0011","010","-","010","ddddd") +ALU64_RRR_ENC(A2_vavghr, "0011","010","-","011","ddddd") +ALU64_RRR_ENC(A2_vavghcr, "0011","010","-","100","ddddd") +ALU64_RRR_ENC(A2_vavguh, "0011","010","-","101","ddddd") +ALU64_RRR_ENC(A2_vavguhr, "0011","010","-","11-","ddddd") + +ALU64_RRR_ENC(A2_vavgw, "0011","011","-","000","ddddd") +ALU64_RRR_ENC(A2_vavgwr, "0011","011","-","001","ddddd") +ALU64_RRR_ENC(A2_vavgwcr, "0011","011","-","010","ddddd") +ALU64_RRR_ENC(A2_vavguw, "0011","011","-","011","ddddd") +ALU64_RRR_ENC(A2_vavguwr, "0011","011","-","100","ddddd") +ALU64_RRR_ENC(A2_addpsat, "0011","011","-","101","ddddd") +ALU64_RRR_ENC(A2_addspl, "0011","011","-","110","ddddd") +ALU64_RRR_ENC(A2_addsph, "0011","011","-","111","ddddd") + +ALU64_RRR_ENC(A2_vnavgh, "0011","100","-","000","ddddd") +ALU64_RRR_ENC(A2_vnavghr, "0011","100","-","001","ddddd") +ALU64_RRR_ENC(A2_vnavghcr, "0011","100","-","010","ddddd") +ALU64_RRR_ENC(A2_vnavgw, "0011","100","-","011","ddddd") +ALU64_RRR_ENC(A2_vnavgwr, "0011","100","-","10-","ddddd") +ALU64_RRR_ENC(A2_vnavgwcr, "0011","100","-","11-","ddddd") + +ALU64_RRR_ENC(A2_vminub, "0011","101","-","000","ddddd") +ALU64_RRR_ENC(A2_vminh, "0011","101","-","001","ddddd") +ALU64_RRR_ENC(A2_vminuh, "0011","101","-","010","ddddd") +ALU64_RRR_ENC(A2_vminw, "0011","101","-","011","ddddd") +ALU64_RRR_ENC(A2_vminuw, "0011","101","-","100","ddddd") +ALU64_RRR_ENC(A2_vmaxuw, "0011","101","-","101","ddddd") /* Doh! We did not put max with other max insns in v3 */ +ALU64_RRR_ENC(A2_minp, "0011","101","-","110","ddddd") +ALU64_RRR_ENC(A2_minup, "0011","101","-","111","ddddd") + +ALU64_RRR_ENC(A2_vmaxub, "0011","110","-","000","ddddd") +ALU64_RRR_ENC(A2_vmaxh, "0011","110","-","001","ddddd") +ALU64_RRR_ENC(A2_vmaxuh, "0011","110","-","010","ddddd") +ALU64_RRR_ENC(A2_vmaxw, "0011","110","-","011","ddddd") +ALU64_RRR_ENC(A2_maxp, "0011","110","-","100","ddddd") +ALU64_RRR_ENC(A2_maxup, "0011","110","-","101","ddddd") +ALU64_RRR_ENC(A2_vmaxb, "0011","110","-","110","ddddd") +ALU64_RRR_ENC(A2_vminb, "0011","110","-","111","ddddd") /* EJP: Because vmaxuw out of place */ + +ALU64_RRR_ENC(A2_andp, "0011","111","-","000","ddddd") +ALU64_RRR_ENC(A2_orp, "0011","111","-","010","ddddd") +ALU64_RRR_ENC(A2_xorp, "0011","111","-","100","ddddd") +ALU64_RRR_ENC(A4_andnp, "0011","111","-","001","ddddd") +ALU64_RRR_ENC(A4_ornp, "0011","111","-","011","ddddd") + +ALU64_RRR_ENC(A4_modwrapu, "0011","111","-","111","ddddd") + + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0100 -------- PP------ --------","[#4] Rdd=(Rs,Rt)") +LEGACY_ALU64_RRR_ENC(S2_packhl, "0100","--0","-","---","ddddd") +ALU64_RRR_ENC(A4_bitsplit, "0100","--1","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0101 -------- PP------ --------","[#5] Rd=(Rs,Rt)") +ALU64_RRR_ENC(A2_addh_l16_ll, "0101","000","-","00-","ddddd") +ALU64_RRR_ENC(A2_addh_l16_hl, "0101","000","-","01-","ddddd") +ALU64_RRR_ENC(A2_addh_l16_sat_ll,"0101","000","-","10-","ddddd") +ALU64_RRR_ENC(A2_addh_l16_sat_hl,"0101","000","-","11-","ddddd") + +ALU64_RRR_ENC(A2_subh_l16_ll, "0101","001","-","00-","ddddd") +ALU64_RRR_ENC(A2_subh_l16_hl, "0101","001","-","01-","ddddd") +ALU64_RRR_ENC(A2_subh_l16_sat_ll,"0101","001","-","10-","ddddd") +ALU64_RRR_ENC(A2_subh_l16_sat_hl,"0101","001","-","11-","ddddd") + +ALU64_RRR_ENC(A2_addh_h16_ll, "0101","010","-","000","ddddd") +ALU64_RRR_ENC(A2_addh_h16_lh, "0101","010","-","001","ddddd") +ALU64_RRR_ENC(A2_addh_h16_hl, "0101","010","-","010","ddddd") +ALU64_RRR_ENC(A2_addh_h16_hh, "0101","010","-","011","ddddd") +ALU64_RRR_ENC(A2_addh_h16_sat_ll,"0101","010","-","100","ddddd") +ALU64_RRR_ENC(A2_addh_h16_sat_lh,"0101","010","-","101","ddddd") +ALU64_RRR_ENC(A2_addh_h16_sat_hl,"0101","010","-","110","ddddd") +ALU64_RRR_ENC(A2_addh_h16_sat_hh,"0101","010","-","111","ddddd") + +ALU64_RRR_ENC(A2_subh_h16_ll, "0101","011","-","000","ddddd") +ALU64_RRR_ENC(A2_subh_h16_lh, "0101","011","-","001","ddddd") +ALU64_RRR_ENC(A2_subh_h16_hl, "0101","011","-","010","ddddd") +ALU64_RRR_ENC(A2_subh_h16_hh, "0101","011","-","011","ddddd") +ALU64_RRR_ENC(A2_subh_h16_sat_ll,"0101","011","-","100","ddddd") +ALU64_RRR_ENC(A2_subh_h16_sat_lh,"0101","011","-","101","ddddd") +ALU64_RRR_ENC(A2_subh_h16_sat_hl,"0101","011","-","110","ddddd") +ALU64_RRR_ENC(A2_subh_h16_sat_hh,"0101","011","-","111","ddddd") + +LEGACY_ALU64_RRR_ENC(A2_addsat, "0101","100","-","0--","ddddd") +LEGACY_ALU64_RRR_ENC(A2_subsat, "0101","100","-","1--","ddddd") + +ALU64_RRR_ENC(A2_min, "0101","101","-","0--","ddddd") +ALU64_RRR_ENC(A2_minu, "0101","101","-","1--","ddddd") + +ALU64_RRR_ENC(A2_max, "0101","110","-","0--","ddddd") +ALU64_RRR_ENC(A2_maxu, "0101","110","-","1--","ddddd") + +ALU64_RRR_ENC(S4_parity, "0101","111","-","---","ddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0110 -------- PP------ --------","[#6] Rd=#u10 ") +DEF_ENC32(F2_sfimm_p, ICLASS_ALU64" 0110 00i ----- PPiiiiii iiiddddd") +DEF_ENC32(F2_sfimm_n, ICLASS_ALU64" 0110 01i ----- PPiiiiii iiiddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 0111 -------- PP------ --------","[#7] Rd=(Rs,Rt,#u6)") +DEF_ENC32(M4_mpyrr_addi, ICLASS_ALU64" 0111 0ii sssss PPittttt iiiddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1000 -------- PP------ --------","[#8] Rd=(Rs,#u6,#U6)") +DEF_ENC32(M4_mpyri_addi, ICLASS_ALU64" 1000 Iii sssss PPiddddd iiiIIIII") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1001 -------- PP------ --------","[#9] Rdd=#u10 ") +DEF_ENC32(F2_dfimm_p, ICLASS_ALU64" 1001 00i ----- PPiiiiii iiiddddd") +DEF_ENC32(F2_dfimm_n, ICLASS_ALU64" 1001 01i ----- PPiiiiii iiiddddd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1010 -------- PP------ --------","[#10] Rx=(Rs,Rx,#s10)") +DEF_ENC32(S4_or_andix, ICLASS_ALU64" 1010 01i xxxxx PPiiiiii iiiuuuuu") +DEF_ENC32(S4_or_andi, ICLASS_ALU64" 1010 00i sssss PPiiiiii iiixxxxx") +DEF_ENC32(S4_or_ori, ICLASS_ALU64" 1010 10i sssss PPiiiiii iiixxxxx") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1011 -------- PP------ --------","[#11] Rd=(Rs,Rd,#s6)") +DEF_ENC32(S4_addaddi, ICLASS_ALU64" 1011 0ii sssss PPiddddd iiiuuuuu") +DEF_ENC32(S4_subaddi, ICLASS_ALU64" 1011 1ii sssss PPiddddd iiiuuuuu") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1100 -------- PP------ --------","[#12] Pd=(Rss,#s8)") +DEF_ENC32(A4_vcmpbeqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii00-dd") +DEF_ENC32(A4_vcmpbgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii00-dd") +DEF_ENC32(A4_vcmpbgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii00-dd") +DEF_ENC32(A4_vcmpheqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii01-dd") +DEF_ENC32(A4_vcmphgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii01-dd") +DEF_ENC32(A4_vcmphgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii01-dd") +DEF_ENC32(A4_vcmpweqi, ICLASS_ALU64"1100 000sssss PP-iiiii iii10-dd") +DEF_ENC32(A4_vcmpwgti, ICLASS_ALU64"1100 001sssss PP-iiiii iii10-dd") +DEF_ENC32(A4_vcmpwgtui, ICLASS_ALU64"1100 010sssss PP-0iiii iii10-dd") + +DEF_ENC32(F2_dfclass, ICLASS_ALU64"1100 100sssss PP-000ii iii10-dd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1101 -------- PP------ --------","[#13] Pd=(Rs,#s8)") +DEF_ENC32(A4_cmpbeqi, ICLASS_ALU64"1101 -00sssss PP-iiiii iii00-dd") +DEF_ENC32(A4_cmpbgti, ICLASS_ALU64"1101 -01sssss PP-iiiii iii00-dd") +DEF_ENC32(A4_cmpbgtui, ICLASS_ALU64"1101 -10sssss PP-0iiii iii00-dd") +DEF_ENC32(A4_cmpheqi, ICLASS_ALU64"1101 -00sssss PP-iiiii iii01-dd") +DEF_ENC32(A4_cmphgti, ICLASS_ALU64"1101 -01sssss PP-iiiii iii01-dd") +DEF_ENC32(A4_cmphgtui, ICLASS_ALU64"1101 -10sssss PP-0iiii iii01-dd") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1110 -------- PP------ --------","[#14] Rx=(#u9,op(Rx,#u5))") + +#define OP_OPI_RI(TAG,OPB)\ +DEF_ENC32(S4_andi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i00-")\ +DEF_ENC32(S4_ori_##TAG##_ri, ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i01-")\ +DEF_ENC32(S4_addi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i10-")\ +DEF_ENC32(S4_subi_##TAG##_ri,ICLASS_ALU64" 1110 iiixxxxx PPiIIIII iii"OPB"i11-") + +OP_OPI_RI(asl,"0") +OP_OPI_RI(lsr,"1") + + +DEF_FIELDROW_DESC32(ICLASS_ALU64" 1111 -------- PP------ --------","[#15] Rd=(Rs,Ru,#u6:2)") +DEF_ENC32(M4_mpyri_addr_u2, ICLASS_ALU64" 1111 0ii sssss PPiddddd iiiuuuuu") +DEF_ENC32(M4_mpyri_addr, ICLASS_ALU64" 1111 1ii sssss PPiddddd iiiuuuuu") diff --git a/target/hexagon/imported/encode_subinsn.def b/target/hexagon/imported/encode_subinsn.def new file mode 100644 index 0000000..ebb8119 --- /dev/null +++ b/target/hexagon/imported/encode_subinsn.def @@ -0,0 +1,150 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + + +/* DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) */ + + + + +/*********************/ +/* Ld1-type subinsns */ +/*********************/ +DEF_ENC_SUBINSN(SL1_loadri_io, SUBINSN_L1, "0iiiissssdddd") +DEF_ENC_SUBINSN(SL1_loadrub_io, SUBINSN_L1, "1iiiissssdddd") + +/*********************/ +/* St1-type subinsns */ +/*********************/ +DEF_ENC_SUBINSN(SS1_storew_io, SUBINSN_S1, "0ii iisssstttt") +DEF_ENC_SUBINSN(SS1_storeb_io, SUBINSN_S1, "1ii iisssstttt") + + +/*********************/ +/* Ld2-type subinsns */ +/*********************/ +DEF_ENC_SUBINSN(SL2_loadrh_io, SUBINSN_L2, "00i iissssdddd") +DEF_ENC_SUBINSN(SL2_loadruh_io, SUBINSN_L2, "01i iissssdddd") +DEF_ENC_SUBINSN(SL2_loadrb_io, SUBINSN_L2, "10i iissssdddd") +DEF_ENC_SUBINSN(SL2_loadri_sp, SUBINSN_L2, "111 0iiiiidddd") +DEF_ENC_SUBINSN(SL2_loadrd_sp, SUBINSN_L2, "111 10iiiiiddd") + +DEF_ENC_SUBINSN(SL2_deallocframe,SUBINSN_L2, "111 1100---0--") + +DEF_ENC_SUBINSN(SL2_return, SUBINSN_L2, "111 1101---0--") +DEF_ENC_SUBINSN(SL2_return_t, SUBINSN_L2, "111 1101---100") +DEF_ENC_SUBINSN(SL2_return_f, SUBINSN_L2, "111 1101---101") +DEF_ENC_SUBINSN(SL2_return_tnew, SUBINSN_L2, "111 1101---110") +DEF_ENC_SUBINSN(SL2_return_fnew, SUBINSN_L2, "111 1101---111") + +DEF_ENC_SUBINSN(SL2_jumpr31, SUBINSN_L2, "111 1111---0--") +DEF_ENC_SUBINSN(SL2_jumpr31_t, SUBINSN_L2, "111 1111---100") +DEF_ENC_SUBINSN(SL2_jumpr31_f, SUBINSN_L2, "111 1111---101") +DEF_ENC_SUBINSN(SL2_jumpr31_tnew,SUBINSN_L2, "111 1111---110") +DEF_ENC_SUBINSN(SL2_jumpr31_fnew,SUBINSN_L2, "111 1111---111") + + +/*********************/ +/* St2-type subinsns */ +/*********************/ +DEF_ENC_SUBINSN(SS2_storeh_io, SUBINSN_S2, "00i iisssstttt") +DEF_ENC_SUBINSN(SS2_storew_sp, SUBINSN_S2, "010 0iiiiitttt") +DEF_ENC_SUBINSN(SS2_stored_sp, SUBINSN_S2, "010 1iiiiiittt") + +DEF_ENC_SUBINSN(SS2_storewi0, SUBINSN_S2, "100 00ssssiiii") +DEF_ENC_SUBINSN(SS2_storewi1, SUBINSN_S2, "100 01ssssiiii") +DEF_ENC_SUBINSN(SS2_storebi0, SUBINSN_S2, "100 10ssssiiii") +DEF_ENC_SUBINSN(SS2_storebi1, SUBINSN_S2, "100 11ssssiiii") + +DEF_ENC_SUBINSN(SS2_allocframe, SUBINSN_S2, "111 0iiiii----") + + + +/*******************/ +/* A-type subinsns */ +/*******************/ +DEF_ENC_SUBINSN(SA1_addi, SUBINSN_A, "00i iiiiiixxxx") +DEF_ENC_SUBINSN(SA1_seti, SUBINSN_A, "010 iiiiiidddd") +DEF_ENC_SUBINSN(SA1_addsp, SUBINSN_A, "011 iiiiiidddd") + +DEF_ENC_SUBINSN(SA1_tfr, SUBINSN_A, "100 00ssssdddd") +DEF_ENC_SUBINSN(SA1_inc, SUBINSN_A, "100 01ssssdddd") +DEF_ENC_SUBINSN(SA1_and1, SUBINSN_A, "100 10ssssdddd") +DEF_ENC_SUBINSN(SA1_dec, SUBINSN_A, "100 11ssssdddd") + +DEF_ENC_SUBINSN(SA1_sxth, SUBINSN_A, "101 00ssssdddd") +DEF_ENC_SUBINSN(SA1_sxtb, SUBINSN_A, "101 01ssssdddd") +DEF_ENC_SUBINSN(SA1_zxth, SUBINSN_A, "101 10ssssdddd") +DEF_ENC_SUBINSN(SA1_zxtb, SUBINSN_A, "101 11ssssdddd") + + +DEF_ENC_SUBINSN(SA1_addrx, SUBINSN_A, "110 00ssssxxxx") +DEF_ENC_SUBINSN(SA1_cmpeqi, SUBINSN_A, "110 01ssss--ii") +DEF_ENC_SUBINSN(SA1_setin1, SUBINSN_A, "110 1--0--dddd") +DEF_ENC_SUBINSN(SA1_clrtnew, SUBINSN_A, "110 1--100dddd") +DEF_ENC_SUBINSN(SA1_clrfnew, SUBINSN_A, "110 1--101dddd") +DEF_ENC_SUBINSN(SA1_clrt, SUBINSN_A, "110 1--110dddd") +DEF_ENC_SUBINSN(SA1_clrf, SUBINSN_A, "110 1--111dddd") + + +DEF_ENC_SUBINSN(SA1_combine0i, SUBINSN_A, "111 -0-ii00ddd") +DEF_ENC_SUBINSN(SA1_combine1i, SUBINSN_A, "111 -0-ii01ddd") +DEF_ENC_SUBINSN(SA1_combine2i, SUBINSN_A, "111 -0-ii10ddd") +DEF_ENC_SUBINSN(SA1_combine3i, SUBINSN_A, "111 -0-ii11ddd") +DEF_ENC_SUBINSN(SA1_combinezr, SUBINSN_A, "111 -1ssss0ddd") +DEF_ENC_SUBINSN(SA1_combinerz, SUBINSN_A, "111 -1ssss1ddd") + + + + +/* maybe R=cmpeq ? */ + + +/* Add a group of NCJ: if (R.new==#0) jump:hint #r9 */ +/* Add a group of NCJ: if (R.new!=#0) jump:hint #r9 */ +/* NCJ goes with LD1, LD2 */ + + + + +DEF_FIELD32("---! !!!! !!!!!!!! EE------ --------",SUBFIELD_B_SLOT1,"B: Slot1 Instruction") +DEF_FIELD32("---- ---- -------- EE-!!!!! !!!!!!!!",SUBFIELD_A_SLOT0,"A: Slot0 Instruction") + + +/* DEF_PACKED32(TAG, CLASSA, CLASSB, ENCSTR) */ + +DEF_PACKED32(P2_PACKED_L1_L1, SUBINSN_L1, SUBINSN_L1, "000B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_L1_L2, SUBINSN_L2, SUBINSN_L1, "000B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_L2_L2, SUBINSN_L2, SUBINSN_L2, "001B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_A_A, SUBINSN_A, SUBINSN_A, "001B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") + +DEF_PACKED32(P2_PACKED_L1_A, SUBINSN_L1, SUBINSN_A, "010B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_L2_A, SUBINSN_L2, SUBINSN_A, "010B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S1_A, SUBINSN_S1, SUBINSN_A, "011B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S2_A, SUBINSN_S2, SUBINSN_A, "011B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") + +DEF_PACKED32(P2_PACKED_S1_L1, SUBINSN_S1, SUBINSN_L1, "100B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S1_L2, SUBINSN_S1, SUBINSN_L2, "100B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S1_S1, SUBINSN_S1, SUBINSN_S1, "101B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S1_S2, SUBINSN_S2, SUBINSN_S1, "101B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") + +DEF_PACKED32(P2_PACKED_S2_L1, SUBINSN_S2, SUBINSN_L1, "110B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S2_L2, SUBINSN_S2, SUBINSN_L2, "110B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") +DEF_PACKED32(P2_PACKED_S2_S2, SUBINSN_S2, SUBINSN_S2, "111B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") + +DEF_PACKED32(P2_PACKED_RESERVED, SUBINSN_INVALID, SUBINSN_INVALID, "111B BBBB BBBB BBBB EE1A AAAA AAAA AAAA") + From patchwork Tue Aug 18 15:50:34 2020 Content-Type: text/plain; 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bh=xxRUwtV9seQpocl47f4bhfzv96+ccLFVOhfXGSKbmKk=; b=b0Ry9doPfeIqVUdJKOnxPRZnHT8vQQValXB2Yn8R/vABdV9OwZ7GgkmK 52xGoqdH9Yypv+bshc/9MjgAOmOdetnQhqIA2sVVZK2POW6ohsJFF3uoU f8Q1vzw736hFMSVoOZ4pUkJZwyOZtl6f3PLs176hJp4W4gyxbcHJcXJXM o=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:51:00 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D444A1618; Tue, 18 Aug 2020 10:50:57 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 21/34] Hexagon (target/hexagon) generator phase 2 - generate header files Date: Tue, 18 Aug 2020 10:50:34 -0500 Message-Id: <1597765847-16637-22-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Python scripts generate the following files helper_protos_generated.h For each instruction we create DEF_HELPER function prototype helper_funcs_generated.h For each instruction we create the helper function definition tcg_funcs_generated.h For each instruction we create TCG code to generate call to helper shortcode_generated.h Generate a table of instruction "shortcode" semantics opcodes_def_generated.h Gives a list of all the opcodes op_attribs_generated.h Lists all the attributes associated with each instruction op_regs_generated.h Lists the register and immediate operands for each instruction printinsn_generated.h Data for printing (disassembling) each instruction (format string + operands) Signed-off-by: Taylor Simpson --- target/hexagon/gen_helper_funcs.py | 230 +++++++++++++++++++++++++++ target/hexagon/gen_helper_protos.py | 158 +++++++++++++++++++ target/hexagon/gen_op_attribs.py | 46 ++++++ target/hexagon/gen_op_regs.py | 119 ++++++++++++++ target/hexagon/gen_opcodes_def.py | 43 ++++++ target/hexagon/gen_printinsn.py | 182 ++++++++++++++++++++++ target/hexagon/gen_shortcode.py | 71 +++++++++ target/hexagon/gen_tcg_funcs.py | 301 ++++++++++++++++++++++++++++++++++++ target/hexagon/hex_common.py | 204 ++++++++++++++++++++++++ 9 files changed, 1354 insertions(+) create mode 100755 target/hexagon/gen_helper_funcs.py create mode 100755 target/hexagon/gen_helper_protos.py create mode 100755 target/hexagon/gen_op_attribs.py create mode 100755 target/hexagon/gen_op_regs.py create mode 100755 target/hexagon/gen_opcodes_def.py create mode 100755 target/hexagon/gen_printinsn.py create mode 100755 target/hexagon/gen_shortcode.py create mode 100755 target/hexagon/gen_tcg_funcs.py create mode 100755 target/hexagon/hex_common.py diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper_funcs.py new file mode 100755 index 0000000..4595887 --- /dev/null +++ b/target/hexagon/gen_helper_funcs.py @@ -0,0 +1,230 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +## +## Helpers for gen_helper_function +## +def gen_decl_ea(f): + f.write("size4u_t EA;\n") + +def gen_helper_return_type(f,regtype,regid,regno): + if regno > 1 : f.write(", ") + f.write("int32_t") + +def gen_helper_return_type_pair(f,regtype,regid,regno): + if regno > 1 : f.write(", ") + f.write("int64_t") + +def gen_helper_arg(f,regtype,regid,regno): + if regno > 0 : f.write(", " ) + f.write("int32_t %s%sV" % (regtype,regid)) + +def gen_helper_arg_new(f,regtype,regid,regno): + if regno >= 0 : f.write(", " ) + f.write("int32_t %s%sN" % (regtype,regid)) + +def gen_helper_arg_pair(f,regtype,regid,regno): + if regno >= 0 : f.write(", ") + f.write("int64_t %s%sV" % (regtype,regid)) + +def gen_helper_arg_opn(f,regtype,regid,i,tag): + if (is_pair(regid)): + gen_helper_arg_pair(f,regtype,regid,i) + elif (is_single(regid)): + if is_old_val(regtype, regid, tag): + gen_helper_arg(f,regtype,regid,i) + elif is_new_val(regtype, regid, tag): + gen_helper_arg_new(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def gen_helper_arg_imm(f,immlett): + f.write(", int32_t %s" % (imm_name(immlett))) + +def gen_helper_dest_decl(f,regtype,regid,regno,subfield=""): + f.write("int32_t %s%sV%s = 0;\n" % \ + (regtype,regid,subfield)) + +def gen_helper_dest_decl_pair(f,regtype,regid,regno,subfield=""): + f.write("int64_t %s%sV%s = 0;\n" % \ + (regtype,regid,subfield)) + +def gen_helper_dest_decl_opn(f,regtype,regid,i): + if (is_pair(regid)): + gen_helper_dest_decl_pair(f,regtype,regid,i) + elif (is_single(regid)): + gen_helper_dest_decl(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def gen_helper_return(f,regtype,regid,regno): + f.write("return %s%sV;\n" % (regtype,regid)) + +def gen_helper_return_pair(f,regtype,regid,regno): + f.write("return %s%sV;\n" % (regtype,regid)) + +def gen_helper_return_opn(f, regtype, regid, i): + if (is_pair(regid)): + gen_helper_return_pair(f,regtype,regid,i) + elif (is_single(regid)): + gen_helper_return(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +## +## Generate the TCG code to call the helper +## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} +## We produce: +## #ifndef fGEN_TCG_A2_add +## int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t RtV) +## { +## uint32_t slot __attribute__(unused)) = 4; +## int32_t RdV = 0; +## { RdV=RsV+RtV;} +## return RdV; +## } +## #endif +## +def gen_helper_function(f, tag, tagregs, tagimms): + regs = tagregs[tag] + imms = tagimms[tag] + + f.write('#ifndef fGEN_TCG_%s\n' % tag) + numresults = 0 + numscalarresults = 0 + numscalarreadwrite = 0 + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + numresults += 1 + if (is_scalar_reg(regtype)): + numscalarresults += 1 + if (is_readwrite(regid)): + if (is_scalar_reg(regtype)): + numscalarreadwrite += 1 + + if (numscalarresults > 1): + ## The helper is bogus when there is more than one result + f.write("void HELPER(%s)(CPUHexagonState *env) { BOGUS_HELPER(%s); }\n" + % (tag, tag)) + else: + ## The return type of the function is the type of the destination + ## register + i=0 + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + if (is_pair(regid)): + gen_helper_return_type_pair(f,regtype,regid,i) + elif (is_single(regid)): + gen_helper_return_type(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + i += 1 + + if (numscalarresults == 0): + f.write("void") + f.write(" HELPER(%s)(CPUHexagonState *env" % tag) + + i = 1 + + ## Arguments to the helper function are the source regs and immediates + for regtype,regid,toss,numregs in regs: + if (is_read(regid)): + gen_helper_arg_opn(f,regtype,regid,i,tag) + i += 1 + for immlett,bits,immshift in imms: + gen_helper_arg_imm(f,immlett) + i += 1 + if need_slot(tag): + if i > 0: f.write(", ") + f.write("uint32_t slot") + i += 1 + if need_part1(tag): + if i > 0: f.write(", ") + f.write("uint32_t part1") + f.write(")\n{\n") + if (not need_slot(tag)): + f.write("uint32_t slot __attribute__((unused)) = 4;\n" ) + if need_ea(tag): gen_decl_ea(f) + ## Declare the return variable + i=0 + for regtype,regid,toss,numregs in regs: + if (is_writeonly(regid)): + gen_helper_dest_decl_opn(f,regtype,regid,i) + i += 1 + + if 'A_FPOP' in attribdict[tag]: + f.write('fFPOP_START();\n'); + + f.write(semdict[tag]) + f.write("\n") + + if 'A_FPOP' in attribdict[tag]: + f.write('fFPOP_END();\n'); + + ## Save/return the return variable + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + gen_helper_return_opn(f, regtype, regid, i) + f.write("}\n") + ## End of the helper definition + f.write('#endif\n') + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + calculate_attribs() + tagregs = get_tagregs() + tagimms = get_tagimms() + + f = StringIO() + + for tag in tags: + ## Skip the priv instructions + if ( "A_PRIV" in attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in attribdict[tag] ) : + continue + ## Skip the diag instructions + if ( tag == "Y6_diag" ) : + continue + if ( tag == "Y6_diag0" ) : + continue + if ( tag == "Y6_diag1" ) : + continue + + gen_helper_function(f, tag, tagregs, tagimms) + + + realf = open('helper_funcs_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helper_protos.py new file mode 100755 index 0000000..6d5ab07 --- /dev/null +++ b/target/hexagon/gen_helper_protos.py @@ -0,0 +1,158 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +## +## Helpers for gen_helper_prototype +## +def_helper_types = { + 'N' : 's32', + 'O' : 's32', + 'P' : 's32', + 'M' : 's32', + 'C' : 's32', + 'R' : 's32', + 'V' : 'ptr', + 'Q' : 'ptr' +} + +def_helper_types_pair = { + 'R' : 's64', + 'C' : 's64', + 'S' : 's64', + 'G' : 's64', + 'V' : 'ptr', + 'Q' : 'ptr' +} + +def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i): + if (is_pair(regid)): + f.write(", %s" % (def_helper_types_pair[regtype])) + elif (is_single(regid)): + f.write(", %s" % (def_helper_types[regtype])) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +## +## Generate the DEF_HELPER prototype for an instruction +## For A2_add: Rd32=add(Rs32,Rt32) +## We produce: +## #ifndef fGEN_TCG_A2_add +## DEF_HELPER_3(A2_add, s32, env, s32, s32) +## #endif +## +def gen_helper_prototype(f, tag, tagregs, tagimms): + regs = tagregs[tag] + imms = tagimms[tag] + + f.write('#ifndef fGEN_TCG_%s\n' % tag) + numresults = 0 + numscalarresults = 0 + numscalarreadwrite = 0 + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + numresults += 1 + if (is_scalar_reg(regtype)): + numscalarresults += 1 + if (is_readwrite(regid)): + if (is_scalar_reg(regtype)): + numscalarreadwrite += 1 + + if (numscalarresults > 1): + ## The helper is bogus when there is more than one result + f.write('DEF_HELPER_1(%s, void, env)\n' % tag) + else: + ## Figure out how many arguments the helper will take + if (numscalarresults == 0): + def_helper_size = len(regs)+len(imms)+numscalarreadwrite+1 + if need_part1(tag): def_helper_size += 1 + if need_slot(tag): def_helper_size += 1 + f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) + ## The return type is void + f.write(', void' ) + else: + def_helper_size = len(regs)+len(imms)+numscalarreadwrite + if need_part1(tag): def_helper_size += 1 + if need_slot(tag): def_helper_size += 1 + f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) + + ## Generate the qemu DEF_HELPER type for each result + i=0 + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + + ## Put the env between the outputs and inputs + f.write(', env' ) + i += 1 + + ## Generate the qemu type for each input operand (regs and immediates) + for regtype,regid,toss,numregs in regs: + if (is_read(regid)): + gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + for immlett,bits,immshift in imms: + f.write(", s32") + + ## Add the arguments for the instruction slot and part1 (if needed) + if need_slot(tag): f.write(', i32' ) + if need_part1(tag): f.write(' , i32' ) + f.write(')\n') + f.write('#endif\n') + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + calculate_attribs() + tagregs = get_tagregs() + tagimms = get_tagimms() + + f = StringIO() + + for tag in tags: + ## Skip the priv instructions + if ( "A_PRIV" in attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in attribdict[tag] ) : + continue + ## Skip the diag instructions + if ( tag == "Y6_diag" ) : + continue + if ( tag == "Y6_diag0" ) : + continue + if ( tag == "Y6_diag1" ) : + continue + + gen_helper_prototype(f, tag, tagregs, tagimms) + + realf = open('helper_protos_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_op_attribs.py b/target/hexagon/gen_op_attribs.py new file mode 100755 index 0000000..663296e --- /dev/null +++ b/target/hexagon/gen_op_attribs.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + calculate_attribs() + + ## + ## Generate the op_attribs_generated.h file + ## Lists all the attributes associated with each instruction + ## + f = StringIO() + for tag in tags: + f.write('OP_ATTRIB(%s,ATTRIBS(%s))\n' % \ + (tag, ','.join(sorted(attribdict[tag])))) + realf = open('op_attribs_generated.h', 'wt') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py new file mode 100755 index 0000000..abb7441 --- /dev/null +++ b/target/hexagon/gen_op_regs.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +## +## Generate the op_regs_generated.h file +## Lists the register and immediate operands for each instruction +## +def calculate_regid_reg(tag): + def letter_inc(x): return chr(ord(x)+1) + ordered_implregs = [ 'SP','FP','LR' ] + srcdst_lett = 'X' + src_lett = 'S' + dst_lett = 'D' + retstr = "" + mapdict = {} + for reg in ordered_implregs: + reg_rd = 0 + reg_wr = 0 + if ('A_IMPLICIT_WRITES_'+reg) in attribdict[tag]: reg_wr = 1 + if reg_rd and reg_wr: + retstr += srcdst_lett + mapdict[srcdst_lett] = reg + srcdst_lett = letter_inc(srcdst_lett) + elif reg_rd: + retstr += src_lett + mapdict[src_lett] = reg + src_lett = letter_inc(src_lett) + elif reg_wr: + retstr += dst_lett + mapdict[dst_lett] = reg + dst_lett = letter_inc(dst_lett) + return retstr,mapdict + +def calculate_regid_letters(tag): + retstr,mapdict = calculate_regid_reg(tag) + return retstr + +def strip_reg_prefix(x): + y=x.replace('UREG.','') + y=y.replace('MREG.','') + return y.replace('GREG.','') + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + tagregs = get_tagregs() + tagimms = get_tagimms() + + f = StringIO() + + for tag in tags: + regs = tagregs[tag] + rregs = [] + wregs = [] + regids = "" + for regtype,regid,toss,numregs in regs: + if is_read(regid): + if regid[0] not in regids: regids += regid[0] + rregs.append(regtype+regid+numregs) + if is_written(regid): + wregs.append(regtype+regid+numregs) + if regid[0] not in regids: regids += regid[0] + for attrib in attribdict[tag]: + if attribinfo[attrib]['rreg']: + rregs.append(strip_reg_prefix(attribinfo[attrib]['rreg'])) + if attribinfo[attrib]['wreg']: + wregs.append(strip_reg_prefix(attribinfo[attrib]['wreg'])) + regids += calculate_regid_letters(tag) + f.write('REGINFO(%s,"%s",\t/*RD:*/\t"%s",\t/*WR:*/\t"%s")\n' % \ + (tag,regids,",".join(rregs),",".join(wregs))) + + for tag in tags: + imms = tagimms[tag] + f.write( 'IMMINFO(%s' % tag) + if not imms: + f.write(''','u',0,0,'U',0,0''') + for sign,size,shamt in imms: + if sign == 'r': sign = 's' + if not shamt: + shamt = "0" + f.write(''','%s',%s,%s''' % (sign,size,shamt)) + if len(imms) == 1: + if sign.isupper(): + myu = 'u' + else: + myu = 'U' + f.write(''','%s',0,0''' % myu) + f.write(')\n') + + realf = open('op_regs_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_opcodes_def.py b/target/hexagon/gen_opcodes_def.py new file mode 100755 index 0000000..c34c2b1 --- /dev/null +++ b/target/hexagon/gen_opcodes_def.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +def main(): + read_semantics_file(sys.argv[1]) + + ## + ## Generate the opcodes_def_generated.h file + ## Gives a list of all the opcodes + ## + f = StringIO() + for tag in tags: + f.write ( "OPCODE(%s),\n" % (tag) ) + realf = open('opcodes_def_generated.h', 'wt') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_printinsn.py b/target/hexagon/gen_printinsn.py new file mode 100755 index 0000000..6fb9424 --- /dev/null +++ b/target/hexagon/gen_printinsn.py @@ -0,0 +1,182 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +## +## Generate the printinsn_generated.h file +## Data for printing each instruction (format string + operands) +## +def regprinter(m): + str = m.group(1) + str += ":".join(["%d"]*len(m.group(2))) + str += m.group(3) + if ('S' in m.group(1)) and (len(m.group(2)) == 1): + str += "/%s" + elif ('C' in m.group(1)) and (len(m.group(2)) == 1): + str += "/%s" + return str + +def spacify(s): + # Regular expression that matches any operator that contains '=' character: + opswithequal_re = '[-+^&|!<>=]?=' + # Regular expression that matches any assignment operator. + assignment_re = '[-+^&|]?=' + + # Out of the operators that contain the = sign, if the operator is also an + # assignment, spaces will be added around it, unless it's enclosed within + # parentheses, or spaces are already present. + + equals = re.compile(opswithequal_re) + assign = re.compile(assignment_re) + + slen = len(s) + paren_count = {} + i = 0 + pc = 0 + while i < slen: + c = s[i] + if c == '(': + pc += 1 + elif c == ')': + pc -= 1 + paren_count[i] = pc + i += 1 + + # Iterate over all operators that contain the equal sign. If any + # match is also an assignment operator, add spaces around it if + # the parenthesis count is 0. + pos = 0 + out = [] + for m in equals.finditer(s): + ms = m.start() + me = m.end() + # t is the string that matched opswithequal_re. + t = m.string[ms:me] + out += s[pos:ms] + pos = me + if paren_count[ms] == 0: + # Check if the entire string t is an assignment. + am = assign.match(t) + if am and len(am.group(0)) == me-ms: + # Don't add spaces if they are already there. + if ms > 0 and s[ms-1] != ' ': + out.append(' ') + out += t + if me < slen and s[me] != ' ': + out.append(' ') + continue + # If this is not an assignment, just append it to the output + # string. + out += t + + # Append the remaining part of the string. + out += s[pos:len(s)] + return ''.join(out) + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + + immext_casere = re.compile(r'IMMEXT\(([A-Za-z])') + + f = StringIO() + + for tag in tags: + if not behdict[tag]: continue + extendable_upper_imm = False + extendable_lower_imm = False + m = immext_casere.search(semdict[tag]) + if m: + if m.group(1).isupper(): + extendable_upper_imm = True + else: + extendable_lower_imm = True + beh = behdict[tag] + beh = regre.sub(regprinter,beh) + beh = absimmre.sub(r"#%s0x%x",beh) + beh = relimmre.sub(r"PC+%s%d",beh) + beh = spacify(beh) + # Print out a literal "%s" at the end, used to match empty string + # so C won't complain at us + if ("A_VECX" in attribdict[tag]): macname = "DEF_VECX_PRINTINFO" + else: macname = "DEF_PRINTINFO" + f.write('%s(%s,"%s%%s"' % (macname,tag,beh)) + regs_or_imms = reg_or_immre.findall(behdict[tag]) + ri = 0 + seenregs = {} + for allregs,a,b,c,d,allimm,immlett,bits,immshift in regs_or_imms: + if a: + #register + if b in seenregs: + regno = seenregs[b] + else: + regno = ri + if len(b) == 1: + f.write(',REGNO(%d)' % regno) + if 'S' in a: + f.write(',sreg2str(REGNO(%d))' % regno) + elif 'C' in a: + f.write(',creg2str(REGNO(%d))' % regno) + elif len(b) == 2: + f.write(',REGNO(%d)+1,REGNO(%d)' % (regno,regno)) + elif len(b) == 4: + f.write(',REGNO(%d)^3,REGNO(%d)^2,REGNO(%d)^1,REGNO(%d)' % \ + (regno,regno,regno,regno)) + else: + print("Put some stuff to handle quads here") + if b not in seenregs: + seenregs[b] = ri + ri += 1 + else: + #immediate + if (immlett.isupper()): + if extendable_upper_imm: + if immlett in 'rR': + f.write(',insn->extension_valid?"##":""') + else: + f.write(',insn->extension_valid?"#":""') + else: + f.write(',""') + ii = 1 + else: + if extendable_lower_imm: + if immlett in 'rR': + f.write(',insn->extension_valid?"##":""') + else: + f.write(',insn->extension_valid?"#":""') + else: + f.write(',""') + ii = 0 + f.write(',IMMNO(%d)' % ii) + # append empty string so there is at least one more arg + f.write(',"")\n') + + realf = open('printinsn_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_shortcode.py b/target/hexagon/gen_shortcode.py new file mode 100755 index 0000000..3255972 --- /dev/null +++ b/target/hexagon/gen_shortcode.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +def gen_shortcode(f, tag): + f.write('DEF_SHORTCODE(%s, %s)\n' % (tag,semdict[tag])) + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + calculate_attribs() + tagregs = get_tagregs() + tagimms = get_tagimms() + + ## + ## Generate the shortcode_generated.h file + ## + f = StringIO() + + f.write("#ifndef DEF_SHORTCODE\n") + f.write("#define DEF_SHORTCODE(TAG,SHORTCODE) /* Nothing */\n") + f.write("#endif\n") + + for tag in tags: + ## Skip the priv instructions + if ( "A_PRIV" in attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in attribdict[tag] ) : + continue + ## Skip the diag instructions + if ( tag == "Y6_diag" ) : + continue + if ( tag == "Y6_diag0" ) : + continue + if ( tag == "Y6_diag1" ) : + continue + + gen_shortcode(f, tag) + + f.write("#undef DEF_SHORTCODE\n") + + realf = open('shortcode_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py new file mode 100755 index 0000000..1b2ef5b --- /dev/null +++ b/target/hexagon/gen_tcg_funcs.py @@ -0,0 +1,301 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +from hex_common import * + +## +## Helpers for gen_tcg_func +## +def gen_decl_ea_tcg(f): + f.write("DECL_EA;\n") + +def gen_free_ea_tcg(f): + f.write("FREE_EA;\n") + +def genptr_decl(f,regtype,regid,regno): + regN="%s%sN" % (regtype,regid) + macro = "DECL_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sV, %s, %d, 0);\n" % \ + (macro, regtype, regid, regN, regno)) + +def genptr_decl_new(f,regtype,regid,regno): + regN="%s%sX" % (regtype,regid) + macro = "DECL_NEW_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sN, %s, %d, 0);\n" % \ + (macro, regtype, regid, regN, regno)) + +def genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i): + if (is_pair(regid)): + genptr_decl(f,regtype,regid,i) + elif (is_single(regid)): + if is_old_val(regtype, regid, tag): + genptr_decl(f,regtype,regid,i) + elif is_new_val(regtype, regid, tag): + genptr_decl_new(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def genptr_decl_imm(f,immlett): + if (immlett.isupper()): + i = 1 + else: + i = 0 + f.write("DECL_IMM(%s,%d);\n" % (imm_name(immlett),i)) + +def genptr_free(f,regtype,regid,regno): + macro = "FREE_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sV);\n" % (macro, regtype, regid)) + +def genptr_free_new(f,regtype,regid,regno): + macro = "FREE_NEW_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sN);\n" % (macro, regtype, regid)) + +def genptr_free_opn(f,regtype,regid,i,tag): + if (is_pair(regid)): + genptr_free(f,regtype,regid,i) + elif (is_single(regid)): + if is_old_val(regtype, regid, tag): + genptr_free(f,regtype,regid,i) + elif is_new_val(regtype, regid, tag): + genptr_free_new(f,regtype,regid,i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def genptr_free_imm(f,immlett): + f.write("FREE_IMM(%s);\n" % (imm_name(immlett))) + +def genptr_src_read(f,regtype,regid): + macro = "READ_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sV, %s%sN);\n" % \ + (macro,regtype,regid,regtype,regid)) + +def genptr_src_read_new(f,regtype,regid): + macro = "READ_NEW_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sN, %s%sX);\n" % \ + (macro,regtype,regid,regtype,regid)) + +def genptr_src_read_opn(f,regtype,regid,tag): + if (is_pair(regid)): + genptr_src_read(f,regtype,regid) + elif (is_single(regid)): + if is_old_val(regtype, regid, tag): + genptr_src_read(f,regtype,regid) + elif is_new_val(regtype, regid, tag): + genptr_src_read_new(f,regtype,regid) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i): + if (i > 0): f.write(", ") + if (is_pair(regid)): + f.write("%s%sV" % (regtype,regid)) + elif (is_single(regid)): + if is_old_val(regtype, regid, tag): + f.write("%s%sV" % (regtype,regid)) + elif is_new_val(regtype, regid, tag): + f.write("%s%sN" % (regtype,regid)) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +def gen_helper_decl_imm(f,immlett): + f.write("DECL_TCG_IMM(tcgv_%s, %s);\n" % \ + (imm_name(immlett), imm_name(immlett))) + +def gen_helper_call_imm(f,immlett): + f.write(", tcgv_%s" % imm_name(immlett)) + +def gen_helper_free_imm(f,immlett): + f.write("FREE_TCG_IMM(tcgv_%s);\n" % imm_name(immlett)) + +def genptr_dst_write(f,regtype, regid): + macro = "WRITE_%sREG_%s" % (regtype, regid) + f.write("%s(%s%sN, %s%sV);\n" % (macro, regtype, regid, regtype, regid)) + +def genptr_dst_write_opn(f,regtype, regid, tag): + if (is_pair(regid)): + genptr_dst_write(f, regtype, regid) + elif (is_single(regid)): + genptr_dst_write(f, regtype, regid) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +## +## Generate the TCG code to call the helper +## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} +## We produce: +## { +## /* A2_add */ +## DECL_RREG_d(RdV, RdN, 0, 0); +## DECL_RREG_s(RsV, RsN, 1, 0); +## DECL_RREG_t(RtV, RtN, 2, 0); +## READ_RREG_s(RsV, RsN); +## READ_RREG_t(RtV, RtN); +## #ifdef fGEN_TCG_A2_add +## fGEN_TCG_A2_add({ RdV=RsV+RtV;}); +## #else +## gen_helper_A2_add(RdV, cpu_env, RsV, RtV); +## #endif +## WRITE_RREG_d(RdN, RdV); +## FREE_RREG_d(RdV); +## FREE_RREG_s(RsV); +## FREE_RREG_t(RtV); +## /* A2_add */ +## } +## +def gen_tcg_func(f, tag, regs, imms): + f.write('{\n') + f.write('/* %s */\n' % tag) + if need_ea(tag): gen_decl_ea_tcg(f) + i=0 + ## Declare all the operands (regs and immediates) + for regtype,regid,toss,numregs in regs: + genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + for immlett,bits,immshift in imms: + genptr_decl_imm(f,immlett) + + if 'A_PRIV' in attribdict[tag]: + f.write('fCHECKFORPRIV();\n') + if 'A_GUEST' in attribdict[tag]: + f.write('fCHECKFORGUEST();\n') + if 'A_FPOP' in attribdict[tag]: + f.write('fFPOP_START();\n'); + + ## Read all the inputs + for regtype,regid,toss,numregs in regs: + if (is_read(regid)): + genptr_src_read_opn(f,regtype,regid,tag) + + f.write("#ifdef fGEN_TCG_%s\n" % tag) + f.write("fGEN_TCG_%s(%s);\n" % (tag, semdict[tag])) + f.write("#else\n") + ## Generate the call to the helper + f.write("do {\n") + for immlett,bits,immshift in imms: + gen_helper_decl_imm(f,immlett) + if need_part1(tag): f.write("PART1_WRAP(") + if need_slot(tag): f.write("SLOT_WRAP(") + f.write("gen_helper_%s(" % (tag)) + i=0 + ## If there is a scalar result, it is the return type + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + if (i > 0): f.write(", ") + f.write("cpu_env") + i=1 + for regtype,regid,toss,numregs in regs: + if (is_read(regid)): + gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + for immlett,bits,immshift in imms: + gen_helper_call_imm(f,immlett) + + if need_slot(tag): f.write(", slot") + if need_part1(tag): f.write(", part1" ) + f.write(")") + if need_slot(tag): f.write(")") + if need_part1(tag): f.write(")") + f.write(";\n") + for immlett,bits,immshift in imms: + gen_helper_free_imm(f,immlett) + f.write("} while (0);\n") + f.write("#endif\n") + + ## Write all the outputs + for regtype,regid,toss,numregs in regs: + if (is_written(regid)): + genptr_dst_write_opn(f,regtype, regid, tag) + + if 'A_FPOP' in attribdict[tag]: + f.write('fFPOP_END();\n'); + + + ## Free all the operands (regs and immediates) + if need_ea(tag): gen_free_ea_tcg(f) + for regtype,regid,toss,numregs in regs: + genptr_free_opn(f,regtype,regid,i,tag) + i += 1 + for immlett,bits,immshift in imms: + genptr_free_imm(f,immlett) + + f.write("/* %s */\n" % tag) + f.write("}") + +def gen_def_tcg_func(f, tag, tagregs, tagimms): + regs = tagregs[tag] + imms = tagimms[tag] + + f.write('DEF_TCG_FUNC(%s, /* %s */\n' % (tag,semdict[tag])) + gen_tcg_func(f, tag, regs, imms) + f.write(")\n" ) + +def main(): + read_semantics_file(sys.argv[1]) + read_attribs_file(sys.argv[2]) + calculate_attribs() + tagregs = get_tagregs() + tagimms = get_tagimms() + + f = StringIO() + + f.write("#ifndef DEF_TCG_FUNC\n") + f.write("#define DEF_TCG_FUNC(TAG,GENFN) /* Nothing */\n") + f.write("#endif\n") + + for tag in tags: + ## Skip the priv instructions + if ( "A_PRIV" in attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in attribdict[tag] ) : + continue + ## Skip the diag instructions + if ( tag == "Y6_diag" ) : + continue + if ( tag == "Y6_diag0" ) : + continue + if ( tag == "Y6_diag1" ) : + continue + + gen_def_tcg_func(f, tag, tagregs, tagimms) + + f.write("#undef DEF_TCG_FUNC\n") + + realf = open('tcg_funcs_generated.h','w') + realf.write(f.getvalue()) + realf.close() + f.close() + +if __name__ == "__main__": + main() diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py new file mode 100755 index 0000000..d45ffab --- /dev/null +++ b/target/hexagon/hex_common.py @@ -0,0 +1,204 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +behdict = {} # tag ->behavior +semdict = {} # tag -> semantics +attribdict = {} # tag -> attributes +macros = {} # macro -> macro information... +attribinfo = {} # Register information and misc +tags = [] # list of all tags + +# We should do this as a hash for performance, +# but to keep order let's keep it as a list. +def uniquify(seq): + seen = set() + seen_add = seen.add + return [x for x in seq if x not in seen and not seen_add(x)] + +regre = re.compile( + r"((?" % l) + macro.attribs |= expand_macro_attribs( + macros[submacro], allmac_re) + finished_macros.add(macro.key) + return macro.attribs + +immextre = re.compile(r'f(MUST_)?IMMEXT[(]([UuSsRr])') +def calculate_attribs(): + # Recurse down macros, find attributes from sub-macros + macroValues = list(macros.values()) + allmacros_restr = "|".join(set([ m.re.pattern for m in macroValues ])) + allmacros_re = re.compile(allmacros_restr) + for macro in macroValues: + expand_macro_attribs(macro,allmacros_re) + # Append attributes to all instructions + for tag in tags: + for macname in allmacros_re.findall(semdict[tag]): + if not macname: continue + macro = macros[macname] + attribdict[tag] |= set(macro.attribs) + +def SEMANTICS(tag, beh, sem): + #print tag,beh,sem + behdict[tag] = beh + semdict[tag] = sem + attribdict[tag] = set() + tags.append(tag) # dicts have no order, this is for order + +def ATTRIBUTES(tag, attribstring): + attribstring = \ + attribstring.replace("ATTRIBS","").replace("(","").replace(")","") + if not attribstring: + return + attribs = attribstring.split(",") + for attrib in attribs: + attribdict[tag].add(attrib.strip()) + +class Macro(object): + __slots__ = ['key','name', 'beh', 'attribs', 're'] + def __init__(self, name, beh, attribs): + self.key = name + self.name = name + self.beh = beh + self.attribs = set(attribs) + self.re = re.compile("\\b" + name + "\\b") + +def MACROATTRIB(macname,beh,attribstring): + attribstring = attribstring.replace("(","").replace(")","") + if attribstring: + attribs = attribstring.split(",") + else: + attribs = [] + macros[macname] = Macro(macname,beh,attribs) + +def compute_tag_regs(tag): + return uniquify(regre.findall(behdict[tag])) + +def compute_tag_immediates(tag): + return uniquify(immre.findall(behdict[tag])) + +## +## tagregs is the main data structure we'll use +## tagregs[tag] will contain the registers used by an instruction +## Within each entry, we'll use the regtype and regid fields +## regtype can be one of the following +## C control register +## N new register value +## P predicate register +## R GPR register +## M modifier register +## regid can be one of the following +## d, e destination register +## dd destination register pair +## s, t, u, v, w source register +## ss, tt, uu, vv source register pair +## x, y read-write register +## xx, yy read-write register pair +## +def get_tagregs(): + return dict(zip(tags, list(map(compute_tag_regs, tags)))) + +def get_tagimms(): + return dict(zip(tags, list(map(compute_tag_immediates, tags)))) + +def is_pair(regid): + return len(regid) == 2 + +def is_single(regid): + return len(regid) == 1 + +def is_written(regid): + return regid[0] in "dexy" + +def is_writeonly(regid): + return regid[0] in "de" + +def is_read(regid): + return regid[0] in "stuvwxy" + +def is_readwrite(regid): + return regid[0] in "xy" + +def is_scalar_reg(regtype): + return regtype in "RPC" + +def is_old_val(regtype, regid, tag): + return regtype+regid+'V' in semdict[tag] + +def is_new_val(regtype, regid, tag): + return regtype+regid+'N' in semdict[tag] + +def need_slot(tag): + if ('A_CONDEXEC' in attribdict[tag] or + 'A_STORE' in attribdict[tag] or + 'A_LOAD' in attribdict[tag]): + return 1 + else: + return 0 + +def need_part1(tag): + return re.compile(r"fPART1").search(semdict[tag]) + +def need_ea(tag): + return re.compile(r"\bEA\b").search(semdict[tag]) + +def imm_name(immlett): + return "%siV" % immlett + +def read_semantics_file(name): + eval_line = "" + for line in open(name, 'rt').readlines(): + if not line.startswith("#"): + eval_line += line + if line.endswith("\\\n"): + eval_line.rstrip("\\\n") + else: + eval(eval_line.strip()) + eval_line = "" + +def read_attribs_file(name): + attribre = re.compile(r'DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), ' + + r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)') + for line in open(sys.argv[2], 'rt').readlines(): + if not attribre.match(line): + continue + (attrib_base,descr,rreg,wreg) = attribre.findall(line)[0] + attrib_base = 'A_' + attrib_base + attribinfo[attrib_base] = {'rreg':rreg, 'wreg':wreg, 'descr':descr} From patchwork Tue Aug 18 15:50:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCF83C433DF for ; Tue, 18 Aug 2020 16:15:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 89DD120674 for ; Tue, 18 Aug 2020 16:15:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="L/olEIMb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 89DD120674 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k84GS-0006A0-MK for qemu-devel@archiver.kernel.org; Tue, 18 Aug 2020 12:15:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83u3-0008J6-3A for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:59 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:12936) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83u0-0005rl-K7 for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765916; x=1629301916; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6BrnM6dxL5Kb7rzVDKnQjwqRht2632BP/pwRgXWRBAk=; b=L/olEIMbwKHg52j6/taJWiomJIwFvB7EN/ipmeZ8rAEcDiTSeiDEo0iN YaNiAlc6Scj0IF+u5QpG9EHkELnb7Hc4H1gN5SqUzLqEfsSrQsiTzbcXp XheRt91ZJRZK8VV21CiDsv9lqV4bmJUOq/nqjsJUEYJOJI+7U8aQIzgTk o=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:51:00 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id EA33F16D3; Tue, 18 Aug 2020 10:50:57 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 22/34] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Date: Tue, 18 Aug 2020 10:50:35 -0500 Message-Id: <1597765847-16637-23-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson --- target/hexagon/gen_dectree_import.c | 191 ++++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 target/hexagon/gen_dectree_import.c diff --git a/target/hexagon/gen_dectree_import.c b/target/hexagon/gen_dectree_import.c new file mode 100644 index 0000000..237726e --- /dev/null +++ b/target/hexagon/gen_dectree_import.c @@ -0,0 +1,191 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * This program generates the encodings file that is processed by + * the dectree.py script to produce the decoding tree. We use the C + * preprocessor to manipulate the files imported from the Hexagon + * architecture library. + */ +#include "qemu/osdep.h" +#include "opcodes.h" + +#define STRINGIZE(X) #X + +const char *opcode_names[] = { +#define OPCODE(IID) STRINGIZE(IID) +#include "opcodes_def_generated.h" + NULL +#undef OPCODE +}; + +const char *opcode_syntax[XX_LAST_OPCODE]; + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + */ +void opcode_init(void) +{ +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + opcode_syntax[TAG] = BEH; +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + opcode_syntax[TAG] = BEH; +#include "imported/allidefs.def" +#undef Q6INSN +#undef EXTINSN +} + +const char *opcode_rregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) RREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +const char *opcode_wregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) WREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +opcode_encoding_t opcode_encodings[] = { +#define DEF_ENC32(TAG, ENCSTR) \ + [TAG] = { .encoding = ENCSTR }, +#define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#include "imported/encode.def" +#undef DEF_ENC32 +#undef DEF_ENC_SUBINSN +#undef DEF_EXT_ENC +}; + +static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = { + "NORMAL", + "16BIT", + "SUBINSN_A", + "SUBINSN_L1", + "SUBINSN_L2", + "SUBINSN_S1", + "SUBINSN_S2", + "EXT_noext", + "EXT_mmvec", +}; + +static const char *get_opcode_enc(int opcode) +{ + const char *tmp = opcode_encodings[opcode].encoding; + if (tmp == NULL) { + tmp = "MISSING ENCODING"; + } + return tmp; +} + +static const char *get_opcode_enc_class(int opcode) +{ + return opcode_enc_class_names[opcode_encodings[opcode].enc_class]; +} + +static void gen_iset_table(FILE *out) +{ + int i; + + fprintf(out, "iset = {\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\' : {\n", opcode_names[i]); + fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]); + fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]); + fprintf(out, "\t\t\'rregs\' : \'%s\',\n", opcode_rregs[i]); + fprintf(out, "\t\t\'wregs\' : \'%s\',\n", opcode_wregs[i]); + fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i)); + fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i)); + fprintf(out, "\t},\n"); + } + fprintf(out, "};\n\n"); +} + +static void gen_tags_list(FILE *out) +{ + int i; + + fprintf(out, "tags = [\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\',\n", opcode_names[i]); + } + fprintf(out, "];\n\n"); +} + +static void gen_enc_ext_spaces_table(FILE *out) +{ + fprintf(out, "enc_ext_spaces = {\n"); +#define DEF_EXT_SPACE(SPACEID, ENCSTR) \ + fprintf(out, "\t\'%s\' : \'%s\',\n", #SPACEID, ENCSTR); +#include "imported/encode.def" +#undef DEF_EXT_SPACE + fprintf(out, "};\n\n"); +} + +static void gen_subinsn_groupings_table(FILE *out) +{ + fprintf(out, "subinsn_groupings = {\n"); +#define DEF_PACKED32(TAG, TYPEA, TYPEB, ENCSTR) \ + do { \ + fprintf(out, "\t\'%s\' : {\n", #TAG); \ + fprintf(out, "\t\t\'name\' : \'%s\',\n", #TAG); \ + fprintf(out, "\t\t\'class_a\' : \'%s\',\n", #TYPEA); \ + fprintf(out, "\t\t\'class_b\' : \'%s\',\n", #TYPEB); \ + fprintf(out, "\t\t\'enc\' : \'%s\',\n", ENCSTR); \ + fprintf(out, "\t},\n"); \ + } while (0); +#include "imported/encode.def" +#undef DEF_PACKED32 + fprintf(out, "};\n\n"); +} + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n"); + return -1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return -1; + } + + opcode_init(); + gen_iset_table(outfile); + gen_tags_list(outfile); + gen_enc_ext_spaces_table(outfile); + gen_subinsn_groupings_table(outfile); + + fclose(outfile); + return 0; +} From patchwork Tue Aug 18 15:50:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4963CC433E1 for ; Tue, 18 Aug 2020 15:58:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0435B20897 for ; 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envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson --- target/hexagon/dectree.py | 352 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 352 insertions(+) create mode 100755 target/hexagon/dectree.py diff --git a/target/hexagon/dectree.py b/target/hexagon/dectree.py new file mode 100755 index 0000000..47a05a3 --- /dev/null +++ b/target/hexagon/dectree.py @@ -0,0 +1,352 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import io +import re + +import sys +import iset + +encs = {tag : ''.join(reversed(iset.iset[tag]['enc'].replace(' ', ''))) + for tag in iset.tags if iset.iset[tag]['enc'] != 'MISSING ENCODING'} + +enc_classes = set([iset.iset[tag]['enc_class'] for tag in encs.keys()]) +subinsn_enc_classes = \ + set([enc_class for enc_class in enc_classes \ + if enc_class.startswith('SUBINSN_')]) +ext_enc_classes = \ + set([enc_class for enc_class in enc_classes \ + if enc_class not in ('NORMAL', '16BIT') and \ + not enc_class.startswith('SUBINSN_')]) + +try: + subinsn_groupings = iset.subinsn_groupings +except AttributeError: + subinsn_groupings = {} + +for (tag, subinsn_grouping) in subinsn_groupings.items(): + encs[tag] = ''.join(reversed(subinsn_grouping['enc'].replace(' ', ''))) + +dectree_normal = {'leaves' : set()} +dectree_16bit = {'leaves' : set()} +dectree_subinsn_groupings = {'leaves' : set()} +dectree_subinsns = {name : {'leaves' : set()} for name in subinsn_enc_classes} +dectree_extensions = {name : {'leaves' : set()} for name in ext_enc_classes} + +for tag in encs.keys(): + if tag in subinsn_groupings: + dectree_subinsn_groupings['leaves'].add(tag) + continue + enc_class = iset.iset[tag]['enc_class'] + if enc_class.startswith('SUBINSN_'): + if len(encs[tag]) != 32: + encs[tag] = encs[tag] + '0' * (32 - len(encs[tag])) + dectree_subinsns[enc_class]['leaves'].add(tag) + elif enc_class == '16BIT': + if len(encs[tag]) != 16: + raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' + + 'width of 16 bits!'.format(tag, enc_class)) + dectree_16bit['leaves'].add(tag) + else: + if len(encs[tag]) != 32: + raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' + + 'width of 32 bits!'.format(tag, enc_class)) + if enc_class == 'NORMAL': + dectree_normal['leaves'].add(tag) + else: + dectree_extensions[enc_class]['leaves'].add(tag) + +faketags = set() +for (tag, enc) in iset.enc_ext_spaces.items(): + faketags.add(tag) + encs[tag] = ''.join(reversed(enc.replace(' ', ''))) + dectree_normal['leaves'].add(tag) + +faketags |= set(subinsn_groupings.keys()) + +def every_bit_counts(bitset): + for i in range(1, len(next(iter(bitset)))): + if len(set([bits[:i] + bits[i+1:] for bits in bitset])) == len(bitset): + return False + return True + +def auto_separate(node): + tags = node['leaves'] + if len(tags) <= 1: + return + enc_width = len(encs[next(iter(tags))]) + opcode_bit_for_all = \ + [all([encs[tag][i] in '01' \ + for tag in tags]) for i in range(enc_width)] + opcode_bit_is_0_for_all = \ + [opcode_bit_for_all[i] and all([encs[tag][i] == '0' \ + for tag in tags]) for i in range(enc_width)] + opcode_bit_is_1_for_all = \ + [opcode_bit_for_all[i] and all([encs[tag][i] == '1' \ + for tag in tags]) for i in range(enc_width)] + differentiator_opcode_bit = \ + [opcode_bit_for_all[i] and \ + not (opcode_bit_is_0_for_all[i] or \ + opcode_bit_is_1_for_all[i]) \ + for i in range(enc_width)] + best_width = 0 + for width in range(4, 0, -1): + for lsb in range(enc_width - width, -1, -1): + bitset = set([encs[tag][lsb:lsb+width] for tag in tags]) + if all(differentiator_opcode_bit[lsb:lsb+width]) and \ + (len(bitset) == len(tags) or every_bit_counts(bitset)): + best_width = width + best_lsb = lsb + caught_all_tags = len(bitset) == len(tags) + break + if best_width != 0: + break + if best_width == 0: + raise Exception('Could not find a way to differentiate the encodings ' + + 'of the following tags:\n{}'.format('\n'.join(tags))) + if caught_all_tags: + for width in range(1, best_width): + for lsb in range(enc_width - width, -1, -1): + bitset = set([encs[tag][lsb:lsb+width] for tag in tags]) + if all(differentiator_opcode_bit[lsb:lsb+width]) and \ + len(bitset) == len(tags): + best_width = width + best_lsb = lsb + break + else: + continue + break + node['separator_lsb'] = best_lsb + node['separator_width'] = best_width + node['children'] = [] + for value in range(2 ** best_width): + child = {} + bits = ''.join(reversed('{:0{}b}'.format(value, best_width))) + child['leaves'] = \ + set([tag for tag in tags \ + if encs[tag][best_lsb:best_lsb+best_width] == bits]) + node['children'].append(child) + for child in node['children']: + auto_separate(child) + +auto_separate(dectree_normal) +auto_separate(dectree_16bit) +if subinsn_groupings: + auto_separate(dectree_subinsn_groupings) +for dectree_subinsn in dectree_subinsns.values(): + auto_separate(dectree_subinsn) +for dectree_ext in dectree_extensions.values(): + auto_separate(dectree_ext) + +for tag in faketags: + del encs[tag] + +def table_name(parents, node): + path = parents + [node] + root = path[0] + tag = next(iter(node['leaves'])) + if tag in subinsn_groupings: + enc_width = len(subinsn_groupings[tag]['enc'].replace(' ', '')) + else: + tag = next(iter(node['leaves'] - faketags)) + enc_width = len(encs[tag]) + determining_bits = ['_'] * enc_width + for (parent, child) in zip(path[:-1], path[1:]): + lsb = parent['separator_lsb'] + width = parent['separator_width'] + value = parent['children'].index(child) + determining_bits[lsb:lsb+width] = \ + list(reversed('{:0{}b}'.format(value, width))) + if tag in subinsn_groupings: + name = 'DECODE_ROOT_EE' + else: + enc_class = iset.iset[tag]['enc_class'] + if enc_class in ext_enc_classes: + name = 'DECODE_EXT_{}'.format(enc_class) + elif enc_class in subinsn_enc_classes: + name = 'DECODE_SUBINSN_{}'.format(enc_class) + else: + name = 'DECODE_ROOT_{}'.format(enc_width) + if node != root: + name += '_' + ''.join(reversed(determining_bits)) + return name + +def print_node(f, node, parents): + if len(node['leaves']) <= 1: + return + name = table_name(parents, node) + lsb = node['separator_lsb'] + width = node['separator_width'] + print('DECODE_NEW_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\ + format(name, 2 ** width, lsb, width), file=f) + for child in node['children']: + if len(child['leaves']) == 0: + print('INVALID()', file=f) + elif len(child['leaves']) == 1: + (tag,) = child['leaves'] + if tag in subinsn_groupings: + class_a = subinsn_groupings[tag]['class_a'] + class_b = subinsn_groupings[tag]['class_b'] + enc = subinsn_groupings[tag]['enc'].replace(' ', '') + if 'RESERVED' in tag: + print('INVALID()', file=f) + else: + print('SUBINSNS({},{},{},"{}")'.\ + format(tag, class_a, class_b, enc), file=f) + elif tag in iset.enc_ext_spaces: + enc = iset.enc_ext_spaces[tag].replace(' ', '') + print('EXTSPACE({},"{}")'.format(tag, enc), file=f) + else: + enc = ''.join(reversed(encs[tag])) + print('TERMINAL({},"{}")'.format(tag, enc), file=f) + else: + print('TABLE_LINK({})'.format(table_name(parents + [node], child)), + file=f) + print('DECODE_END_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\ + format(name, 2 ** width, lsb, width), file=f) + print(file=f) + parents.append(node) + for child in node['children']: + print_node(f, child, parents) + parents.pop() + +def print_tree(f, tree): + print_node(f, tree, []) + +def print_match_info(f): + for tag in sorted(encs.keys(), key=iset.tags.index): + enc = ''.join(reversed(encs[tag])) + mask = int(re.sub(r'[^1]', r'0', enc.replace('0', '1')), 2) + match = int(re.sub(r'[^01]', r'0', enc), 2) + suffix = '' + print('DECODE{}_MATCH_INFO({},0x{:x}U,0x{:x}U)'.\ + format(suffix, tag, mask, match), file=f) + +regre = re.compile( + r'((? 1: + raise Exception('Tag "{}" has split register field!'.\ + format(tag)) + reg_enc_field = reg_enc_fields[0] + if 2 ** len(reg_enc_field) != reg_num_choices: + raise Exception('Tag "{}" has incorrect register field width!'.\ + format(tag)) + print(' DECODE_REG({},{},{})'.\ + format(regno, len(reg_enc_field), enc.index(reg_enc_field)), + file=f) + if reg_type in num_registers and \ + reg_num_choices != num_registers[reg_type]: + print(' DECODE_MAPPED_REG({},{})'.\ + format(regno, reg_mapping), file=f) + regno += 1 + def implicit_register_key(reg): + return implicit_registers[reg] + for reg in sorted( + set([r for r in (iset.iset[tag]['rregs'].split(',') + \ + iset.iset[tag]['wregs'].split(',')) \ + if r in implicit_registers]), key=implicit_register_key): + print(' DECODE_IMPL_REG({},{})'.\ + format(regno, implicit_registers[reg]), file=f) + regno += 1 + if imms and imms[0][0].isupper(): + imms = reversed(imms) + for imm in imms: + if imm[0].isupper(): + immno = 1 + else: + immno = 0 + imm_type = imm[0] + imm_width = int(imm[1]) + imm_shift = imm[2] + if imm_shift: + imm_shift = int(imm_shift) + else: + imm_shift = 0 + if imm_type.islower(): + imm_letter = 'i' + else: + imm_letter = 'I' + remainder = imm_width + for m in reversed(list(re.finditer(imm_letter + '+', enc))): + remainder -= m.end() - m.start() + print(' DECODE_IMM({},{},{},{})'.\ + format(immno, m.end() - m.start(), m.start(), remainder), + file=f) + if remainder != 0: + if imm[2]: + imm[2] = ':' + imm[2] + raise Exception('Tag "{}" has an incorrect number of ' + \ + 'encoding bits for immediate "{}"'.\ + format(tag, ''.join(imm))) + if imm_type.lower() in 'sr': + print(' DECODE_IMM_SXT({},{})'.\ + format(immno, imm_width), file=f) + if imm_type.lower() == 'n': + print(' DECODE_IMM_NEG({},{})'.\ + format(immno, imm_width), file=f) + if imm_shift: + print(' DECODE_IMM_SHIFT({},{})'.\ + format(immno, imm_shift), file=f) + print(')', file=f) + +if __name__ == '__main__': + f = io.StringIO() + print_tree(f, dectree_normal) + print_tree(f, dectree_16bit) + if subinsn_groupings: + print_tree(f, dectree_subinsn_groupings) + for (name, dectree_subinsn) in sorted(dectree_subinsns.items()): + print_tree(f, dectree_subinsn) + for (name, dectree_ext) in sorted(dectree_extensions.items()): + print_tree(f, dectree_ext) + print_match_info(f) + print_op_info(f) + open('dectree_generated.h', 'w').write(f.getvalue()) From patchwork Tue Aug 18 15:50:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26EF7C433E1 for ; Tue, 18 Aug 2020 16:09:29 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D753A2076E for ; Tue, 18 Aug 2020 16:09:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail 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Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 25/34] Hexagon (target/hexagon) macros to interface with the generator Date: Tue, 18 Aug 2020 10:50:38 -0500 Message-Id: <1597765847-16637-26-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Various forms of declare, read, write, free Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 364 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 target/hexagon/macros.h diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h new file mode 100644 index 0000000..5582dcb --- /dev/null +++ b/target/hexagon/macros.h @@ -0,0 +1,364 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_MACROS_H +#define HEXAGON_MACROS_H + +#include "qemu.h" +#include "cpu.h" +#include "hex_regs.h" +#include "reg_fields.h" + +#ifdef QEMU_GENERATE +#define DECL_REG(NAME, NUM, X, OFF) \ + TCGv NAME = tcg_temp_local_new(); \ + int NUM = REGNO(X) + OFF + +#define DECL_REG_WRITABLE(NAME, NUM, X, OFF) \ + TCGv NAME = tcg_temp_local_new(); \ + int NUM = REGNO(X) + OFF; \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + if (is_predicated && !is_preloaded(ctx, NUM)) { \ + tcg_gen_mov_tl(hex_new_value[NUM], hex_gpr[NUM]); \ + } \ + } while (0) +/* + * For read-only temps, avoid allocating and freeing + */ +#define DECL_REG_READONLY(NAME, NUM, X, OFF) \ + TCGv NAME; \ + int NUM = REGNO(X) + OFF + +#define DECL_RREG_d(NAME, NUM, X, OFF) \ + DECL_REG_WRITABLE(NAME, NUM, X, OFF) +#define DECL_RREG_e(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) +#define DECL_RREG_s(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_RREG_t(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_RREG_u(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_RREG_v(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_RREG_x(NAME, NUM, X, OFF) \ + DECL_REG_WRITABLE(NAME, NUM, X, OFF) +#define DECL_RREG_y(NAME, NUM, X, OFF) \ + DECL_REG_WRITABLE(NAME, NUM, X, OFF) + +#define DECL_PREG_d(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) +#define DECL_PREG_e(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) +#define DECL_PREG_s(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_PREG_t(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_PREG_u(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_PREG_v(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_PREG_x(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) +#define DECL_PREG_y(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) + +#define DECL_CREG_d(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) +#define DECL_CREG_s(NAME, NUM, X, OFF) \ + DECL_REG(NAME, NUM, X, OFF) + +#define DECL_MREG_u(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) + +#define DECL_NEW_NREG_s(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_NEW_NREG_t(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) + +#define DECL_NEW_PREG_t(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_NEW_PREG_u(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) +#define DECL_NEW_PREG_v(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) + +#define DECL_NEW_OREG_s(NAME, NUM, X, OFF) \ + DECL_REG_READONLY(NAME, NUM, X, OFF) + +#define DECL_PAIR(NAME, NUM, X, OFF) \ + TCGv_i64 NAME = tcg_temp_local_new_i64(); \ + size1u_t NUM = REGNO(X) + OFF + +#define DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) \ + TCGv_i64 NAME = tcg_temp_local_new_i64(); \ + size1u_t NUM = REGNO(X) + OFF; \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + if (is_predicated) { \ + if (!is_preloaded(ctx, NUM)) { \ + tcg_gen_mov_tl(hex_new_value[NUM], hex_gpr[NUM]); \ + } \ + if (!is_preloaded(ctx, NUM + 1)) { \ + tcg_gen_mov_tl(hex_new_value[NUM + 1], hex_gpr[NUM + 1]); \ + } \ + } \ + } while (0) + +#define DECL_RREG_dd(NAME, NUM, X, OFF) \ + DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) +#define DECL_RREG_ss(NAME, NUM, X, OFF) \ + DECL_PAIR(NAME, NUM, X, OFF) +#define DECL_RREG_tt(NAME, NUM, X, OFF) \ + DECL_PAIR(NAME, NUM, X, OFF) +#define DECL_RREG_xx(NAME, NUM, X, OFF) \ + DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) +#define DECL_RREG_yy(NAME, NUM, X, OFF) \ + DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) + +#define DECL_CREG_dd(NAME, NUM, X, OFF) \ + DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) +#define DECL_CREG_ss(NAME, NUM, X, OFF) \ + DECL_PAIR(NAME, NUM, X, OFF) + +#define DECL_IMM(NAME, X) \ + int NAME = IMMNO(X); \ + do { \ + NAME = NAME; \ + } while (0) +#define DECL_TCG_IMM(TCG_NAME, VAL) \ + TCGv TCG_NAME = tcg_const_tl(VAL) + +#define DECL_EA \ + TCGv EA; \ + do { \ + if (GET_ATTRIB(insn->opcode, A_CONDEXEC)) { \ + EA = tcg_temp_local_new(); \ + } else { \ + EA = tcg_temp_new(); \ + } \ + } while (0) + +#define LOG_REG_WRITE(RNUM, VAL)\ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_reg_write(RNUM, VAL, insn->slot, is_predicated); \ + ctx_log_reg_write(ctx, (RNUM)); \ + } while (0) + +#define LOG_PRED_WRITE(PNUM, VAL) \ + do { \ + gen_log_pred_write(PNUM, VAL); \ + ctx_log_pred_write(ctx, (PNUM)); \ + } while (0) + +#define FREE_REG(NAME) \ + tcg_temp_free(NAME) +#define FREE_REG_READONLY(NAME) \ + /* Nothing */ + +#define FREE_RREG_d(NAME) FREE_REG(NAME) +#define FREE_RREG_e(NAME) FREE_REG(NAME) +#define FREE_RREG_s(NAME) FREE_REG_READONLY(NAME) +#define FREE_RREG_t(NAME) FREE_REG_READONLY(NAME) +#define FREE_RREG_u(NAME) FREE_REG_READONLY(NAME) +#define FREE_RREG_v(NAME) FREE_REG_READONLY(NAME) +#define FREE_RREG_x(NAME) FREE_REG(NAME) +#define FREE_RREG_y(NAME) FREE_REG(NAME) + +#define FREE_PREG_d(NAME) FREE_REG(NAME) +#define FREE_PREG_e(NAME) FREE_REG(NAME) +#define FREE_PREG_s(NAME) FREE_REG_READONLY(NAME) +#define FREE_PREG_t(NAME) FREE_REG_READONLY(NAME) +#define FREE_PREG_u(NAME) FREE_REG_READONLY(NAME) +#define FREE_PREG_v(NAME) FREE_REG_READONLY(NAME) +#define FREE_PREG_x(NAME) FREE_REG(NAME) + +#define FREE_CREG_d(NAME) FREE_REG(NAME) +#define FREE_CREG_s(NAME) FREE_REG_READONLY(NAME) + +#define FREE_MREG_u(NAME) FREE_REG_READONLY(NAME) + +#define FREE_NEW_NREG_s(NAME) FREE_REG(NAME) +#define FREE_NEW_NREG_t(NAME) FREE_REG(NAME) + +#define FREE_NEW_PREG_t(NAME) FREE_REG_READONLY(NAME) +#define FREE_NEW_PREG_u(NAME) FREE_REG_READONLY(NAME) +#define FREE_NEW_PREG_v(NAME) FREE_REG_READONLY(NAME) + +#define FREE_NEW_OREG_s(NAME) FREE_REG(NAME) + +#define FREE_REG_PAIR(NAME) \ + tcg_temp_free_i64(NAME) + +#define FREE_RREG_dd(NAME) FREE_REG_PAIR(NAME) +#define FREE_RREG_ss(NAME) FREE_REG_PAIR(NAME) +#define FREE_RREG_tt(NAME) FREE_REG_PAIR(NAME) +#define FREE_RREG_xx(NAME) FREE_REG_PAIR(NAME) +#define FREE_RREG_yy(NAME) FREE_REG_PAIR(NAME) + +#define FREE_CREG_dd(NAME) FREE_REG_PAIR(NAME) +#define FREE_CREG_ss(NAME) FREE_REG_PAIR(NAME) + +#define FREE_IMM(NAME) /* nothing */ +#define FREE_TCG_IMM(NAME) tcg_temp_free(NAME) + +#define FREE_EA \ + tcg_temp_free(EA) +#else +#define LOG_REG_WRITE(RNUM, VAL)\ + log_reg_write(env, RNUM, VAL, slot) +#define LOG_PRED_WRITE(RNUM, VAL)\ + log_pred_write(env, RNUM, VAL) +#endif + +#define SLOT_WRAP(CODE) \ + do { \ + TCGv slot = tcg_const_tl(insn->slot); \ + CODE; \ + tcg_temp_free(slot); \ + } while (0) + +#define PART1_WRAP(CODE) \ + do { \ + TCGv part1 = tcg_const_tl(insn->part1); \ + CODE; \ + tcg_temp_free(part1); \ + } while (0) + +#define MARK_LATE_PRED_WRITE(RNUM) /* Not modelled in qemu */ + +#define REGNO(NUM) (insn->regno[NUM]) +#define IMMNO(NUM) (insn->immed[NUM]) + +#ifdef QEMU_GENERATE +#define READ_REG(dest, NUM) \ + gen_read_reg(dest, NUM) +#define READ_REG_READONLY(dest, NUM) \ + do { dest = hex_gpr[NUM]; } while (0) + +#define READ_RREG_s(dest, NUM) \ + READ_REG_READONLY(dest, NUM) +#define READ_RREG_t(dest, NUM) \ + READ_REG_READONLY(dest, NUM) +#define READ_RREG_u(dest, NUM) \ + READ_REG_READONLY(dest, NUM) +#define READ_RREG_x(dest, NUM) \ + READ_REG(dest, NUM) +#define READ_RREG_y(dest, NUM) \ + READ_REG(dest, NUM) + +#define READ_OREG_s(dest, NUM) \ + READ_REG_READONLY(dest, NUM) + +#define READ_CREG_s(dest, NUM) \ + do { \ + if ((NUM) + HEX_REG_SA0 == HEX_REG_P3_0) { \ + gen_read_p3_0(dest); \ + } else { \ + READ_REG_READONLY(dest, ((NUM) + HEX_REG_SA0)); \ + } \ + } while (0) + +#define READ_MREG_u(dest, NUM) \ + do { \ + READ_REG_READONLY(dest, ((NUM) + HEX_REG_M0)); \ + dest = dest; \ + } while (0) +#else +#define READ_REG(NUM) \ + (env->gpr[(NUM)]) +#endif + +#ifdef QEMU_GENERATE +#define READ_REG_PAIR(tmp, NUM) \ + tcg_gen_concat_i32_i64(tmp, hex_gpr[NUM], hex_gpr[(NUM) + 1]) +#define READ_RREG_ss(tmp, NUM) READ_REG_PAIR(tmp, NUM) +#define READ_RREG_tt(tmp, NUM) READ_REG_PAIR(tmp, NUM) +#define READ_RREG_xx(tmp, NUM) READ_REG_PAIR(tmp, NUM) +#define READ_RREG_yy(tmp, NUM) READ_REG_PAIR(tmp, NUM) + +#define READ_CREG_PAIR(tmp, i) \ + READ_REG_PAIR(tmp, ((i) + HEX_REG_SA0)) +#define READ_CREG_ss(tmp, i) READ_CREG_PAIR(tmp, i) +#endif + +#ifdef QEMU_GENERATE +#define READ_PREG(dest, NUM) gen_read_preg(dest, (NUM)) +#define READ_PREG_READONLY(dest, NUM) do { dest = hex_pred[NUM]; } while (0) + +#define READ_PREG_s(dest, NUM) READ_PREG_READONLY(dest, NUM) +#define READ_PREG_t(dest, NUM) READ_PREG_READONLY(dest, NUM) +#define READ_PREG_u(dest, NUM) READ_PREG_READONLY(dest, NUM) +#define READ_PREG_v(dest, NUM) READ_PREG_READONLY(dest, NUM) +#define READ_PREG_x(dest, NUM) READ_PREG(dest, NUM) + +#define READ_NEW_PREG(pred, PNUM) \ + do { pred = hex_new_pred_value[PNUM]; } while (0) +#define READ_NEW_PREG_t(pred, PNUM) READ_NEW_PREG(pred, PNUM) +#define READ_NEW_PREG_u(pred, PNUM) READ_NEW_PREG(pred, PNUM) +#define READ_NEW_PREG_v(pred, PNUM) READ_NEW_PREG(pred, PNUM) + +#define READ_NEW_REG(tmp, i) \ + do { tmp = tcg_const_tl(i); } while (0) +#define READ_NEW_NREG_s(tmp, i) READ_NEW_REG(tmp, i) +#define READ_NEW_NREG_t(tmp, i) READ_NEW_REG(tmp, i) +#define READ_NEW_OREG_s(tmp, i) READ_NEW_REG(tmp, i) +#else +#define READ_PREG(NUM) (env->pred[NUM]) +#endif + + +#define WRITE_RREG(NUM, VAL) LOG_REG_WRITE(NUM, VAL) +#define WRITE_RREG_d(NUM, VAL) LOG_REG_WRITE(NUM, VAL) +#define WRITE_RREG_e(NUM, VAL) LOG_REG_WRITE(NUM, VAL) +#define WRITE_RREG_x(NUM, VAL) LOG_REG_WRITE(NUM, VAL) +#define WRITE_RREG_y(NUM, VAL) LOG_REG_WRITE(NUM, VAL) + +#define WRITE_PREG(NUM, VAL) LOG_PRED_WRITE(NUM, VAL) +#define WRITE_PREG_d(NUM, VAL) LOG_PRED_WRITE(NUM, VAL) +#define WRITE_PREG_e(NUM, VAL) LOG_PRED_WRITE(NUM, VAL) +#define WRITE_PREG_x(NUM, VAL) LOG_PRED_WRITE(NUM, VAL) + +#ifdef QEMU_GENERATE +#define WRITE_CREG(i, tmp) \ + do { \ + if (i + HEX_REG_SA0 == HEX_REG_P3_0) { \ + gen_write_p3_0(tmp); \ + } else { \ + WRITE_RREG((i) + HEX_REG_SA0, tmp); \ + } \ + } while (0) +#define WRITE_CREG_d(NUM, VAL) WRITE_CREG(NUM, VAL) + +#define WRITE_CREG_PAIR(i, tmp) WRITE_REG_PAIR((i) + HEX_REG_SA0, tmp) +#define WRITE_CREG_dd(NUM, VAL) WRITE_CREG_PAIR(NUM, VAL) + +#define WRITE_REG_PAIR(NUM, VAL) \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_reg_write_pair(NUM, VAL, insn->slot, is_predicated); \ + ctx_log_reg_write(ctx, (NUM)); \ + ctx_log_reg_write(ctx, (NUM) + 1); \ + } while (0) + +#define WRITE_RREG_dd(NUM, VAL) WRITE_REG_PAIR(NUM, VAL) +#define WRITE_RREG_xx(NUM, VAL) WRITE_REG_PAIR(NUM, VAL) +#define WRITE_RREG_yy(NUM, VAL) WRITE_REG_PAIR(NUM, VAL) +#endif + From patchwork Tue Aug 18 15:50:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49FAC433DF for ; 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18 Aug 2020 08:50:59 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id E1DA9EB5; Tue, 18 Aug 2020 10:50:58 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 31/34] Hexagon (target/hexagon) translation Date: Tue, 18 Aug 2020 10:50:44 -0500 Message-Id: <1597765847-16637-32-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 103 +++++++ target/hexagon/translate.c | 730 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 833 insertions(+) create mode 100644 target/hexagon/translate.h create mode 100644 target/hexagon/translate.c diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h new file mode 100644 index 0000000..144140f --- /dev/null +++ b/target/hexagon/translate.h @@ -0,0 +1,103 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_TRANSLATE_H +#define HEXAGON_TRANSLATE_H + +#include "cpu.h" +#include "exec/translator.h" +#include "tcg/tcg-op.h" +#include "internal.h" + +typedef struct DisasContext { + DisasContextBase base; + uint32_t mem_idx; + int reg_log[REG_WRITES_MAX]; + int reg_log_idx; + int preg_log[PRED_WRITES_MAX]; + int preg_log_idx; + uint8_t store_width[STORES_MAX]; +} DisasContext; + +static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) +{ +#if HEX_DEBUG + int i; + for (i = 0; i < ctx->reg_log_idx; i++) { + if (ctx->reg_log[i] == rnum) { + HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); + } + } +#endif + ctx->reg_log[ctx->reg_log_idx] = rnum; + ctx->reg_log_idx++; +} + +static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) +{ + ctx->preg_log[ctx->preg_log_idx] = pnum; + ctx->preg_log_idx++; +} + +static inline bool is_preloaded(DisasContext *ctx, int num) +{ + int i; + for (i = 0; i < ctx->reg_log_idx; i++) { + if (ctx->reg_log[i] == num) { + return true; + } + } + return false; +} + +extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_pred[NUM_PREGS]; +extern TCGv hex_next_PC; +extern TCGv hex_this_PC; +extern TCGv hex_slot_cancelled; +extern TCGv hex_branch_taken; +extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_new_pred_value[NUM_PREGS]; +extern TCGv hex_pred_written; +extern TCGv hex_store_addr[STORES_MAX]; +extern TCGv hex_store_width[STORES_MAX]; +extern TCGv hex_store_val32[STORES_MAX]; +extern TCGv_i64 hex_store_val64[STORES_MAX]; +extern TCGv hex_dczero_addr; +extern TCGv hex_llsc_addr; +extern TCGv hex_llsc_val; +extern TCGv_i64 hex_llsc_val_i64; + +static inline void gen_slot_cancelled_check(TCGv check, int slot_num) +{ + TCGv mask = tcg_const_tl(1 << slot_num); + TCGv one = tcg_const_tl(1); + TCGv zero = tcg_const_tl(0); + + tcg_gen_and_tl(mask, hex_slot_cancelled, mask); + tcg_gen_movcond_tl(TCG_COND_NE, check, mask, zero, one, zero); + + tcg_temp_free(one); + tcg_temp_free(zero); + tcg_temp_free(mask); +} + +extern void gen_exception(int excp); +extern void gen_exception_debug(void); + +#endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c new file mode 100644 index 0000000..9e3f4af --- /dev/null +++ b/target/hexagon/translate.c @@ -0,0 +1,730 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define QEMU_GENERATE +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/log.h" +#include "internal.h" +#include "attribs.h" +#include "insn.h" +#include "decode.h" +#include "translate.h" +#include "printinsn.h" + +TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; +TCGv hex_pred[NUM_PREGS]; +TCGv hex_next_PC; +TCGv hex_this_PC; +TCGv hex_slot_cancelled; +TCGv hex_branch_taken; +TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +#if HEX_DEBUG +TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; +#endif +TCGv hex_new_pred_value[NUM_PREGS]; +TCGv hex_pred_written; +TCGv hex_store_addr[STORES_MAX]; +TCGv hex_store_width[STORES_MAX]; +TCGv hex_store_val32[STORES_MAX]; +TCGv_i64 hex_store_val64[STORES_MAX]; +TCGv hex_pkt_has_store_s1; +TCGv hex_dczero_addr; +TCGv hex_llsc_addr; +TCGv hex_llsc_val; +TCGv_i64 hex_llsc_val_i64; + +static const char * const hexagon_prednames[] = { + "p0", "p1", "p2", "p3" +}; + +void gen_exception(int excp) +{ + TCGv_i32 helper_tmp = tcg_const_i32(excp); + gen_helper_raise_exception(cpu_env, helper_tmp); + tcg_temp_free_i32(helper_tmp); +} + +void gen_exception_debug(void) +{ + gen_exception(EXCP_DEBUG); +} + +#if HEX_DEBUG +#define PACKET_BUFFER_LEN 1028 +static void print_pkt(packet_t *pkt) +{ + char buf[PACKET_BUFFER_LEN]; + snprint_a_pkt(buf, PACKET_BUFFER_LEN, pkt); + HEX_DEBUG_LOG("%s", buf); +} +#define HEX_DEBUG_PRINT_PKT(pkt) print_pkt(pkt) +#else +#define HEX_DEBUG_PRINT_PKT(pkt) /* nothing */ +#endif + +static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, + uint32_t words[]) +{ + bool found_end = false; + int max_words; + int nwords; + int i; + + /* Make sure we don't cross a page boundary */ + max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); + if (max_words < PACKET_WORDS_MAX) { + /* Might cross a page boundary */ + if (ctx->base.num_insns == 1) { + /* OK if it's the first packet in the TB */ + max_words = PACKET_WORDS_MAX; + } + } else { + max_words = PACKET_WORDS_MAX; + } + + memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); + for (nwords = 0; !found_end && nwords < max_words; nwords++) { + words[nwords] = cpu_ldl_code(env, + ctx->base.pc_next + nwords * sizeof(uint32_t)); + found_end = is_packet_end(words[nwords]); + } + if (!found_end) { + if (nwords == PACKET_WORDS_MAX) { + /* Read too many words without finding the end */ + gen_exception(HEX_EXCP_INVALID_PACKET); + ctx->base.is_jmp = DISAS_NORETURN; + return 0; + } + /* Crosses page boundary - defer to next TB */ + ctx->base.is_jmp = DISAS_TOO_MANY; + return 0; + } + + HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG(" words = { "); + for (i = 0; i < nwords; i++) { + HEX_DEBUG_LOG("0x%x, ", words[i]); + } + HEX_DEBUG_LOG("}\n"); + + return nwords; +} + +static void gen_start_packet(DisasContext *ctx, packet_t *pkt) +{ + target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; + int i; + + /* Clear out the disassembly context */ + ctx->reg_log_idx = 0; + ctx->preg_log_idx = 0; + for (i = 0; i < STORES_MAX; i++) { + ctx->store_width[i] = 0; + } + tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); + +#if HEX_DEBUG + /* Handy place to set a breakpoint before the packet executes */ + gen_helper_debug_start_packet(cpu_env); + tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); +#endif + + /* Initialize the runtime state for packet semantics */ + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + tcg_gen_movi_tl(hex_slot_cancelled, 0); + if (pkt->pkt_has_cof) { + tcg_gen_movi_tl(hex_branch_taken, 0); + tcg_gen_movi_tl(hex_next_PC, next_PC); + } + tcg_gen_movi_tl(hex_pred_written, 0); +} + +/* + * The LOG_*_WRITE macros mark most of the writes in a packet + * However, there are some implicit writes marked as attributes + * of the applicable instructions. + */ +static void mark_implicit_reg_write(DisasContext *ctx, insn_t *insn, + int attrib, int rnum) +{ + if (GET_ATTRIB(insn->opcode, attrib)) { + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); + if (is_predicated && !is_preloaded(ctx, rnum)) { + tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); + } + + ctx->reg_log[ctx->reg_log_idx] = rnum; + ctx->reg_log_idx++; + } +} + +static void mark_implicit_pred_write(DisasContext *ctx, insn_t *insn, + int attrib, int pnum) +{ + if (GET_ATTRIB(insn->opcode, attrib)) { + ctx->preg_log[ctx->preg_log_idx] = pnum; + ctx->preg_log_idx++; + } +} + +static void mark_implicit_writes(DisasContext *ctx, insn_t *insn) +{ + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); + + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); +} + +static void gen_insn(CPUHexagonState *env, DisasContext *ctx, + insn_t *insn, packet_t *pkt) +{ + if (insn->generate) { + mark_implicit_writes(ctx, insn); + insn->generate(env, ctx, insn, pkt); + } else { + gen_exception(HEX_EXCP_INVALID_OPCODE); + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +/* + * Helpers for generating the packet commit + */ +static void gen_reg_writes(DisasContext *ctx) +{ + int i; + + for (i = 0; i < ctx->reg_log_idx; i++) { + int reg_num = ctx->reg_log[i]; + + tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); + } +} + +static void gen_pred_writes(DisasContext *ctx, packet_t *pkt) +{ + /* Early exit if the log is empty */ + if (!ctx->preg_log_idx) { + return; + } + + TCGv zero = tcg_const_tl(0); + TCGv control_reg = tcg_temp_new(); + TCGv pval = tcg_temp_new(); + int i; + + /* + * Only endloop instructions will conditionally + * write a predicate. If there are no endloop + * instructions, we can use the non-conditional + * write of the predicates. + */ + if (pkt->pkt_has_endloop) { + TCGv pred_written = tcg_temp_new(); + for (i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + + tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); + tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], + pred_written, zero, + hex_new_pred_value[pred_num], + hex_pred[pred_num]); + } + tcg_temp_free(pred_written); + } else { + for (i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); +#if HEX_DEBUG + /* Do this so HELPER(debug_commit_end) will know */ + tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pred_num); +#endif + } + } + + tcg_temp_free(zero); + tcg_temp_free(control_reg); + tcg_temp_free(pval); +} + +#if HEX_DEBUG +static inline void gen_check_store_width(DisasContext *ctx, int slot_num) +{ + TCGv slot = tcg_const_tl(slot_num); + TCGv check = tcg_const_tl(ctx->store_width[slot_num]); + gen_helper_debug_check_store_width(cpu_env, slot, check); + tcg_temp_free(slot); + tcg_temp_free(check); +} +#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) \ + gen_check_store_width(ctx, slot_num) +#else +#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) /* nothing */ +#endif + +static void process_store(DisasContext *ctx, int slot_num) +{ + TCGv cancelled = tcg_temp_local_new(); + TCGLabel *label_end = gen_new_label(); + + /* Don't do anything if the slot was cancelled */ + gen_slot_cancelled_check(cancelled, slot_num); + tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); + { + int ctx_width = ctx->store_width[slot_num]; + TCGv address = tcg_temp_local_new(); + tcg_gen_mov_tl(address, hex_store_addr[slot_num]); + + /* + * If we know the width from the DisasContext, we can + * generate much cleaner code. + * Unfortunately, not all instructions execute the fSTORE + * macro during code generation. Anything that uses the + * generic helper will have this problem. Instructions + * that use fWRAP to generate proper TCG code will be OK. + */ + TCGv value; + TCGv_i64 value_i64; + TCGLabel *label_w2; + TCGLabel *label_w4; + TCGLabel *label_w8; + switch (ctx_width) { + case 1: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st8(value, address, ctx->mem_idx); + tcg_temp_free(value); + break; + case 2: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st16(value, address, ctx->mem_idx); + tcg_temp_free(value); + break; + case 4: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st32(value, address, ctx->mem_idx); + tcg_temp_free(value); + break; + case 8: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + value_i64 = tcg_temp_new_i64(); + tcg_gen_mov_i64(value_i64, hex_store_val64[slot_num]); + tcg_gen_qemu_st64(value_i64, address, ctx->mem_idx); + tcg_temp_free_i64(value_i64); + break; + default: + /* + * If we get to here, we don't know the width at + * TCG generation time, we'll generate branching + * based on the width at runtime. + */ + label_w2 = gen_new_label(); + label_w4 = gen_new_label(); + label_w8 = gen_new_label(); + TCGv width = tcg_temp_local_new(); + + tcg_gen_mov_tl(width, hex_store_width[slot_num]); + tcg_gen_brcondi_tl(TCG_COND_NE, width, 1, label_w2); + { + /* Width is 1 byte */ + TCGv value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st8(value, address, ctx->mem_idx); + tcg_gen_br(label_end); + tcg_temp_free(value); + } + gen_set_label(label_w2); + tcg_gen_brcondi_tl(TCG_COND_NE, width, 2, label_w4); + { + /* Width is 2 bytes */ + TCGv value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st16(value, address, ctx->mem_idx); + tcg_gen_br(label_end); + tcg_temp_free(value); + } + gen_set_label(label_w4); + tcg_gen_brcondi_tl(TCG_COND_NE, width, 4, label_w8); + { + /* Width is 4 bytes */ + TCGv value = tcg_temp_new(); + tcg_gen_mov_tl(value, hex_store_val32[slot_num]); + tcg_gen_qemu_st32(value, address, ctx->mem_idx); + tcg_gen_br(label_end); + tcg_temp_free(value); + } + gen_set_label(label_w8); + { + /* Width is 8 bytes */ + TCGv_i64 value = tcg_temp_new_i64(); + tcg_gen_mov_i64(value, hex_store_val64[slot_num]); + tcg_gen_qemu_st64(value, address, ctx->mem_idx); + tcg_gen_br(label_end); + tcg_temp_free_i64(value); + } + + tcg_temp_free(width); + } + tcg_temp_free(address); + } + gen_set_label(label_end); + + tcg_temp_free(cancelled); +} + +static void process_store_log(DisasContext *ctx, packet_t *pkt) +{ + /* + * When a packet has two stores, the hardware processes + * slot 1 and then slot 2. This will be important when + * the memory accesses overlap. + */ + if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { + process_store(ctx, 1); + } + if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { + process_store(ctx, 0); + } +} + +/* Zero out a 32-bit cache line */ +static void process_dczeroa(DisasContext *ctx, packet_t *pkt) +{ + if (pkt->pkt_has_dczeroa) { + /* Store 32 bytes of zero starting at (addr & ~0x1f) */ + TCGv addr = tcg_temp_new(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + + tcg_temp_free(addr); + tcg_temp_free_i64(zero); + } +} + +static bool process_change_of_flow(DisasContext *ctx, packet_t *pkt) +{ + if (pkt->pkt_has_cof) { + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + return true; + } + return false; +} + +static void gen_exec_counters(packet_t *pkt) +{ + int num_insns = pkt->num_insns; + int num_real_insns = 0; + int i; + + for (i = 0; i < num_insns; i++) { + if (!pkt->insn[i].is_endloop && + !pkt->insn[i].part1 && + !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { + num_real_insns++; + } + } + + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], + hex_gpr[HEX_REG_QEMU_PKT_CNT], 1); + if (num_real_insns) { + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], + hex_gpr[HEX_REG_QEMU_INSN_CNT], num_real_insns); + } +} + +static void gen_commit_packet(DisasContext *ctx, packet_t *pkt) +{ + bool end_tb = false; + + gen_reg_writes(ctx); + gen_pred_writes(ctx, pkt); + process_store_log(ctx, pkt); + process_dczeroa(ctx, pkt); + end_tb |= process_change_of_flow(ctx, pkt); + gen_exec_counters(pkt); +#if HEX_DEBUG + { + TCGv has_st0 = + tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); + TCGv has_st1 = + tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); + + /* Handy place to set a breakpoint at the end of execution */ + gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); + + tcg_temp_free(has_st0); + tcg_temp_free(has_st1); + } +#endif + + if (end_tb) { + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) +{ + uint32_t words[PACKET_WORDS_MAX]; + int nwords; + packet_t pkt; + int i; + + nwords = read_packet_words(env, ctx, words); + if (!nwords) { + return; + } + + if (decode_this(nwords, words, &pkt)) { + HEX_DEBUG_PRINT_PKT(&pkt); + gen_start_packet(ctx, &pkt); + for (i = 0; i < pkt.num_insns; i++) { + gen_insn(env, ctx, &pkt.insn[i], &pkt); + } + gen_commit_packet(ctx, &pkt); + ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; + } else { + gen_exception(HEX_EXCP_INVALID_PACKET); + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + ctx->mem_idx = MMU_USER_IDX; +} + +static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_debug(); + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + ctx->base.pc_next += 4; + return true; +} + + +static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUHexagonState *env = cpu->env_ptr; + + decode_and_translate_packet(env, ctx); + + if (ctx->base.is_jmp == DISAS_NEXT) { + target_ulong page_start; + + page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } + + /* + * The CPU log is used to compare against LLDB single stepping, + * so end the TLB after every packet. + */ + if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } +#if HEX_DEBUG + /* When debugging, only put one packet per TB */ + ctx->base.is_jmp = DISAS_TOO_MANY; +#endif + } +} + +static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { + case DISAS_TOO_MANY: + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + if (ctx->base.singlestep_enabled) { + gen_exception_debug(); + } else { + tcg_gen_exit_tb(NULL, 0); + } + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); + } +} + +static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + + +static const TranslatorOps hexagon_tr_ops = { + .init_disas_context = hexagon_tr_init_disas_context, + .tb_start = hexagon_tr_tb_start, + .insn_start = hexagon_tr_insn_start, + .breakpoint_check = hexagon_tr_breakpoint_check, + .translate_insn = hexagon_tr_translate_packet, + .tb_stop = hexagon_tr_tb_stop, + .disas_log = hexagon_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +{ + DisasContext ctx; + + translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); +} + +#define NAME_LEN 64 +static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; +#if HEX_DEBUG +static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; +#endif +static char new_pred_value_names[NUM_PREGS][NAME_LEN]; +static char store_addr_names[STORES_MAX][NAME_LEN]; +static char store_width_names[STORES_MAX][NAME_LEN]; +static char store_val32_names[STORES_MAX][NAME_LEN]; +static char store_val64_names[STORES_MAX][NAME_LEN]; + +void hexagon_translate_init(void) +{ + int i; + + opcode_init(); + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + hex_gpr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, gpr[i]), + hexagon_regnames[i]); + + snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); + hex_new_value[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value[i]), + new_value_names[i]); + +#if HEX_DEBUG + snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", + hexagon_regnames[i]); + hex_reg_written[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, reg_written[i]), + reg_written_names[i]); +#endif + } + for (i = 0; i < NUM_PREGS; i++) { + hex_pred[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pred[i]), + hexagon_prednames[i]); + + snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", + hexagon_prednames[i]); + hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_pred_value[i]), + new_pred_value_names[i]); + } + hex_pred_written = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pred_written), "pred_written"); + hex_next_PC = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, next_PC), "next_PC"); + hex_this_PC = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, this_PC), "this_PC"); + hex_slot_cancelled = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); + hex_branch_taken = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, branch_taken), "branch_taken"); + hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); + hex_dczero_addr = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); + hex_llsc_addr = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); + hex_llsc_val = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, llsc_val), "llsc_val"); + hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); + for (i = 0; i < STORES_MAX; i++) { + snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); + hex_store_addr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].va), + store_addr_names[i]); + + snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); + hex_store_width[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].width), + store_width_names[i]); + + snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); + hex_store_val32[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].data32), + store_val32_names[i]); + + snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); + hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].data64), + store_val64_names[i]); + } + + init_genptr(); +} From patchwork Tue Aug 18 15:50:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BC4DC433E3 for ; Tue, 18 Aug 2020 16:19:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83B922065D for ; Tue, 18 Aug 2020 16:19:05 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 18 Aug 2020 11:52:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765927; x=1629301927; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+ShBUvhTiiXPoYPJLfrd3X8rUDAI64Voo8bW9mTSNvk=; b=gdNXBOTRKst3ubi58HTInPZ+/EMovGqhLmXJAtL5D7IlJI1F9YYPvmcB iSSAs7fJswYCYItlvFIR/npovDhPXRmeLbgNoYl2ijhJEkTDaz9cym1Ru t9exaYh//Og5nfAG9t/ZeW0cQoKGshUyi6QXrCruRcZeTgAHKqVV1xV+o Y=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:51:01 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:59 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 8F9777BD; Tue, 18 Aug 2020 10:50:59 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 33/34] Hexagon (tests/tcg/hexagon) TCG tests Date: Tue, 18 Aug 2020 10:50:46 -0500 Message-Id: <1597765847-16637-34-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Add Hexagon-specific tests Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/atomics.c | 122 ++++++ tests/tcg/hexagon/clrtnew.c | 56 +++ tests/tcg/hexagon/dual_stores.c | 60 +++ tests/tcg/hexagon/exec_counters.c | 57 +++ tests/tcg/hexagon/mem_noshuf.c | 291 ++++++++++++++ tests/tcg/hexagon/misc.c | 293 ++++++++++++++ tests/tcg/hexagon/preg_alias.c | 106 +++++ tests/tcg/hexagon/pthread_cancel.c | 43 +++ tests/tcg/hexagon/sfminmax.c | 62 +++ tests/tcg/configure.sh | 4 +- tests/tcg/hexagon/Makefile.target | 49 +++ tests/tcg/hexagon/first.S | 57 +++ tests/tcg/hexagon/float_convs.ref | 748 ++++++++++++++++++++++++++++++++++++ tests/tcg/hexagon/float_madds.ref | 768 +++++++++++++++++++++++++++++++++++++ 14 files changed, 2715 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/atomics.c create mode 100644 tests/tcg/hexagon/clrtnew.c create mode 100644 tests/tcg/hexagon/dual_stores.c create mode 100644 tests/tcg/hexagon/exec_counters.c create mode 100644 tests/tcg/hexagon/mem_noshuf.c create mode 100644 tests/tcg/hexagon/misc.c create mode 100644 tests/tcg/hexagon/preg_alias.c create mode 100644 tests/tcg/hexagon/pthread_cancel.c create mode 100644 tests/tcg/hexagon/sfminmax.c create mode 100644 tests/tcg/hexagon/Makefile.target create mode 100644 tests/tcg/hexagon/first.S create mode 100644 tests/tcg/hexagon/float_convs.ref create mode 100644 tests/tcg/hexagon/float_madds.ref diff --git a/tests/tcg/hexagon/atomics.c b/tests/tcg/hexagon/atomics.c new file mode 100644 index 0000000..88d7450 --- /dev/null +++ b/tests/tcg/hexagon/atomics.c @@ -0,0 +1,122 @@ +#include +#include +#include +#include +#include +#include + +/* Using volatile because we are testing atomics */ +static inline int atomic_inc32(volatile int *x) +{ + int old, dummy; + __asm__ __volatile__( + "1: %0 = memw_locked(%2)\n\t" + " %1 = add(%0, #1)\n\t" + " memw_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline long long atomic_inc64(volatile long long *x) +{ + long long old, dummy; + __asm__ __volatile__( + "1: %0 = memd_locked(%2)\n\t" + " %1 = #1\n\t" + " %1 = add(%0, %1)\n\t" + " memd_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline int atomic_dec32(volatile int *x) +{ + int old, dummy; + __asm__ __volatile__( + "1: %0 = memw_locked(%2)\n\t" + " %1 = add(%0, #-1)\n\t" + " memw_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline long long atomic_dec64(volatile long long *x) +{ + long long old, dummy; + __asm__ __volatile__( + "1: %0 = memd_locked(%2)\n\t" + " %1 = #-1\n\t" + " %1 = add(%0, %1)\n\t" + " memd_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +#define LOOP_CNT 1000 +/* Using volatile because we are testing atomics */ +volatile int tick32 = 1; +/* Using volatile because we are testing atomics */ +volatile long long tick64 = 1; +int err; + +void *thread1_func(void *arg) +{ + int i; + + for (i = 0; i < LOOP_CNT; i++) { + atomic_inc32(&tick32); + atomic_dec64(&tick64); + } + return NULL; +} + +void *thread2_func(void *arg) +{ + int i; + for (i = 0; i < LOOP_CNT; i++) { + atomic_dec32(&tick32); + atomic_inc64(&tick64); + } + return NULL; +} + +void test_pthread(void) +{ + pthread_t tid1, tid2; + + pthread_create(&tid1, NULL, thread1_func, "hello1"); + pthread_create(&tid2, NULL, thread2_func, "hello2"); + pthread_join(tid1, NULL); + pthread_join(tid2, NULL); + + if (tick32 != 1) { + printf("ERROR: tick32 %d != 1\n", tick32); + err++; + } + if (tick64 != 1) { + printf("ERROR: tick64 %lld != 1\n", tick64); + err++; + } +} + +int main(int argc, char **argv) +{ + test_pthread(); + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/clrtnew.c b/tests/tcg/hexagon/clrtnew.c new file mode 100644 index 0000000..665c2b3 --- /dev/null +++ b/tests/tcg/hexagon/clrtnew.c @@ -0,0 +1,56 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +static inline int test_clrtnew(int arg1, int old_val) +{ + int ret; + asm volatile("r5 = %2\n\t" + "{\n\t" + "p0 = cmp.eq(%1, #1)\n\t" + "if (p0.new) r5=#0\n\t" + "}\n\t" + "%0 = r5\n\t" + : "=r"(ret) + : "r"(arg1), "r"(old_val) + : "p0", "r5"); + return ret; +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%d != 0x%d\n", val, expect); + err++; + } +} + +int main() +{ + int res; + + res = test_clrtnew(1, 7); + check(res, 0); + res = test_clrtnew(2, 7); + check(res, 7); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/dual_stores.c b/tests/tcg/hexagon/dual_stores.c new file mode 100644 index 0000000..ba81bc2 --- /dev/null +++ b/tests/tcg/hexagon/dual_stores.c @@ -0,0 +1,60 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * Make sure that two stores in the same packet honor proper + * semantics: slot 1 executes first, then slot 0. + * This is important when the addresses overlap. + */ +static inline void dual_stores(int *p, char *q, int x, char y) +{ + asm volatile("{\n\t" + " memw(%0) = %2\n\t" + " memb(%1) = %3\n\t" + "}\n" + :: "r"(p), "r"(q), "r"(x), "r"(y) + : "memory"); +} + +typedef union { + int word; + char byte; +} Dual; + +int err; + +static void check(Dual d, int expect) +{ + if (d.word != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", d.word, expect); + err++; + } +} + +int main() +{ + Dual d; + + d.word = ~0; + dual_stores(&d.word, &d.byte, 0x12345678, 0xff); + check(d, 0x123456ff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/exec_counters.c b/tests/tcg/hexagon/exec_counters.c new file mode 100644 index 0000000..36eae25 --- /dev/null +++ b/tests/tcg/hexagon/exec_counters.c @@ -0,0 +1,57 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Check the instruction counters in qemu + */ +#include + +int err; + +static void check(const char *name, int val, int expect) +{ + if (val != expect) { + printf("ERROR: %s %d != %d\n", name, val, expect); + err++; + } +} + +int main() +{ + int pkt, insn; + + asm volatile("r2 = #0\n\t" + "c23 = r2\n\t" + "c22 = r2\n\t" + "c21 = r2\n\t" + "c20 = r2\n\t" + "r2 = #7\n\t" + "loop0(1f, #3)\n\t" + "1:\n\t" + " { p0 = cmp.eq(r2,#5); if (p0.new) jump:nt 2f }\n\t" + " {r0 = r1; r1 = r0 }:endloop0\n\t" + "2:\n\t" + "%[pkt] = c20\n\t" + "%[insn] = c21\n\t" + : [pkt] "=r"(pkt), [insn] "=r"(insn) + : : "r0", "r1", "r2", "sa0", "lc0", "p0"); + + check("Packet", pkt, 9); + check("Instruction", insn, 14); + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/mem_noshuf.c b/tests/tcg/hexagon/mem_noshuf.c new file mode 100644 index 0000000..f7bf2e3 --- /dev/null +++ b/tests/tcg/hexagon/mem_noshuf.c @@ -0,0 +1,291 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * Make sure that the :mem_noshuf packet attribute is honored. + * This is important when the addresses overlap. + * The store instruction in slot 1 effectively executes first, + * followed by the load instruction in slot 0. + */ + +#define MEM_NOSHUF32(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ +static inline unsigned int NAME(ST_TYPE * p, LD_TYPE * q, ST_TYPE x) \ +{ \ + unsigned int ret; \ + asm volatile("{\n\t" \ + " " #ST_OP "(%1) = %3\n\t" \ + " %0 = " #LD_OP "(%2)\n\t" \ + "}:mem_noshuf\n" \ + : "=r"(ret) \ + : "r"(p), "r"(q), "r"(x) \ + : "memory"); \ + return ret; \ +} + +#define MEM_NOSHUF64(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ +static inline unsigned long long NAME(ST_TYPE * p, LD_TYPE * q, ST_TYPE x) \ +{ \ + unsigned long long ret; \ + asm volatile("{\n\t" \ + " " #ST_OP "(%1) = %3\n\t" \ + " %0 = " #LD_OP "(%2)\n\t" \ + "}:mem_noshuf\n" \ + : "=r"(ret) \ + : "r"(p), "r"(q), "r"(x) \ + : "memory"); \ + return ret; \ +} + +/* Store byte combinations */ +MEM_NOSHUF32(mem_noshuf_sb_lb, signed char, signed char, memb, memb) +MEM_NOSHUF32(mem_noshuf_sb_lub, signed char, unsigned char, memb, memub) +MEM_NOSHUF32(mem_noshuf_sb_lh, signed char, signed short, memb, memh) +MEM_NOSHUF32(mem_noshuf_sb_luh, signed char, unsigned short, memb, memuh) +MEM_NOSHUF32(mem_noshuf_sb_lw, signed char, signed int, memb, memw) +MEM_NOSHUF64(mem_noshuf_sb_ld, signed char, signed long long, memb, memd) + +/* Store half combinations */ +MEM_NOSHUF32(mem_noshuf_sh_lb, signed short, signed char, memh, memb) +MEM_NOSHUF32(mem_noshuf_sh_lub, signed short, unsigned char, memh, memub) +MEM_NOSHUF32(mem_noshuf_sh_lh, signed short, signed short, memh, memh) +MEM_NOSHUF32(mem_noshuf_sh_luh, signed short, unsigned short, memh, memuh) +MEM_NOSHUF32(mem_noshuf_sh_lw, signed short, signed int, memh, memw) +MEM_NOSHUF64(mem_noshuf_sh_ld, signed short, signed long long, memh, memd) + +/* Store word combinations */ +MEM_NOSHUF32(mem_noshuf_sw_lb, signed int, signed char, memw, memb) +MEM_NOSHUF32(mem_noshuf_sw_lub, signed int, unsigned char, memw, memub) +MEM_NOSHUF32(mem_noshuf_sw_lh, signed int, signed short, memw, memh) +MEM_NOSHUF32(mem_noshuf_sw_luh, signed int, unsigned short, memw, memuh) +MEM_NOSHUF32(mem_noshuf_sw_lw, signed int, signed int, memw, memw) +MEM_NOSHUF64(mem_noshuf_sw_ld, signed int, signed long long, memw, memd) + +/* Store double combinations */ +MEM_NOSHUF32(mem_noshuf_sd_lb, long long, signed char, memd, memb) +MEM_NOSHUF32(mem_noshuf_sd_lub, long long, unsigned char, memd, memub) +MEM_NOSHUF32(mem_noshuf_sd_lh, long long, signed short, memd, memh) +MEM_NOSHUF32(mem_noshuf_sd_luh, long long, unsigned short, memd, memuh) +MEM_NOSHUF32(mem_noshuf_sd_lw, long long, signed int, memd, memw) +MEM_NOSHUF64(mem_noshuf_sd_ld, long long, signed long long, memd, memd) + +static inline unsigned int cancel_sw_lb(int pred, int *p, signed char *q, int x) +{ + unsigned int ret; + asm volatile("p0 = cmp.eq(%4, #0)\n\t" + "{\n\t" + " if (!p0) memw(%1) = %3\n\t" + " %0 = memb(%2)\n\t" + "}:mem_noshuf\n" + : "=r"(ret) + : "r"(p), "r"(q), "r"(x), "r"(pred) + : "p0", "memory"); + return ret; +} + +static inline +unsigned long long cancel_sw_ld(int pred, int *p, long long *q, int x) +{ + long long ret; + asm volatile("p0 = cmp.eq(%4, #0)\n\t" + "{\n\t" + " if (!p0) memw(%1) = %3\n\t" + " %0 = memd(%2)\n\t" + "}:mem_noshuf\n" + : "=r"(ret) + : "r"(p), "r"(q), "r"(x), "r"(pred) + : "p0", "memory"); + return ret; +} + +typedef union { + signed long long d; + unsigned long long ud; + signed int w[2]; + unsigned int uw[2]; + signed short h[4]; + unsigned short uh[4]; + signed char b[8]; + unsigned char ub[8]; +} Memory; + +int err; + +static void check32(int n, int expect) +{ + if (n != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", n, expect); + err++; + } +} + +static void check64(long long n, long long expect) +{ + if (n != expect) { + printf("ERROR: 0x%08llx != 0x%08llx\n", n, expect); + err++; + } +} + +int main() +{ + Memory n; + unsigned int res32; + unsigned long long res64; + + /* + * Store byte combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sb_lb(&n.b[0], &n.b[0], 0x87); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lub(&n.b[0], &n.ub[0], 0x87); + check32(res32, 0x00000087); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lh(&n.b[0], &n.h[0], 0x87); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_luh(&n.b[0], &n.uh[0], 0x87); + check32(res32, 0x0000ff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lw(&n.b[0], &n.w[0], 0x87); + check32(res32, 0xffffff87); + + n.d = ~0; + res64 = mem_noshuf_sb_ld(&n.b[0], &n.d, 0x87); + check64(res64, 0xffffffffffffff87); + + /* + * Store half combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sh_lb(&n.h[0], &n.b[0], 0x8787); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lub(&n.h[0], &n.ub[1], 0x8f87); + check32(res32, 0x0000008f); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lh(&n.h[0], &n.h[0], 0x8a87); + check32(res32, 0xffff8a87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_luh(&n.h[0], &n.uh[0], 0x8a87); + check32(res32, 0x8a87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lw(&n.h[1], &n.w[0], 0x8a87); + check32(res32, 0x8a87ffff); + + n.w[0] = ~0; + res64 = mem_noshuf_sh_ld(&n.h[1], &n.d, 0x8a87); + check64(res64, 0xffffffff8a87ffff); + + /* + * Store word combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sw_lb(&n.w[0], &n.b[0], 0x12345687); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lub(&n.w[0], &n.ub[0], 0x12345687); + check32(res32, 0x00000087); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lh(&n.w[0], &n.h[0], 0x1234f678); + check32(res32, 0xfffff678); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_luh(&n.w[0], &n.uh[0], 0x12345678); + check32(res32, 0x00005678); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lw(&n.w[0], &n.w[0], 0x12345678); + check32(res32, 0x12345678); + + n.d = ~0; + res64 = mem_noshuf_sw_ld(&n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffff12345678); + + /* + * Store double combinations + */ + n.d = ~0; + res32 = mem_noshuf_sd_lb(&n.d, &n.b[1], 0x123456789abcdef0); + check32(res32, 0xffffffde); + + n.d = ~0; + res32 = mem_noshuf_sd_lub(&n.d, &n.ub[1], 0x123456789abcdef0); + check32(res32, 0x000000de); + + n.d = ~0; + res32 = mem_noshuf_sd_lh(&n.d, &n.h[1], 0x123456789abcdef0); + check32(res32, 0xffff9abc); + + n.d = ~0; + res32 = mem_noshuf_sd_luh(&n.d, &n.uh[1], 0x123456789abcdef0); + check32(res32, 0x00009abc); + + n.d = ~0; + res32 = mem_noshuf_sd_lw(&n.d, &n.w[1], 0x123456789abcdef0); + check32(res32, 0x12345678); + + n.d = ~0; + res64 = mem_noshuf_sd_ld(&n.d, &n.d, 0x123456789abcdef0); + check64(res64, 0x123456789abcdef0); + + /* + * Predicated word stores + */ + n.w[0] = ~0; + res32 = cancel_sw_lb(0, &n.w[0], &n.b[0], 0x12345678); + check32(res32, 0xffffffff); + + n.w[0] = ~0; + res32 = cancel_sw_lb(1, &n.w[0], &n.b[0], 0x12345687); + check32(res32, 0xffffff87); + + /* + * Predicated double stores + */ + n.d = ~0; + res64 = cancel_sw_ld(0, &n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffffffffffff); + + n.d = ~0; + res64 = cancel_sw_ld(1, &n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffff12345678); + + n.d = ~0; + res64 = cancel_sw_ld(0, &n.w[1], &n.d, 0x12345678); + check64(res64, 0xffffffffffffffff); + + n.d = ~0; + res64 = cancel_sw_ld(1, &n.w[1], &n.d, 0x12345678); + check64(res64, 0x12345678ffffffff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c new file mode 100644 index 0000000..796ac74 --- /dev/null +++ b/tests/tcg/hexagon/misc.c @@ -0,0 +1,293 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + + +static inline void S4_storerhnew_rr(void *p, int index, uint16_t v) +{ + asm volatile("{\n\t" + " r0 = %0\n\n" + " memh(%1+%2<<#2) = r0.new\n\t" + "}\n" + :: "r"(v), "r"(p), "r"(index) + : "r0", "memory"); +} + +static uint32_t data; +static inline void *S4_storerbnew_ap(uint8_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memb(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void *S4_storerhnew_ap(uint16_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memh(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void *S4_storerinew_ap(uint32_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memw(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void S4_storeirbt_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memb(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbf_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memb(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbtnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memb(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbfnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memb(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirht_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memh(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhf_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memh(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhtnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memh(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhfnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memh(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirit_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memw(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirif_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memw(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeiritnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memw(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirifnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memw(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%04x != 0x%04x\n", val, expect); + err++; + } +} + +uint32_t init[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; +uint32_t array[10]; + +int main() +{ + + memcpy(array, init, sizeof(array)); + S4_storerhnew_rr(array, 4, 0xffff); + check(array[4], 0xffff); + + data = ~0; + check((uint32_t)S4_storerbnew_ap(0x12), (uint32_t)&data); + check(data, 0xffffff12); + + data = ~0; + check((uint32_t)S4_storerhnew_ap(0x1234), (uint32_t)&data); + check(data, 0xffff1234); + + data = ~0; + check((uint32_t)S4_storerinew_ap(0x12345678), (uint32_t)&data); + check(data, 0x12345678); + + /* Byte */ + memcpy(array, init, sizeof(array)); + S4_storeirbt_io(&array[1], 1); + check(array[2], 27); + S4_storeirbt_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirbf_io(&array[3], 0); + check(array[4], 27); + S4_storeirbf_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeirbtnew_io(&array[5], 1); + check(array[6], 27); + S4_storeirbtnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirbfnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirbfnew_io(&array[8], 1); + check(array[9], 9); + + /* Half word */ + memcpy(array, init, sizeof(array)); + S4_storeirht_io(&array[1], 1); + check(array[2], 27); + S4_storeirht_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirhf_io(&array[3], 0); + check(array[4], 27); + S4_storeirhf_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeirhtnew_io(&array[5], 1); + check(array[6], 27); + S4_storeirhtnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirhfnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirhfnew_io(&array[8], 1); + check(array[9], 9); + + /* Word */ + memcpy(array, init, sizeof(array)); + S4_storeirit_io(&array[1], 1); + check(array[2], 27); + S4_storeirit_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirif_io(&array[3], 0); + check(array[4], 27); + S4_storeirif_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeiritnew_io(&array[5], 1); + check(array[6], 27); + S4_storeiritnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirifnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirifnew_io(&array[8], 1); + check(array[9], 9); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/preg_alias.c b/tests/tcg/hexagon/preg_alias.c new file mode 100644 index 0000000..4d51674 --- /dev/null +++ b/tests/tcg/hexagon/preg_alias.c @@ -0,0 +1,106 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +static inline int preg_alias(int v0, int v1, int v2, int v3) +{ + int ret; + asm volatile("p0 = %1\n\t" + "p1 = %2\n\t" + "p2 = %3\n\t" + "p3 = %4\n\t" + "%0 = C4\n" + : "=r"(ret) + : "r"(v0), "r"(v1), "r"(v2), "r"(v3) + : "p0", "p1", "p2", "p3"); + return ret; +} + +typedef union { + int creg; + struct { + unsigned char p0; + unsigned char p1; + unsigned char p2; + unsigned char p3; + } pregs; +} PRegs; + +static inline void creg_alias(int cval, PRegs *pregs) +{ + unsigned char val; + asm volatile("c4 = %0" : : "r"(cval)); + + asm volatile("%0 = p0" : "=r"(val)); + pregs->pregs.p0 = val; + asm volatile("%0 = p1" : "=r"(val)); + pregs->pregs.p1 = val; + asm volatile("%0 = p2" : "=r"(val)); + pregs->pregs.p2 = val; + asm volatile("%0 = p3" : "=r"(val)); + pregs->pregs.p3 = val; +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", val, expect); + err++; + } +} + +int main() +{ + int c4; + PRegs pregs; + + c4 = preg_alias(0xff, 0x00, 0xff, 0x00); + check(c4, 0x00ff00ff); + c4 = preg_alias(0xff, 0x00, 0x00, 0x00); + check(c4, 0x000000ff); + c4 = preg_alias(0x00, 0xff, 0x00, 0x00); + check(c4, 0x0000ff00); + c4 = preg_alias(0x00, 0x00, 0xff, 0x00); + check(c4, 0x00ff0000); + c4 = preg_alias(0x00, 0x00, 0x00, 0xff); + check(c4, 0xff000000); + c4 = preg_alias(0xff, 0xff, 0xff, 0xff); + check(c4, 0xffffffff); + + creg_alias(0x00ff00ff, &pregs); + check(pregs.creg, 0x00ff00ff); + creg_alias(0x00ffff00, &pregs); + check(pregs.creg, 0x00ffff00); + creg_alias(0x00000000, &pregs); + check(pregs.creg, 0x00000000); + creg_alias(0xff000000, &pregs); + check(pregs.creg, 0xff000000); + creg_alias(0x00ff0000, &pregs); + check(pregs.creg, 0x00ff0000); + creg_alias(0x0000ff00, &pregs); + check(pregs.creg, 0x0000ff00); + creg_alias(0x000000ff, &pregs); + check(pregs.creg, 0x000000ff); + creg_alias(0xffffffff, &pregs); + check(pregs.creg, 0xffffffff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/pthread_cancel.c b/tests/tcg/hexagon/pthread_cancel.c new file mode 100644 index 0000000..db30cbc --- /dev/null +++ b/tests/tcg/hexagon/pthread_cancel.c @@ -0,0 +1,43 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include + +static void *func(void *arg) +{ + sleep(3); + return 0; +} + +int main() +{ + int err = 0; + pthread_t thread; + void *res; + + pthread_create(&thread, 0, func, NULL); + pthread_cancel(thread); + pthread_join(thread, &res); + if (res != PTHREAD_CANCELED) { + err++; + } + + puts(err == 0 ? "PASS" : "FAIL"); + return err == 0 ? 0 : -1; +} diff --git a/tests/tcg/hexagon/sfminmax.c b/tests/tcg/hexagon/sfminmax.c new file mode 100644 index 0000000..cfe443f --- /dev/null +++ b/tests/tcg/hexagon/sfminmax.c @@ -0,0 +1,62 @@ +/* + * Copyright(c) 2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * This test checks that the FP invalid bit in USR is not set + * when one of the operands is NaN. + */ +const int FPINVF_BIT = 1; + +int err; + +int main() +{ + int usr; + + asm volatile("r2 = usr\n\t" + "r2 = clrbit(r2, #%1)\n\t" + "usr = r2\n\t" + "r2 = ##0x7fc00000\n\t" /* NaN */ + "r3 = ##0x7f7fffff\n\t" + "r2 = sfmin(r2, r3)\n\t" + "%0 = usr\n\t" + : "=r"(usr) : "i"(FPINVF_BIT) : "r2", "r3", "usr"); + + if (usr & (1 << FPINVF_BIT)) { + puts("sfmin test failed"); + err++; + } + + asm volatile("r2 = usr\n\t" + "r2 = clrbit(r2, #%1)\n\t" + "usr = r2\n\t" + "r2 = ##0x7fc00000\n\t" /* NaN */ + "r3 = ##0x7f7fffff\n\t" + "r2 = sfmax(r2, r3)\n\t" + "%0 = usr\n\t" + : "=r"(usr) : "i"(FPINVF_BIT) : "r2", "r3", "usr"); + + if (usr & (1 << FPINVF_BIT)) { + puts("sfmax test failed"); + err++; + } + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 102578c..43a940d 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -69,6 +69,8 @@ fi : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"} : ${cross_cc_x86_64="x86_64-pc-linux-gnu-gcc"} : ${cross_cc_cflags_x86_64="-m64"} +: ${cross_cc_hexagon="hexagon-linux-clang"} +: ${cross_cc_cflags_hexagon="-mv67 -O2 -Wno-incompatible-pointer-types"} for target in $target_list; do arch=${target%%-*} @@ -94,7 +96,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64|hexagon) arches=$target ;; *) diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target new file mode 100644 index 0000000..f696c78 --- /dev/null +++ b/tests/tcg/hexagon/Makefile.target @@ -0,0 +1,49 @@ +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +# Hexagon doesn't support gdb, so skip the EXTRA_RUNS +EXTRA_RUNS = + +# Hexagon has 64K pages, so increase the timeout to keep +# test-mmap from timing out +ifeq ($(CONFIG_DEBUG_TCG),y) +TIMEOUT=90 +else +TIMEOUT=40 +endif + + +CFLAGS = -mv67 -O2 + +HEX_SRC=$(SRC_PATH)/tests/tcg/hexagon +VPATH += $(HEX_SRC) + +first: $(HEX_SRC)/first.S + $(CC) -static -mv67 -nostdlib $^ -o $@ + +HEX_TESTS = first +HEX_TESTS += exec_counters +HEX_TESTS += misc +HEX_TESTS += preg_alias +HEX_TESTS += dual_stores +HEX_TESTS += clrtnew +HEX_TESTS += mem_noshuf +HEX_TESTS += pthread_cancel +HEX_TESTS += atomics +HEX_TESTS += sfminmax + +TESTS += $(HEX_TESTS) diff --git a/tests/tcg/hexagon/first.S b/tests/tcg/hexagon/first.S new file mode 100644 index 0000000..841c0bb --- /dev/null +++ b/tests/tcg/hexagon/first.S @@ -0,0 +1,57 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define SYS_write 64 +#define SYS_exit_group 94 +#define SYS_exit 93 + +#define FD_STDOUT 1 + + .type str,@object + .section .rodata +str: + .string "Hello!\n" + .size str, 8 + +.text +.global _start +_start: + r6 = #SYS_write + r0 = #FD_STDOUT + r1 = ##str + r2 = #7 + trap0(#1) + + r0 = #0 + r6 = #SYS_exit_group + trap0(#1) + +.section ".note.ABI-tag", "a" +.align 4 +.long 1f - 0f /* name length */ +.long 3f - 2f /* data length */ +.long 1 /* note type */ + +/* + * vendor name seems like this should be MUSL but lldb doesn't agree. + */ +0: .asciz "GNU" +1: .align 4 +2: .long 0 /* linux */ + .long 3,0,0 +3: .align 4 + diff --git a/tests/tcg/hexagon/float_convs.ref b/tests/tcg/hexagon/float_convs.ref new file mode 100644 index 0000000..9ec9ffc --- /dev/null +++ b/tests/tcg/hexagon/float_convs.ref @@ -0,0 +1,748 @@ +### Rounding to nearest +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding upwards +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding downwards +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding to zero +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) diff --git a/tests/tcg/hexagon/float_madds.ref b/tests/tcg/hexagon/float_madds.ref new file mode 100644 index 0000000..ceed3bb --- /dev/null +++ b/tests/tcg/hexagon/float_madds.ref @@ -0,0 +1,768 @@ +### Rounding to nearest +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27fa00000000000000p+60:0x5d8613fd) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46200000000000000p+34:0x50936231) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f94000000000000000p-106:0x0ac8fca0) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f75000000000000000p-40:0xab98fba8) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040200000000000000p+0:0x3f800201) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804200000000000000p+3:0x41094021) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3c00000000000000p+17:0x4848f69e) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edf000000000000000p+18:0x488476f8) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7a00000000000000p+18:0x4884773d) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840800000000000000p+31:0x4f7fc204) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+31:0x4f7fc104) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860800000000000000p+31:0x4f7fc304) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+32:0x4fffc104) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830800000000000000p+32:0x4fffc184) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840800000000000000p+32:0x4fffc204) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820800000000000000p+33:0x507fc104) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810800000000000000p+33:0x507fc084) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0838000000000000000p+116:0x79e041c0) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) +### Rounding upwards +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b000000000000000p+103:0xf30c3a58) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27fa00000000000000p+60:0x5d8613fd) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46200000000000000p+34:0x50936231) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f94000000000000000p-106:0x0ac8fca0) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f74e00000000000000p-40:0xab98fba7) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544200000000000000p-66:0x9ea82a21) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe800000000000000p-25:0x337ffff4) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe800000000000000p-50:0x26fffff4) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000200000000000000p-25:0x33000001) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00080000000000000000p-25:0x33000400) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f400000000000000p-24:0x338000fa) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000e00000000000000p-14:0x38800007) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf600000000000000p-24:0x3387fdfb) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000200000000000000p+0:0x3f800001) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01a00000000000000p-14:0x38ffe00d) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01a00000000000000p-14:0x38ffe00d) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440200000000000000p+0:0x3f802201) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440200000000000000p+0:0x3f802201) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040200000000000000p+0:0x3f800201) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d400000000000000p+2:0x409711ea) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804200000000000000p+3:0x41094021) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458200000000000000p+3:0x4128a2c1) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0600000000000000p+3:0x41100603) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1600000000000000p+15:0x477fe78b) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3c00000000000000p+17:0x4848f69e) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56200000000000000p+17:0x482de2b1) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edf000000000000000p+18:0x488476f8) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0a00000000000000p+31:0x4f7fbf05) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7a00000000000000p+18:0x4884773d) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800a00000000000000p+31:0x4f7fc005) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840800000000000000p+31:0x4f7fc204) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+31:0x4f7fc104) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860800000000000000p+31:0x4f7fc304) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+32:0x4fffc104) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800a00000000000000p+32:0x4fffc005) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830800000000000000p+32:0x4fffc184) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8a00000000000000p+33:0x507fbfc5) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840800000000000000p+32:0x4fffc204) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800a00000000000000p+33:0x507fc005) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820800000000000000p+33:0x507fc104) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810800000000000000p+33:0x507fc084) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab800000000000000p+99:0x71605d5c) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0838000000000000000p+116:0x79e041c0) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c082a000000000000000p+116:0x79e04150) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-148:0x00000002) flags=UNDERFLOW INEXACT (32/0) +### Rounding downwards +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27f800000000000000p+60:0x5d8613fc) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46000000000000000p+34:0x50936230) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f93e00000000000000p-106:0x0ac8fc9f) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f75000000000000000p-40:0xab98fba8) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x1.00000000000000000000p-149:0x80000001) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040000000000000000p+0:0x3f800200) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804000000000000000p+3:0x41094020) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3a00000000000000p+17:0x4848f69d) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edee00000000000000p+18:0x488476f7) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7800000000000000p+18:0x4884773c) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840600000000000000p+31:0x4f7fc203) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+31:0x4f7fc103) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860600000000000000p+31:0x4f7fc303) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+32:0x4fffc103) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830600000000000000p+32:0x4fffc183) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840600000000000000p+32:0x4fffc203) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820600000000000000p+33:0x507fc103) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810600000000000000p+33:0x507fc083) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0837e00000000000000p+116:0x79e041bf) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) +### Rounding to zero +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b000000000000000p+103:0xf30c3a58) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27f800000000000000p+60:0x5d8613fc) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46000000000000000p+34:0x50936230) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f93e00000000000000p-106:0x0ac8fc9f) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f74e00000000000000p-40:0xab98fba7) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544200000000000000p-66:0x9ea82a21) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040000000000000000p+0:0x3f800200) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804000000000000000p+3:0x41094020) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3a00000000000000p+17:0x4848f69d) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edee00000000000000p+18:0x488476f7) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7800000000000000p+18:0x4884773c) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840600000000000000p+31:0x4f7fc203) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+31:0x4f7fc103) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860600000000000000p+31:0x4f7fc303) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+32:0x4fffc103) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830600000000000000p+32:0x4fffc183) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840600000000000000p+32:0x4fffc203) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820600000000000000p+33:0x507fc103) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810600000000000000p+33:0x507fc083) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0837e00000000000000p+116:0x79e041bf) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) From patchwork Tue Aug 18 15:50:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 276117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, 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b=r+jBqT6d2Grxv+NEzuDW5ldwf4jOSd7efNJbB+I5ACrsa3ORcxyCS+H8 39oIQHwGWfkMo5apSDdz1o2svQQSYb5xgvQZCvj8WaI4Uh+DlDIitjF4o B7zdFNEd3wbD8TrPtFD7ee3GHIwVgYQQIBadmQ7UB1ifCBLge9hfbzCQ0 0=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 Aug 2020 08:51:00 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:59 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id B1001848; Tue, 18 Aug 2020 10:50:59 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 34/34] Hexagon build infrastructure Date: Tue, 18 Aug 2020 10:50:47 -0500 Message-Id: <1597765847-16637-35-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add file to default-configs Change configure Add target/hexagon/Makefile.objs Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" will pass. Signed-off-by: Taylor Simpson --- configure | 9 ++ default-configs/hexagon-linux-user.mak | 1 + scripts/qemu-binfmt-conf.sh | 6 +- target/hexagon/Makefile.objs | 203 +++++++++++++++++++++++++++++++++ 4 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 default-configs/hexagon-linux-user.mak create mode 100644 target/hexagon/Makefile.objs diff --git a/configure b/configure index 2acc4d1..1f5c5a0 100755 --- a/configure +++ b/configure @@ -8275,6 +8275,12 @@ case "$target_name" in bflt="yes" mttcg="yes" ;; + hexagon) + TARGET_BASE_ARCH=hexagon + TARGET_ABI_DIR=hexagon + mttcg=yes + target_compiler=$cross_cc_hexagon + ;; *) error_exit "Unsupported target CPU" ;; @@ -8447,6 +8453,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do xtensa*) disas_config "XTENSA" ;; + hexagon) + disas_config "HEXAGON" + ;; esac done if test "$tcg_interpreter" = "yes" ; then diff --git a/default-configs/hexagon-linux-user.mak b/default-configs/hexagon-linux-user.mak new file mode 100644 index 0000000..ad55af0 --- /dev/null +++ b/default-configs/hexagon-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for hexagon-linux-user diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 9f1580a..7b5d54b 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -4,7 +4,7 @@ qemu_target_list="i386 i486 alpha arm armeb sparc sparc32plus sparc64 \ ppc ppc64 ppc64le m68k mips mipsel mipsn32 mipsn32el mips64 mips64el \ sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ -microblaze microblazeel or1k x86_64" +microblaze microblazeel or1k x86_64 hexagon" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -136,6 +136,10 @@ or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\ or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' or1k_family=or1k +hexagon_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xa4\x00' +hexagon_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' +hexagon_family=hexagon + qemu_get_family() { cpu=${HOST_ARCH:-$(uname -m)} case "$cpu" in diff --git a/target/hexagon/Makefile.objs b/target/hexagon/Makefile.objs new file mode 100644 index 0000000..f9321c8 --- /dev/null +++ b/target/hexagon/Makefile.objs @@ -0,0 +1,203 @@ +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +obj-y += \ + cpu.o \ + translate.o \ + op_helper.o \ + gdbstub.o \ + genptr.o \ + reg_fields.o \ + decode.o \ + iclass.o \ + opcodes.o \ + printinsn.o \ + arch.o \ + fma_emu.o \ + conv_emu.o + +# +# Step 1 +# We use a C program to create semantics_generated.pyinc +# +BUILD_USER_DIR = $(BUILD_DIR)/hexagon-linux-user +GEN_SEMANTICS = gen_semantics +GEN_SEMANTICS_SRC = $(SRC_PATH)/target/hexagon/gen_semantics.c + +IDEF_FILES = \ + $(SRC_PATH)/target/hexagon/imported/alu.idef \ + $(SRC_PATH)/target/hexagon/imported/branch.idef \ + $(SRC_PATH)/target/hexagon/imported/compare.idef \ + $(SRC_PATH)/target/hexagon/imported/float.idef \ + $(SRC_PATH)/target/hexagon/imported/ldst.idef \ + $(SRC_PATH)/target/hexagon/imported/mpy.idef \ + $(SRC_PATH)/target/hexagon/imported/shift.idef \ + $(SRC_PATH)/target/hexagon/imported/subinsns.idef \ + $(SRC_PATH)/target/hexagon/imported/system.idef +DEF_FILES = \ + $(SRC_PATH)/target/hexagon/imported/allidefs.def \ + $(SRC_PATH)/target/hexagon/imported/macros.def + +$(GEN_SEMANTICS): $(GEN_SEMANTICS_SRC) $(IDEF_FILES) $(DEF_FILES) + $(CC) $(CFLAGS) $(GEN_SEMANTICS_SRC) -o $(GEN_SEMANTICS) + +SEMANTICS=semantics_generated.pyinc +$(SEMANTICS): $(GEN_SEMANTICS) + $(call quiet-command, \ + $(BUILD_USER_DIR)/$(GEN_SEMANTICS) $(SEMANTICS), \ + "GEN", $(SEMANTICS)) + +# +# Step 2 +# We use Python scripts to generate the following files +# +SHORTCODE_H = $(BUILD_USER_DIR)/shortcode_generated.h +HELPER_PROTOS_H = $(BUILD_USER_DIR)/helper_protos_generated.h +TCG_FUNCS_H = $(BUILD_USER_DIR)/tcg_funcs_generated.h +HELPER_FUNCS_H = $(BUILD_USER_DIR)/helper_funcs_generated.h +OPCODES_DEF_H = $(BUILD_USER_DIR)/opcodes_def_generated.h +OP_ATTRIBS_H = $(BUILD_USER_DIR)/op_attribs_generated.h +OP_REGS_H = $(BUILD_USER_DIR)/op_regs_generated.h +PRINTINSN_H = $(BUILD_USER_DIR)/printinsn_generated.h + +GENERATED_HEXAGON_FILES = \ + $(SHORTCODE_H) \ + $(HELPER_PROTOS_H) \ + $(TCG_FUNCS_H) \ + $(HELPER_FUNCS_H) \ + $(OPCODES_DEF_H) \ + $(OP_ATTRIBS_H) \ + $(OP_REGS_H) \ + $(PRINTINSN_H) + +$(SHORTCODE_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_shortcode.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_shortcode.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon shortcode_generated.h") + +$(HELPER_PROTOS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_helper_protos.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_helper_protos.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon helper_protos_generated.h") + +$(TCG_FUNCS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_tcg_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_tcg_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon tcg_funcs_generated.h") + +$(HELPER_FUNCS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_helper_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_helper_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon helper_funcs_generated.h") + +$(PRINTINSN_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_printinsn.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_printinsn.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon printinsn_generated.h") + +$(OP_REGS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_op_regs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_op_regs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon op_regs_generated.h") + +$(OP_ATTRIBS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_op_attribs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_op_attribs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon op_attribs_generated.h") + +$(OPCODES_DEF_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_opcodes_def.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_opcodes_def.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon opcodes_def_generated.h") + +# +# Step 3 +# We use a C program to create iset.py which is imported into dectree.py +# to create the decode tree +# +GEN_DECTREE_IMPORT=gen_dectree_import +GEN_DECTREE_IMPORT_SRC = $(SRC_PATH)/target/hexagon/gen_dectree_import.c + +$(GEN_DECTREE_IMPORT): $(GEN_DECTREE_IMPORT_SRC) $(OPCODES_DEF_H) config-target.h + $(CC) $(QEMU_CFLAGS) $(QEMU_INCLUDES) -I$(BUILD_DIR) $(GEN_DECTREE_IMPORT_SRC) -o $(GEN_DECTREE_IMPORT) + +DECTREE_IMPORT=iset.py +$(DECTREE_IMPORT): $(GEN_DECTREE_IMPORT) + $(call quiet-command, \ + $(BUILD_USER_DIR)/$(GEN_DECTREE_IMPORT) $(DECTREE_IMPORT), \ + "GEN", $(DECTREE_IMPORT)) + +# +# Step 4 +# We use the dectree.py script to generate the decode tree header file +# +DECTREE_HEADER=dectree_generated.h +$(DECTREE_HEADER): $(SRC_PATH)/target/hexagon/dectree.py $(DECTREE_IMPORT) + $(call quiet-command, \ + PYTHONPATH=$(BUILD_USER_DIR) \ + $(PYTHON) $(SRC_PATH)/target/hexagon/dectree.py, \ + "GEN", "Hexagon decode tree") + +generated-files-y += $(GENERATED_HEXAGON_FILES) $(DECTREE_HEADER)