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[209.132.180.67]) by mx.google.com with ESMTP id z88si12912405pff.304.2017.11.06.11.47.15; Mon, 06 Nov 2017 11:47:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Z4vlp3Iq; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932811AbdKFTrN (ORCPT + 6 others); Mon, 6 Nov 2017 14:47:13 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:44004 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932808AbdKFTrM (ORCPT ); Mon, 6 Nov 2017 14:47:12 -0500 Received: by mail-pg0-f65.google.com with SMTP id s75so9060061pgs.0 for ; Mon, 06 Nov 2017 11:47:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=StiEn5Ga03p19IerdWqiZoZrlSEelJUY11hdc8pXUz8=; b=Z4vlp3IqQ0bkbGSFOavFIrfeJSxiaZCLjM90XNrs8ntbqofWpts+uTriY4BideJIJV BP9TWfTXEwG8yMSGcbaDFUq8j41XlmdOCl97BFqNZHdnBeoCgCqgpeyp7gsC0zqtBxVq cuO6UOSDUffc0TAePj4Unl5iBtaKq6t50bVd0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=StiEn5Ga03p19IerdWqiZoZrlSEelJUY11hdc8pXUz8=; b=KzRIMD/hd6np6ChIGuuPEutw585PqRJdxCj06A0UrtmDuN+3ZlA+OZgZHYs7FMwidR qwkdHrO2Nr7mTM3lx3xQY01JO/R+hy4UC7/Ay4IlO8hwSPLGWK0QEEZnZ0fNo/eYu8/5 lVbedpR8TihfWFEAB+WA/BaLZBMVAAJCKkm1xXlyuBDpqHhoaR9TNKsAwyULx4m6EoZT 0SIOTrGS58ybfxgUgy1TpLAYVeBZec1z1WdQJXx+UzbC0NzhU6EjLDMtM2oGyTxIOYAh rXSDuB4TIPSBm1akRNevob8a3e2d4HPfhABQLm1w69os8zh/LA+m2byIdb1+tZYBLkCc ZeLQ== X-Gm-Message-State: AMCzsaWhvqXQIU3cZOwmyuIfc2HcXkB7CqVxW9yCYIQzkJA7ZWqY3Sc/ r6zdtxN85VWE34GNicrC5+0wwMvgnU2e X-Received: by 10.98.234.9 with SMTP id t9mr17856257pfh.92.1509997631441; Mon, 06 Nov 2017 11:47:11 -0800 (PST) Received: from localhost.localdomain ([2405:204:71cc:8264:4544:dc65:374e:dc33]) by smtp.gmail.com with ESMTPSA id t2sm27919118pfk.90.2017.11.06.11.47.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Nov 2017 11:47:10 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@codeaurora.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, arnd@arndb.de, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, viresh.kumar@linaro.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 1/3] dt-bindings: clock: Add Actions S900 clock bindings Date: Tue, 7 Nov 2017 01:15:50 +0530 Message-Id: <1509997552-29718-2-git-send-email-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509997552-29718-1-git-send-email-manivannan.sadhasivam@linaro.org> References: <1509997552-29718-1-git-send-email-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Actions Semi S900 clock bindings. Signed-off-by: Manivannan Sadhasivam --- Changes in v2: 1. Added binding header to this patch 2. Changed clock-controller node name to cmu 3. Added clocks property to cmu node 4. Changed compatible property value to "actions,s900-cmu" 5. Fixed example UART controller node 6. Fixed tab vs space issue .../devicetree/bindings/clock/actions,s900-cmu.txt | 47 +++++++ include/dt-bindings/clock/actions,s900-cmu.h | 139 +++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/actions,s900-cmu.txt create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt new file mode 100644 index 0000000..6e2c038 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt @@ -0,0 +1,47 @@ +* Actions S900 Clock Management Unit (CMU) + +The Actions S900 clock management unit generates and supplies clock to various +controllers within the SoC. The clock binding described here is applicable to +S900 SoC. + +Required Properties: + +- compatible: should be "actions,s900-cmu" +- reg: physical base address of the controller and length of memory mapped + region. +- clocks: Reference to the parent clocks ("hosc", "losc") +- #clock-cells: should be 1. + +Each clock is assigned an identifier, and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/actions,s900-cmu.h header and can be used in device +tree sources. + +External clocks: + +The hosc clock used as input for the plls is generated outside the SoC. It is +expected that it is defined using standard clock bindings as "hosc". + +Actions S900 CMU also requires one more clock: + - "losc" - internal low frequency oscillator + +Example: Clock Management Unit node: + + cmu: clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0 0xe0160000 0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + +Example: UART controller node that consumes clock generated by the clock +management unit: + + uart: serial@e012a000 { + compatible = "actions,s900-uart", "actions,owl-uart"; + reg = <0x0 0xe012a000 0x0 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART5>; + }; diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h new file mode 100644 index 0000000..2155449 --- /dev/null +++ b/include/dt-bindings/clock/actions,s900-cmu.h @@ -0,0 +1,139 @@ +/* + * Device Tree binding constants for Actions S900 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +#define __DT_BINDINGS_CLOCK_S900_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_DSI_PLL 8 +#define CLK_ASSIST_PLL 9 +#define CLK_AUDIO_PLL 10 + +/* system clock */ +#define CLK_CPU 15 +#define CLK_DEV 16 +#define CLK_NOC 17 +#define CLK_NOC_CLK_MUX 18 +#define CLK_NOC_CLK_DIV 19 +#define CLK_AHB 20 +#define CLK_APB 21 +#define CLK_DMAC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 + +#define CLK_BISP 24 +#define CLK_CSI0 25 +#define CLK_CSI1 26 + +#define CLK_DE 27 +#define CLK_DE1 28 +#define CLK_DE2 29 +#define CLK_DE3 30 +#define CLK_DSI 32 + +#define CLK_GPU 33 +#define CLK_GPU_CORE 34 +#define CLK_GPU_MEM 35 +#define CLK_GPU_SYS 36 + +#define CLK_HDE 37 +#define CLK_I2C0 38 +#define CLK_I2C1 39 +#define CLK_I2C2 40 +#define CLK_I2C3 41 +#define CLK_I2C4 42 +#define CLK_I2C5 43 +#define CLK_I2SRX 44 +#define CLK_I2STX 45 +#define CLK_IMX 46 +#define CLK_LCD 47 +#define CLK_NAND0 48 +#define CLK_NAND1 49 +#define CLK_PWM0 50 +#define CLK_PWM1 51 +#define CLK_PWM2 52 +#define CLK_PWM3 53 +#define CLK_PWM4 54 +#define CLK_PWM5 55 +#define CLK_SD0 56 +#define CLK_SD1 57 +#define CLK_SD2 58 +#define CLK_SD3 59 +#define CLK_SENSOR 60 +#define CLK_SPEED_SENSOR 61 +#define CLK_SPI0 62 +#define CLK_SPI1 63 +#define CLK_SPI2 64 +#define CLK_SPI3 65 +#define CLK_THERMAL_SENSOR 66 +#define CLK_UART0 67 +#define CLK_UART1 68 +#define CLK_UART2 69 +#define CLK_UART3 70 +#define CLK_UART4 71 +#define CLK_UART5 72 +#define CLK_UART6 73 +#define CLK_VCE 74 +#define CLK_VDE 75 + +#define CLK_USB3_480MPLL0 76 +#define CLK_USB3_480MPHY0 77 +#define CLK_USB3_5GPHY 78 +#define CLK_USB3_CCE 79 +#define CLK_USB3_MAC 80 + +#define CLK_TIMER 83 + +#define CLK_HDMI_AUDIO 84 + +#define CLK_24M 85 + +#define CLK_EDP 86 + +#define CLK_24M_EDP 87 +#define CLK_EDP_PLL 88 +#define CLK_EDP_LINK 89 + +#define CLK_USB2H0_PLLEN 90 +#define CLK_USB2H0_PHY 91 +#define CLK_USB2H0_CCE 92 +#define CLK_USB2H1_PLLEN 93 +#define CLK_USB2H1_PHY 94 +#define CLK_USB2H1_CCE 95 + +#define CLK_DDR0 96 +#define CLK_DDR1 97 +#define CLK_DMM 98 + +#define CLK_ETH_MAC 99 +#define CLK_RMII_REF 100 + +#define CLK_NR_CLKS 110 + +#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */