From patchwork Mon Nov 6 18:34:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 118085 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3074694qgn; Mon, 6 Nov 2017 10:34:51 -0800 (PST) X-Google-Smtp-Source: ABhQp+Q5l929CjrdEr1RHT3YzB6a9x6K8Yvw0vglAh8D8ACo1IVlljL6R4ELDs5bAWml3ahz+MiF X-Received: by 10.98.10.153 with SMTP id 25mr17681074pfk.60.1509993291483; Mon, 06 Nov 2017 10:34:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1509993291; cv=none; d=google.com; s=arc-20160816; b=Zy5+c+zXBcvikj49ZriLSwSzLQdm3BTzWUhIpPWm8QiM3Nomzi88l/RA/QmaKdHomO brFZvNigEk2VrZpVzDflMYkkDvN1yK7MZZcfI7kSFsYxze1CWyvMSF8Oi4s0Y6Cy+YgR ziI3XKJZ90sAGKVNMAW3vQ2tLFJXGf42XTBHHu0/J3eXWDzwnbL8DP4j36W0L2i59cwz 5koozNTZuD1ZByamKUEKhhF+eYfQp1kJuJEXoTmGToeXdofdTJfgYyqwit5tcgLyf6YM e2YNVVGs+qbQS9uIQ/qER0CtbeahfJ3ik5EUGdUfDNYaHcsJJq/zjJruqj7v9ZJoiYA0 E15g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=zHQ+KUucT0Yw+L7YTjBwvGgN6IXqSGB2nh9k4q0Nl9w=; b=zS9KmsXeeh/DtnyEeJAXTeHFhZV5+CPxqf7Vkh6l/C7dlzV0gk/xqTZF6rrENNWp32 iix2emPWbynHRw/jQKCG0SbJIo3/zPalW5tOoj/Tu2RCeTRoiaOJCpZQCl24M5nkQ3GS ouX/LfovBNZJ7Vl9ciITlPpT4OSWW7Vg1GK38BRtQHg4A1uzyyYuRwHFA79BZW1o5iw2 UoM6Mw0REquCctVz/sNQ1alxB7ZisAKPyKcSmr10Mcxr15YFMI9PhiIwMucDqPLmR1cH g9vl1ecaECSs9ZSStFuMLYQPU94LU+R8GxHS2Yv/SQ9s4OvftZLGn/eY6Rdlvaw/jDgv uaiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q4er+RHY; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y1si12514741pfy.314.2017.11.06.10.34.51; Mon, 06 Nov 2017 10:34:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q4er+RHY; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932327AbdKFSeu (ORCPT + 6 others); Mon, 6 Nov 2017 13:34:50 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:50462 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932241AbdKFSet (ORCPT ); Mon, 6 Nov 2017 13:34:49 -0500 Received: by mail-wr0-f194.google.com with SMTP id p96so9537873wrb.7 for ; Mon, 06 Nov 2017 10:34:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=dxg+dRcw/FfjsWQS13t1RiuLjz1iGQEX1qUH0Ee7hsI=; b=Q4er+RHYT1AvrFtznk54BFg2vGAcxdzmsJP6a+61s8EG1D6Ao8kn/Pn0xMwwrifzIu hVBohFFadEr9+XFvPhDHfZOn0PoAtrHOwKfnp2AJHNxDIk4iWiQzsnrYmTadZBGgBjZ5 qC3Hydii/8SI91CzXtfIqpWCM0CaVmdLcY8VA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=dxg+dRcw/FfjsWQS13t1RiuLjz1iGQEX1qUH0Ee7hsI=; b=j1OcWgN1QMnRICCmKz8TQmUGBIYknuaxBjPhQazCbz4GI4YXIllCm92oCy8Q+VemIe iUJ4cl31p/tIESX9YNpX/EfeQlAAjz/A9M2Dr85005/nY4jFTT70zHSI1/jn0JOiZ0UP XSmN2ohoJRh/z2DFjxw6mCWNlIJRy7egEd5hzApsPyeY5/y1HGbxD4bACjRCZE5Dha98 fhwjvtpWSHXqRqLWYdu+PrOBR0GBDy3TsodOC0gLRBpNBZygxVKAPRpIkIR1yfrZBTGQ awDYGuj/fbwNPXLLD+tb0imyiExWFOwHhHPq3M+Y+/ndUPtgMZ+9us0lMrFUj3o3Vzaq +v4Q== X-Gm-Message-State: AMCzsaXX2eFxxOzJhFXtqruEobXnQABr1n6rWdk08uk4q2XlnnyDJjR/ tj6tg8D/kk63MOvX1R78UXogDO9efnA= X-Received: by 10.223.141.148 with SMTP id o20mr12040385wrb.35.1509993288725; Mon, 06 Nov 2017 10:34:48 -0800 (PST) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id 2sm6872113wrq.83.2017.11.06.10.34.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Nov 2017 10:34:47 -0800 (PST) From: Ard Biesheuvel To: robh+dt@kernel.org, mark.rutland@arm.com, marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de, catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Ard Biesheuvel Subject: [PATCH v2 1/2] dt-bindings: add description of Socionext EXIU interrupt controller Date: Mon, 6 Nov 2017 18:34:36 +0000 Message-Id: <20171106183437.18214-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a description of the External Interrupt Unit (EXIU) interrupt controller as found on the Socionext SynQuacer SoC. Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt new file mode 100644 index 000000000000..dc3778b6fbee --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt @@ -0,0 +1,32 @@ +Socionext SynQuacer External Interrupt Unit (EXIU) + +The Socionext Synquacer SoC has an external interrupt unit (EXIU) +that forwards a block of 32 configurable input lines to 32 adjacent +level-high type GICv3 SPIs. + +Required properties: + +- compatible : Should be "socionext,synquacer-exiu". +- reg : Specifies base physical address and size of the + control registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : phandle of the GIC these interrupts are routed to. +- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent + ones the EXIU forwards its interrups to. + +Notes: + +- Only SPIs can use the EXIU as an interrupt parent. + +Example: + + exiu: exiu@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x0 0x510c0000 0x0 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; From patchwork Mon Nov 6 18:34:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 118086 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3074732qgn; Mon, 6 Nov 2017 10:34:54 -0800 (PST) X-Google-Smtp-Source: ABhQp+TC/AsSOzBpeyr1Ke29bx25qFWj68yMoZg6liqSC3HhyRyaRjGwtuHVf2jeDJJ5EMF2o4jl X-Received: by 10.99.96.15 with SMTP id u15mr16399986pgb.424.1509993294342; Mon, 06 Nov 2017 10:34:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1509993294; cv=none; d=google.com; s=arc-20160816; b=j4+Ixiqbpw1X3T6PxwwyRi+f7H0Ni7miIP8lU0Dnj2+AhPGQY1wJj0yFPGgmm2ovt/ Xq1yiQmS3l3BZKOhAUSXSk2JpIQY4Cams21FAMTQuRJHam4pjuRqSR0mJmMMOLnu8wqE 2nRnEl/zehOiA2kogq3m5abevSs4lxgLPA2yeRwiS7WFTsb070JhvA/LzgK6ip1BQHqh /QcBFYFPKGVsQOYxjaXeUHSfPGRXfM6lg+wXiBnDyQzoxZAydWpX44ktnUXl4bQQ+Z7x dDQnOEIXZqINoLZI5u76UUI91AiGCu1Ry18oJ0PWv8rtSSbjICWs4V+0c6A9vnl5mR+R jaXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=o3ieBh+4eZMSmiaFpRhKffBSApq35iSsjsmG3pmzSz0=; b=REqyrFfIVy1Mh2xu+3tF2ca6jk46CHzLxEZLXiX6G7wEscsyL/yovrSLkj5C2QcFCf nwGOyWOEL1gUWBtUHbblMH96IQldYsbPh3K6BxrzkRCBbZQJcBSSm8+FrYiFf2m1T3Wk l2KE3USyA3s6q8rH1kRfTRnbrO38WeVEIQtXOykaWRfdJvFRZepBPddRVse0XSNThwzn x46VJr3k5/a4WY/EZq3HwOoTiWkda+08keUrWqqnu9h/pBcZBbE+7wBXQRkpqUqdYuJZ /y91Vo3xodSmcchnEp4XOOuUlASdutqe+OUrkSfifqBmkF6MgWJOPulx9BSDPmHPvUGN jbVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T+Eq6Qmv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y1si12514741pfy.314.2017.11.06.10.34.54; Mon, 06 Nov 2017 10:34:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T+Eq6Qmv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932241AbdKFSex (ORCPT + 6 others); Mon, 6 Nov 2017 13:34:53 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:44983 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932342AbdKFSew (ORCPT ); Mon, 6 Nov 2017 13:34:52 -0500 Received: by mail-wm0-f67.google.com with SMTP id n74so11673415wmi.1 for ; Mon, 06 Nov 2017 10:34:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EI3v4zbC9eQ2TYvKkbIkfYH5NcDpPcrKnUjpf4qyVqw=; b=T+Eq6QmvQFGXD0i8uj6TyGe7GUKASgMjcWBldQKEKAMZ+wH+vvAxvHEhVh/bMHMDtx CXPdpP519tZvqqPPSpcOUsi0t2j+Db+jkz4pUVUesLwoaXtQzt+UTPF/TGl3fd/iRmLZ mfz9irlorkPyLKU0uxGEijBwJSXIxqll8XIO0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EI3v4zbC9eQ2TYvKkbIkfYH5NcDpPcrKnUjpf4qyVqw=; b=K9E1BkXT18wKONHcfdorV04WN1K/VwM/uqqAu/phL9MDkQcZ1Md6t7tQoVI02EFRDJ jwRxKl4AWvSIFyBasXy/kDcf54u3mR2j9g2luZmB35l5U4p/67MZxaESTO4NqIjQ4FDm 3o7DKYyWJ+Noy/NuGepIrUGD1ADOyA7dfe78j+wdhArER7jxHN0uvAoIrDr3P1Rk0w5n iRtjgIEzGDGX7AoiPwIAcyDk7RQ5bVd24EM4WPCHVUS82CwkOop6lCn4TMEaiyp8X9pU cYMv9FwGttP5lIrX3JRNQDmrvcWHb8JI8M109SBzu7TnhODTZBUyiFK/v73xahBZYur6 Sm6Q== X-Gm-Message-State: AJaThX6Rkw9DAb7M+9PSpxdQ6az2MQshymSba5tf/Jcybynuf7fOgcFO Wte5hQKtiDV7/ciJcY6oqLk/tA== X-Received: by 10.28.146.20 with SMTP id u20mr6617847wmd.49.1509993291260; Mon, 06 Nov 2017 10:34:51 -0800 (PST) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id 2sm6872113wrq.83.2017.11.06.10.34.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Nov 2017 10:34:50 -0800 (PST) From: Ard Biesheuvel To: robh+dt@kernel.org, mark.rutland@arm.com, marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de, catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Ard Biesheuvel Subject: [PATCH v2 2/2] drivers/irqchip: add support for Socionext Synquacer EXIU controller Date: Mon, 6 Nov 2017 18:34:37 +0000 Message-Id: <20171106183437.18214-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171106183437.18214-1-ard.biesheuvel@linaro.org> References: <20171106183437.18214-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC has an external interrupt unit (EXIU) that forwards a block of 32 configurable input lines to 32 adjacent level-high type GICv3 SPIs. The EXIU has per-interrupt level/edge and polarity controls, and mask bits that keep the outgoing lines de-asserted, even though the controller may still latch interrupt conditions that occur while the line is masked. Signed-off-by: Ard Biesheuvel --- arch/arm64/Kconfig.platforms | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sni-exiu.c | 227 ++++++++++++++++++++ 3 files changed, 231 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6b54ee8c1262..1d03ef54295a 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -161,6 +161,9 @@ config ARCH_SEATTLE config ARCH_SHMOBILE bool +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoC Family" + config ARCH_RENESAS bool "Renesas SoC Platforms" select ARCH_SHMOBILE diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 845abc107ad5..1ebb2e6c67e8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -79,3 +79,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o +obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c new file mode 100644 index 000000000000..1b6e2f7c59af --- /dev/null +++ b/drivers/irqchip/irq-sni-exiu.c @@ -0,0 +1,227 @@ +/* + * Driver for Socionext External Interrupt Unit (EXIU) + * + * Copyright (c) 2017 Linaro, Ltd. + * + * Based on irq-tegra.c: + * Copyright (C) 2011 Google, Inc. + * Copyright (C) 2010,2013, NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define NUM_IRQS 32 + +#define EIMASK 0x00 +#define EISRCSEL 0x04 +#define EIREQSTA 0x08 +#define EIRAWREQSTA 0x0C +#define EIREQCLR 0x10 +#define EILVL 0x14 +#define EIEDG 0x18 +#define EISIR 0x1C + +struct exiu_irq_data { + void __iomem *base; + u32 spi_base; +}; + +static void exiu_irq_eoi(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + + writel(BIT(d->hwirq), data->base + EIREQCLR); + irq_chip_eoi_parent(d); +} + +static void exiu_irq_mask(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 val; + + val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); + writel_relaxed(val, data->base + EIMASK); + irq_chip_mask_parent(d); +} + +static void exiu_irq_unmask(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 val; + + val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); + writel_relaxed(val, data->base + EIMASK); + irq_chip_unmask_parent(d); +} + +static void exiu_irq_enable(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 val; + + /* clear interrupts that were latched while disabled */ + writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); + + val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); + writel_relaxed(val, data->base + EIMASK); + irq_chip_enable_parent(d); +} + +static int exiu_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 val; + + val = readl_relaxed(data->base + EILVL); + if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) + val |= BIT(d->hwirq); + else + val &= ~BIT(d->hwirq); + writel_relaxed(val, data->base + EILVL); + + val = readl_relaxed(data->base + EIEDG); + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) + val &= ~BIT(d->hwirq); + else + val |= BIT(d->hwirq); + writel_relaxed(val, data->base + EIEDG); + + writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static struct irq_chip exiu_irq_chip = { + .name = "EXIU", + .irq_eoi = exiu_irq_eoi, + .irq_enable = exiu_irq_enable, + .irq_mask = exiu_irq_mask, + .irq_unmask = exiu_irq_unmask, + .irq_set_type = exiu_irq_set_type, + .irq_set_affinity = irq_chip_set_affinity_parent, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_EOI_THREADED | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int exiu_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct exiu_irq_data *info = domain->host_data; + + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; + + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; /* No PPI should point to this domain */ + + *hwirq = fwspec->param[1] - info->spi_base; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + return 0; + } + return -EINVAL; +} + +static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + struct exiu_irq_data *info = dom->host_data; + irq_hw_number_t hwirq; + + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; /* No PPI should point to this domain */ + + WARN_ON(nr_irqs != 1); + hwirq = fwspec->param[1] - info->spi_base; + irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); + + parent_fwspec = *fwspec; + parent_fwspec.fwnode = dom->parent->fwnode; + return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); +} + +static const struct irq_domain_ops exiu_domain_ops = { + .translate = exiu_domain_translate, + .alloc = exiu_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int __init exiu_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + struct exiu_irq_data *data; + int err; + + if (!parent) { + pr_err("%pOF: no parent, giving up\n", node); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: unable to obtain parent domain\n", node); + return -ENXIO; + } + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) { + pr_err("%pOF: failed to parse 'spi-base' property\n", node); + err = -ENODEV; + goto out_free; + } + + data->base = of_iomap(node, 0); + if (IS_ERR(data->base)) { + err = PTR_ERR(data->base); + goto out_free; + } + + /* clear and mask all interrupts */ + writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR); + writel_relaxed(0xFFFFFFFF, data->base + EIMASK); + + domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node, + &exiu_domain_ops, data); + if (!domain) { + pr_err("%pOF: failed to allocate domain\n", node); + err = -ENOMEM; + goto out_unmap; + } + + pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS, + parent); + + return 0; + +out_unmap: + iounmap(data->base); +out_free: + kfree(data); + return err; +} +IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init);