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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id a3sm155223ljm.7.2020.08.28.04.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 04:39:34 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 2/2] target/microblaze: Improve transaction failure handling Date: Fri, 28 Aug 2020 13:39:31 +0200 Message-Id: <20200828113931.3252489-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828113931.3252489-1-edgar.iglesias@gmail.com> References: <20200828113931.3252489-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::243; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 13 X-Spam_score: 1.3 X-Spam_bar: + X-Spam_report: (1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=3.425, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, qemu-arm@nongnu.org, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" When the CPU has exceptions disabled, avoid unwinding CPU state and clobbering registers if we're not going to raise any exception. Signed-off-by: Edgar E. Iglesias --- target/microblaze/op_helper.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 13ac476199..190cd96c6a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -483,22 +483,17 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, cpu = MICROBLAZE_CPU(cs); env = &cpu->env; - cpu_restore_state(cs, retaddr, true); if (!(env->sregs[SR_MSR] & MSR_EE)) { return; } - env->sregs[SR_EAR] = addr; - if (access_type == MMU_INST_FETCH) { - if (cpu->cfg.iopb_bus_exception) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } - } else { - if (cpu->cfg.dopb_bus_exception) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } + if ((access_type == MMU_INST_FETCH && cpu->cfg.iopb_bus_exception) || + (access_type != MMU_INST_FETCH && cpu->cfg.dopb_bus_exception)) { + cpu_restore_state(cs, retaddr, true); + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? + ESR_EC_INSN_BUS : ESR_EC_DATA_BUS; + env->sregs[SR_EAR] = addr; + helper_raise_exception(env, EXCP_HW_EXCP); } } #endif