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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id z8sm5502642pfl.135.2017.11.02.03.13.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Nov 2017 03:13:16 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Thu, 2 Nov 2017 15:43:08 +0530 Message-Id: <1509617589-22760-1-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich Subject: [Xen-devel] [PATCH 1/2] xen: Add support for initializing 16550 UART using ACPI X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, Xen supports only DT based initialization of 16550 UART. This patch adds support for initializing 16550 UART using ACPI SPCR table. Signed-off-by: Bhupinder Thakur --- CC: Andrew Cooper CC: George Dunlap CC: Ian Jackson CC: Jan Beulich CC: Konrad Rzeszutek Wilk CC: Stefano Stabellini CC: Tim Deegan CC: Wei Liu CC: Julien Grall xen/drivers/char/ns16550.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ xen/include/xen/8250-uart.h | 1 + 2 files changed, 58 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index e0f8199..b3f6d85 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1538,6 +1538,63 @@ DT_DEVICE_START(ns16550, "NS16550 UART", DEVICE_SERIAL) DT_DEVICE_END #endif /* HAS_DEVICE_TREE */ + +#ifdef CONFIG_ACPI +#include + +static int __init ns16550_acpi_uart_init(const void *data) +{ + struct ns16550 *uart; + acpi_status status; + struct acpi_table_spcr *spcr = NULL; + + status = acpi_get_table(ACPI_SIG_SPCR, 0, + (struct acpi_table_header **)&spcr); + + if ( ACPI_FAILURE(status) ) + { + printk("ns16550: Failed to get SPCR table\n"); + return -EINVAL; + } + + uart = &ns16550_com[0]; + + ns16550_init_common(uart); + + uart->baud = BAUD_AUTO; + uart->data_bits = 8; + uart->parity = spcr->parity; + uart->stop_bits = spcr->stop_bits; + uart->io_base = spcr->serial_port.address; + uart->irq = spcr->interrupt; + uart->reg_width = spcr->serial_port.bit_width/8; + uart->reg_shift = 0; + uart->io_size = UART_MAX_REG<reg_shift; + + irq_set_type(spcr->interrupt, spcr->interrupt_type); + + uart->vuart.base_addr = uart->io_base; + uart->vuart.size = uart->io_size; + uart->vuart.data_off = UART_THR <reg_shift; + uart->vuart.status_off = UART_LSR<reg_shift; + uart->vuart.status = UART_LSR_THRE|UART_LSR_TEMT; + + /* Register with generic serial driver. */ + serial_register_uart(uart - ns16550_com, &ns16550_driver, uart); + + return 0; +} + +ACPI_DEVICE_START(ns16550c, "16550 COMPAT UART", DEVICE_SERIAL) + .class_type = ACPI_DBG2_16550_COMPATIBLE, + .init = ns16550_acpi_uart_init, +ACPI_DEVICE_END +ACPI_DEVICE_START(ns16550s, "16550 SUBSET UART", DEVICE_SERIAL) + .class_type = ACPI_DBG2_16550_SUBSET, + .init = ns16550_acpi_uart_init, +ACPI_DEVICE_END + +#endif /* * Local variables: * mode: C diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h index 5c3bac3..1b3e137 100644 --- a/xen/include/xen/8250-uart.h +++ b/xen/include/xen/8250-uart.h @@ -35,6 +35,7 @@ #define UART_USR 0x1f /* Status register (DW) */ #define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */ #define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */ +#define UART_MAX_REG (UART_USR+1) /* Interrupt Enable Register */ #define UART_IER_ERDAI 0x01 /* rx data recv'd */ From patchwork Thu Nov 2 10:13:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupinder Thakur X-Patchwork-Id: 117768 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1969810qgn; Thu, 2 Nov 2017 03:15:34 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RnjpO7UwCO5U91VLmijOe+i1Vvw0u4mVb9F+ey9omi6YfYhqqp2hceNdjUySYtWEOUOVUF X-Received: by 10.36.76.1 with SMTP id a1mr1871246itb.94.1509617734409; Thu, 02 Nov 2017 03:15:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509617734; cv=none; d=google.com; s=arc-20160816; b=mC6JXTz0P6vqMrycDqv8+3JWToaNh89evOUMcOdL7bxqHc+78LCkl7SYKXl3EIzHA7 XdpDuVex6UboQbhYBfNLVa2TxL/skS/moPsd+9yr7kInRU07NCxdTo3oEfkfg4aeSyNs +m1GrvtZtwzB/2UP7SRV9+DCewe4h6lxxwC/YOfJDY+xPtybJqoTJ6VQI8BpRXHTSC77 L3Uc4cRTxepHOqHllc5ER/bG9vhqCviXtVzYphUYOWElpzNb5i/WWwOo6yv625M3ICnZ 514pt7vHer+J/JhpH8108wwl8pX2BSnHH+uWLIN2Z7SqZKLNIdjfFEKAzOlK6CYQn8gQ MonA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=IDDm684zAGaCPRmNFHJz6j0dJK7tdQGbCHDiEYGwjqA=; b=Bo1/GXO+SqphOJy8cXUzcoCO1+e7tJoYyVr9OfdJ5kI4Zs2LG3P4Iqth5bLfOBuTYd SkywEnmJaxy2ubN7HSn80HI6wyBwq9kuqHFfAUBuzfkOz+zpc0J+JsooXAM+vPJ5d8Lw 3t3rrL62uAXYWmGSI1+XQSso9we0JiHV2QZ6DiNbAkXns8B6mlZRIPEzhJQg96YOnjXl ozEWTShMRH0SFIoCBE42PuQ/ohGroT0kVZD/88HaJJP6d8TARkmVtkAJ7dA/v5cHHBIw JwWSCsATxSpTyzQRYmQMEJOSOgnJpXEg167h9lWp0UfQZ4332Jn9L1IQWTUSD0rKesXq sGtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jUnMxKWB; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id z8sm5502642pfl.135.2017.11.02.03.13.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Nov 2017 03:13:20 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Thu, 2 Nov 2017 15:43:09 +0530 Message-Id: <1509617589-22760-2-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509617589-22760-1-git-send-email-bhupinder.thakur@linaro.org> References: <1509617589-22760-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich Subject: [Xen-devel] [PATCH 2/2] xen: Fix 16550 UART console for HP Moonshot (Aarch64) platform X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The console was not working on HP Moonshot (HPE Proliant Aarch64) because the UART registers were accessed as 8-bit aligned addresses. However, registers are 32-bit aligned for HP Moonshot. Since ACPI/SPCR table does not specify the register shift to be applied to the register offset, this patch implements an erratum to correctly set the register shift for HP Moonshot. Similar erratum was implemented in linux: commit 79a648328d2a604524a30523ca763fbeca0f70e3 Author: Loc Ho Date: Mon Jul 3 14:33:09 2017 -0700 ACPI: SPCR: Workaround for APM X-Gene 8250 UART 32-alignment errata APM X-Gene verion 1 and 2 have an 8250 UART with its register aligned to 32-bit. In addition, the latest released BIOS encodes the access field as 8-bit access instead 32-bit access. This causes no console with ACPI boot as the console will not match X-Gene UART port due to the lack of mmio32 option. Signed-off-by: Loc Ho Acked-by: Greg Kroah-Hartman Signed-off-by: Rafael J. Wysocki Signed-off-by: Bhupinder Thakur --- CC: Andrew Cooper CC: George Dunlap CC: Ian Jackson CC: Jan Beulich CC: Konrad Rzeszutek Wilk CC: Stefano Stabellini CC: Tim Deegan CC: Wei Liu CC: Julien Grall xen/drivers/char/ns16550.c | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index b3f6d85..e716aba 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1542,6 +1542,33 @@ DT_DEVICE_END #ifdef CONFIG_ACPI #include +/* + * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its + * register aligned to 32-bit. In addition, the BIOS also encoded the + * access width to be 8 bits. This function detects this errata condition. + */ +static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb) +{ + bool xgene_8250 = false; + + if ( tb->interface_type != ACPI_DBG2_16550_COMPATIBLE ) + return false; + + if ( memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) && + memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE) ) + return false; + + if ( !memcmp(tb->header.oem_table_id, "XGENESPC", + ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0 ) + xgene_8250 = true; + + if ( !memcmp(tb->header.oem_table_id, "ProLiant", + ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1 ) + xgene_8250 = true; + + return xgene_8250; +} + static int __init ns16550_acpi_uart_init(const void *data) { struct ns16550 *uart; @@ -1568,9 +1595,20 @@ static int __init ns16550_acpi_uart_init(const void *data) uart->io_base = spcr->serial_port.address; uart->irq = spcr->interrupt; uart->reg_width = spcr->serial_port.bit_width/8; - uart->reg_shift = 0; - uart->io_size = UART_MAX_REG<reg_shift; + if ( xgene_8250_erratum_present(spcr) ) + { + /* + * for xgene v1 and v2 the registers are 32-bit and so a + * register shift of 2 has to be applied to get the + * correct register offset. + */ + uart->reg_shift = 2; + } + else + uart->reg_shift = 0; + + uart->io_size = UART_MAX_REG<reg_shift; irq_set_type(spcr->interrupt, spcr->interrupt_type); uart->vuart.base_addr = uart->io_base;