From patchwork Tue Oct 13 14:45:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 287336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E923C433E7 for ; Tue, 13 Oct 2020 14:45:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B249324893 for ; Tue, 13 Oct 2020 14:45:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="vJzCHegg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388948AbgJMOpe (ORCPT ); Tue, 13 Oct 2020 10:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388880AbgJMOpe (ORCPT ); Tue, 13 Oct 2020 10:45:34 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4B06C0613D5 for ; Tue, 13 Oct 2020 07:45:33 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id b1so19049581lfp.11 for ; Tue, 13 Oct 2020 07:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=jlIMHmRJzRdhdiHnj8E8zCbvxaVzpiEGp2QpRRia+RU=; b=vJzCHeggFHVLBcDajiEGnH9kPwV0axI0dKUEtK3EgLI6EdXYAU7/mWGlFLi/H3QNp5 c1S6oWHuRfxPHqyx4h0B5PNAWE1l5mBOG1M7gQYT+fcdE/T8IG2b1JliGtCbKIejTHcq Y5K9wAQNgHBeCrceN3NBoKgcDzcjBr9O3JGkk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=jlIMHmRJzRdhdiHnj8E8zCbvxaVzpiEGp2QpRRia+RU=; b=I8vBs6AV1ezqBLe8p3n3ky60c1l10xTydPUe5ZTyewJmcrrOf0n4VGaljG4ljuqngJ 692KOFkPYTqc34YK8MIpoSUdzTSg6ojSuM20I+bXvvev9Q+WOBn5Tc/asWRTMwFTLwCw CIC48Fqh1S0k/k+iH0xCvZhbvUn6+2PzcV8JPcgNxqQRd8Zmc8/CIV4x4xVO1ETR1D5p b7k3jhD9//xfvz+o5evxhtTep/9PbKyQWy80HzRZEKYWSMrteD1R+Qf3wxFUCrzSMlpl kHrTzfo9cSXwtJinm4yfWgDhuMmIF1xMTCV0VUtBjFnAZIUMhcgwp9Ty+uIzeRs2U+Rz Uo1Q== X-Gm-Message-State: AOAM5335MKXD1uUVXRnTrxQdPM8kTjaJKBJ3uejBo6C2YCDplIpLY/Om oQdn+JNdxlJJ46NP4G5c21KSWQ== X-Google-Smtp-Source: ABdhPJw7dq7jgtXKc/GuCVJ2dgz7UjE/8XjamhQlnHEOveKXv/uAZKy91+OxOuQ0PmgFc/JNiH0p4Q== X-Received: by 2002:a19:3859:: with SMTP id d25mr11166271lfj.179.1602600332185; Tue, 13 Oct 2020 07:45:32 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id l129sm4452924lfd.191.2020.10.13.07.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 07:45:31 -0700 (PDT) Date: Tue, 13 Oct 2020 16:45:24 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v12 1/5] dt-bindings: vendor: add vendor prefix for LiteX Message-ID: <20201013164454.2002023-1-mholenko@antmicro.com> References: <20201013164454.2002023-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201013164454.2002023-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski Add vendor prefix for LiteX SoC builder. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Acked-by: Rob Herring --- Notes: No changes in v12. No changes in v11. No changes in v10. No changes in v9. No changes in v8. No changes in v7. No changes in v6. No changes in v5. No changes in v4. Changes in v3: - added Acked-by tag No changes in v2. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d3891386d671..9aae6c56d7a3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -571,6 +571,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^litex,.*": + description: LiteX SoC builder "^lltc,.*": description: Linear Technology Corporation "^logicpd,.*": From patchwork Tue Oct 13 14:45:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 269836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31320C433DF for ; Tue, 13 Oct 2020 14:45:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D83E92488C for ; Tue, 13 Oct 2020 14:45:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="Ap1hDLxK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389000AbgJMOpt (ORCPT ); Tue, 13 Oct 2020 10:45:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388992AbgJMOpt (ORCPT ); Tue, 13 Oct 2020 10:45:49 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7821C0613D5 for ; Tue, 13 Oct 2020 07:45:47 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id l28so7107251lfp.10 for ; Tue, 13 Oct 2020 07:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=pJiypWtRSWGeA7qvGozCNTMcITV17kuSzo6s5k3yp0c=; b=Ap1hDLxKbZkfleLmsjHoYjiy28861EusmWSvaGnN18GXwiUwqo+45d8ucMkH5ORbIf f+WP8dmVnjmPjdfCJ2ai+mdU3DJF5gQ6AW2ftlfnR7rLgm8oR1PFkRkTZnK40WFEu+Y0 shcI5xjGascCEm9BQluFvr5KMJq0AM2AQ4wOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=pJiypWtRSWGeA7qvGozCNTMcITV17kuSzo6s5k3yp0c=; b=k8p6rPW+974jdyJkwxSKkqGozmilA5tjUazRsWXNp89aBOdKYVBmEpsKaREWLObFw7 BYXGKhYSZ4HHg1sjdCTcB5kCCaiHbdZ9VOBiJZ/tGAf7GXNxgbd3buEZMBFiTiHFrAVr /uwHuqSQShnEbRQ8PdSTwIn00AmImhR3Z9DhdBI5S4D+nhEuzffXWx6kUGtfRKVONviq Ae4f0w5mAwTd0n3BNG94ENISdTSwRi+52cM0Fw6UOS33W/EW5oY8X3eWn/YHe7EKwwgb PGIrAxSC6iFjCeXhtrouHo0WJozLiqlym36jPGr9zdettJhXbaCRcAWWgPZNEvOLz/+6 48UQ== X-Gm-Message-State: AOAM531nh8jBKGQnrNqAtkaqnEF1d+c6xwW+B0X3bBFgRBH3viLPzEDP jKdn9vTleGPQ/vUTX9OdH/2Ymw== X-Google-Smtp-Source: ABdhPJzdCS2hRhUwwM98BhE9GUIZoNmvjOpWxz8AWxl855PrVpwphnpEHcu0tXGfCY+abzv0n/z7Sw== X-Received: by 2002:a19:2302:: with SMTP id j2mr8897933lfj.78.1602600346272; Tue, 13 Oct 2020 07:45:46 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id m30sm4506250lfc.97.2020.10.13.07.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 07:45:45 -0700 (PDT) Date: Tue, 13 Oct 2020 16:45:40 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v12 2/5] dt-bindings: soc: document LiteX SoC Controller bindings Message-ID: <20201013164454.2002023-2-mholenko@antmicro.com> References: <20201013164454.2002023-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201013164454.2002023-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pawel Czarnecki Add documentation for LiteX SoC Controller bindings. Signed-off-by: Pawel Czarnecki Signed-off-by: Mateusz Holenko Reviewed-by: Rob Herring --- Notes: Changes in v12: - fixed the description and the example in the yaml file No changes in v11. No changes in v10. Changes in v9: - fixed the `reg` node notation in the DT example No changes in v8. No changes in v7. Changes in v6: - fixed license header Changes in v5: - added reviewed-by tag Changes in v4: - changes compatible to "litex,soc-controller" - fixed yaml's header - removed unnecessary sections from yaml - fixed indentation in yaml This commit has been introduced in v3 of the patchset. .../soc/litex/litex,soc-controller.yaml | 39 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml b/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml new file mode 100644 index 000000000000..53121c1fbe4d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2020 Antmicro +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: LiteX SoC Controller driver + +description: | + This is the SoC Controller driver for the LiteX SoC Builder. + Its purpose is to verify LiteX CSR (Control&Status Register) access + operations and provide functions for other drivers to read/write CSRs + and to check if those accessors are ready to be used. + +maintainers: + - Karol Gugala + - Mateusz Holenko + +properties: + compatible: + const: litex,soc-controller + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + soc_ctrl0: soc-controller@f0000000 { + compatible = "litex,soc-controller"; + reg = <0xf0000000 0xc>; + status = "okay"; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7b58ca29cc80..39be98db7418 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9835,6 +9835,12 @@ L: kunit-dev@googlegroups.com S: Maintained F: lib/list-test.c +LITEX PLATFORM +M: Karol Gugala +M: Mateusz Holenko +S: Maintained +F: Documentation/devicetree/bindings/*/litex,*.yaml + LIVE PATCHING M: Josh Poimboeuf M: Jiri Kosina From patchwork Tue Oct 13 14:45:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 287335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 450DBC43467 for ; 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[77.65.79.196]) by smtp.gmail.com with ESMTPSA id v13sm3957561ljh.66.2020.10.13.07.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 07:45:57 -0700 (PDT) Date: Tue, 13 Oct 2020 16:45:52 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v12 3/5] drivers/soc/litex: add LiteX SoC Controller driver Message-ID: <20201013164454.2002023-3-mholenko@antmicro.com> References: <20201013164454.2002023-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201013164454.2002023-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pawel Czarnecki This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder. Co-developed-by: Mateusz Holenko Signed-off-by: Mateusz Holenko Signed-off-by: Pawel Czarnecki --- Notes: Changes in v12: - removed unnecssary WARN on a failed validation (panic is enough) - simplified probe implementation - introduced litex_{read,write}{8,16,32,64}() fast accessors - added formal documentation of litex_get_reg()/litex_set_reg() - added LITEX config symbol - removed unnecessary header include - removed spin locks from CSR accessors Changes in v11: - removed an unnecessary comment left over from previous version - changed a multi-line comment to comply with the formatting rules - use WARN instad of BUG on a failed CSR validation Changes in v10: - added casting to avoid sparse warnings in the SoC Controller's driver Changes in v9: - added exporting of the `litex_set_reg`/`litex_get_reg` symbols Changes in v8: - removed `litex_check_accessors()` helper function - added crashing (BUG) on the failed LiteX CSR access test No changes in v7. Changes in v6: - added dependency on OF || COMPILE_TEST - used le32_to_cpu(readl(addr)) instead of __raw_readl and writel(cpu_to_le32(value), addr) instead of __raw_writel to take advantage of memory barriers provided by readl/writel Changes in v5: - removed helper accessors and used __raw_readl/__raw_writel instead - fixed checking for errors in litex_soc_ctrl_probe Changes in v4: - fixed indent in Kconfig's help section - fixed copyright header - changed compatible to "litex,soc-controller" - simplified litex_soc_ctrl_probe - removed unnecessary litex_soc_ctrl_remove This commit has been introduced in v3 of the patchset. It includes a simplified version of common 'litex.h' header introduced in v2 of the patchset. MAINTAINERS | 2 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/litex/Kconfig | 19 ++++ drivers/soc/litex/Makefile | 3 + drivers/soc/litex/litex_soc_ctrl.c | 178 +++++++++++++++++++++++++++++ include/linux/litex.h | 103 ++++++++++++++++ 7 files changed, 307 insertions(+) create mode 100644 drivers/soc/litex/Kconfig create mode 100644 drivers/soc/litex/Makefile create mode 100644 drivers/soc/litex/litex_soc_ctrl.c create mode 100644 include/linux/litex.h diff --git a/MAINTAINERS b/MAINTAINERS index 39be98db7418..4d70a1b22a87 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9840,6 +9840,8 @@ M: Karol Gugala M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml +F: drivers/soc/litex/litex_soc_ctrl.c +F: include/linux/litex.h LIVE PATCHING M: Josh Poimboeuf diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..d097d070f579 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..0b16108823ef 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/litex/Kconfig b/drivers/soc/litex/Kconfig new file mode 100644 index 000000000000..c974ec3846bc --- /dev/null +++ b/drivers/soc/litex/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License_Identifier: GPL-2.0 + +menu "Enable LiteX SoC Builder specific drivers" + +config LITEX + bool + +config LITEX_SOC_CONTROLLER + tristate "Enable LiteX SoC Controller driver" + depends on OF || COMPILE_TEST + select LITEX + help + This option enables the SoC Controller Driver which verifies + LiteX CSR access and provides common litex_get_reg/litex_set_reg + accessors. + All drivers that use functions from litex.h must depend on + LITEX. + +endmenu diff --git a/drivers/soc/litex/Makefile b/drivers/soc/litex/Makefile new file mode 100644 index 000000000000..98ff7325b1c0 --- /dev/null +++ b/drivers/soc/litex/Makefile @@ -0,0 +1,3 @@ +# SPDX-License_Identifier: GPL-2.0 + +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex_soc_ctrl.o diff --git a/drivers/soc/litex/litex_soc_ctrl.c b/drivers/soc/litex/litex_soc_ctrl.c new file mode 100644 index 000000000000..08330c9872b0 --- /dev/null +++ b/drivers/soc/litex/litex_soc_ctrl.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteX SoC Controller Driver + * + * Copyright (C) 2020 Antmicro + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * LiteX SoC Generator, depending on the configuration, can split a single + * logical CSR (Control&Status Register) into a series of consecutive physical + * registers. + * + * For example, in the configuration with 8-bit CSR Bus, 32-bit aligned (the + * default one for 32-bit CPUs) a 32-bit logical CSR will be generated as four + * 32-bit physical registers, each one containing one byte of meaningful data. + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + * + * The purpose of `litex_set_reg`/`litex_get_reg` is to implement the logic + * of writing to/reading from the LiteX CSR in a single place that can be + * then reused by all LiteX drivers. + */ + +/** + * litex_set_reg() - Writes the value to the LiteX CSR (Control&Status Register) + * @reg: Address of the CSR + * @reg_size: The width of the CSR expressed in the number of bytes + * @val: Value to be written to the CSR + * + * In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned), + * a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers, + * each one containing one byte of meaningful data. + * + * This function splits a single possibly multi-byte write into a series of + * single-byte writes with a proper offset. + */ +void litex_set_reg(void __iomem *reg, unsigned long reg_size, + unsigned long val) +{ + unsigned long shifted_data, shift, i; + + for (i = 0; i < reg_size; ++i) { + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + shifted_data = val >> shift; + + WRITE_LITEX_SUBREGISTER(shifted_data, reg, i); + } +} +EXPORT_SYMBOL_GPL(litex_set_reg); + +/** + * litex_get_reg() - Reads the value of the LiteX CSR (Control&Status Register) + * @reg: Address of the CSR + * @reg_size: The width of the CSR expressed in the number of bytes + * + * Return: Value read from the CSR + * + * In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned), + * a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers, + * each one containing one byte of meaningful data. + * + * This function generates a series of single-byte reads with a proper offset + * and joins their results into a single multi-byte value. + */ +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size) +{ + unsigned long shifted_data, shift, i; + unsigned long result = 0; + + for (i = 0; i < reg_size; ++i) { + shifted_data = READ_LITEX_SUBREGISTER(reg, i); + + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + result |= (shifted_data << shift); + } + + return result; +} +EXPORT_SYMBOL_GPL(litex_get_reg); + +#define SCRATCH_REG_OFF 0x04 +#define SCRATCH_REG_VALUE 0x12345678 +#define SCRATCH_TEST_VALUE 0xdeadbeef + +/* + * Check LiteX CSR read/write access + * + * This function reads and writes a scratch register in order to verify if CSR + * access works. + * + * In case any problems are detected, the driver should panic. + * + * Access to the LiteX CSR is, by design, done in CPU native endianness. + * The driver should not dynamically configure access functions when + * the endianness mismatch is detected. Such situation indicates problems in + * the soft SoC design and should be solved at the LiteX generator level, + * not in the software. + */ +static int litex_check_csr_access(void __iomem *reg_addr) +{ + unsigned long reg; + + reg = litex_read32(reg_addr + SCRATCH_REG_OFF); + + if (reg != SCRATCH_REG_VALUE) { + panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx", + SCRATCH_REG_VALUE, reg); + return -EINVAL; + } + + litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE); + reg = litex_read32(reg_addr + SCRATCH_REG_OFF); + + if (reg != SCRATCH_TEST_VALUE) { + panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx", + SCRATCH_TEST_VALUE, reg); + return -EINVAL; + } + + /* restore original value of the SCRATCH register */ + litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE); + + pr_info("LiteX SoC Controller driver initialized"); + + return 0; +} + +struct litex_soc_ctrl_device { + void __iomem *base; +}; + +static const struct of_device_id litex_soc_ctrl_of_match[] = { + {.compatible = "litex,soc-controller"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match); + +static int litex_soc_ctrl_probe(struct platform_device *pdev) +{ + struct litex_soc_ctrl_device *soc_ctrl_dev; + + soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL); + if (!soc_ctrl_dev) + return -ENOMEM; + + soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(soc_ctrl_dev->base)) + return PTR_ERR(soc_ctrl_dev->base); + + return litex_check_csr_access(soc_ctrl_dev->base); +} + +static struct platform_driver litex_soc_ctrl_driver = { + .driver = { + .name = "litex-soc-controller", + .of_match_table = of_match_ptr(litex_soc_ctrl_of_match) + }, + .probe = litex_soc_ctrl_probe, +}; + +module_platform_driver(litex_soc_ctrl_driver); +MODULE_DESCRIPTION("LiteX SoC Controller driver"); +MODULE_AUTHOR("Antmicro "); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..72061018c172 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Implementation of the functions is provided by + * the LiteX SoC Controller driver. + * + * Copyright (C) 2019-2020 Antmicro + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include +#include +#include + +/* + * The parameters below are true for LiteX SoCs configured for 8-bit CSR Bus, + * 32-bit aligned. + * + * Supporting other configurations will require extending the logic in this + * header and in the LiteX SoC controller driver. + */ +#define LITEX_REG_SIZE 0x4 +#define LITEX_SUBREG_SIZE 0x1 +#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8) + +#define WRITE_LITEX_SUBREGISTER(val, base_offset, subreg_id) \ + writel((u32 __force)cpu_to_le32(val), base_offset + (LITEX_REG_SIZE * subreg_id)) + +#define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \ + le32_to_cpu((__le32 __force)readl(base_offset + (LITEX_REG_SIZE * subreg_id))) + +void litex_set_reg(void __iomem *reg, unsigned long reg_sz, unsigned long val); + +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_sz); + +static inline void litex_write8(void __iomem *reg, u8 val) +{ + WRITE_LITEX_SUBREGISTER(val, reg, 0); +} + +static inline void litex_write16(void __iomem *reg, u16 val) +{ + WRITE_LITEX_SUBREGISTER(val >> 8, reg, 0); + WRITE_LITEX_SUBREGISTER(val, reg, 1); +} + +static inline void litex_write32(void __iomem *reg, u32 val) +{ + WRITE_LITEX_SUBREGISTER(val >> 24, reg, 0); + WRITE_LITEX_SUBREGISTER(val >> 16, reg, 1); + WRITE_LITEX_SUBREGISTER(val >> 8, reg, 2); + WRITE_LITEX_SUBREGISTER(val, reg, 3); +} + +static inline void litex_write64(void __iomem *reg, u64 val) +{ + WRITE_LITEX_SUBREGISTER(val >> 56, reg, 0); + WRITE_LITEX_SUBREGISTER(val >> 48, reg, 1); + WRITE_LITEX_SUBREGISTER(val >> 40, reg, 2); + WRITE_LITEX_SUBREGISTER(val >> 32, reg, 3); + WRITE_LITEX_SUBREGISTER(val >> 24, reg, 4); + WRITE_LITEX_SUBREGISTER(val >> 16, reg, 5); + WRITE_LITEX_SUBREGISTER(val >> 8, reg, 6); + WRITE_LITEX_SUBREGISTER(val, reg, 7); +} + +static inline u8 litex_read8(void __iomem *reg) +{ + return READ_LITEX_SUBREGISTER(reg, 0); +} + +static inline u16 litex_read16(void __iomem *reg) +{ + return (READ_LITEX_SUBREGISTER(reg, 0) << 8) + | (READ_LITEX_SUBREGISTER(reg, 1)); +} + +static inline u32 litex_read32(void __iomem *reg) +{ + return (READ_LITEX_SUBREGISTER(reg, 0) << 24) + | (READ_LITEX_SUBREGISTER(reg, 1) << 16) + | (READ_LITEX_SUBREGISTER(reg, 2) << 8) + | (READ_LITEX_SUBREGISTER(reg, 3)); +} + +static inline u64 litex_read64(void __iomem *reg) +{ + return ((u64)READ_LITEX_SUBREGISTER(reg, 0) << 56) + | ((u64)READ_LITEX_SUBREGISTER(reg, 1) << 48) + | ((u64)READ_LITEX_SUBREGISTER(reg, 2) << 40) + | ((u64)READ_LITEX_SUBREGISTER(reg, 3) << 32) + | ((u64)READ_LITEX_SUBREGISTER(reg, 4) << 24) + | ((u64)READ_LITEX_SUBREGISTER(reg, 5) << 16) + | ((u64)READ_LITEX_SUBREGISTER(reg, 6) << 8) + | ((u64)READ_LITEX_SUBREGISTER(reg, 7)); +} + +#endif /* _LINUX_LITEX_H */ From patchwork Tue Oct 13 14:46:05 2020 Content-Type: text/plain; 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[77.65.79.196]) by smtp.gmail.com with ESMTPSA id p10sm4555297lfc.217.2020.10.13.07.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 07:46:11 -0700 (PDT) Date: Tue, 13 Oct 2020 16:46:05 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v12 4/5] dt-bindings: serial: document LiteUART bindings Message-ID: <20201013164454.2002023-4-mholenko@antmicro.com> References: <20201013164454.2002023-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201013164454.2002023-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski Add documentation for LiteUART devicetree bindings. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Reviewed-by: Rob Herring --- Notes: Changes in v12: - fixed the description in the yaml file No changes in v11. No changes in v10. No changes in v9. No changes in v8. No changes in v7. Changes in v6: - fixed license header No changes in v5. No changes in v4. Changes in v3: - added Reviewed-by tag - patch number changed from 3 to 4 - removed changes in MAINTAINERS file (moved to patch #2) Changes in v2: - binding description rewritten to a yaml schema file - added interrupt line - fixed unit address - patch number changed from 2 to 3 .../bindings/serial/litex,liteuart.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/litex,liteuart.yaml diff --git a/Documentation/devicetree/bindings/serial/litex,liteuart.yaml b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml new file mode 100644 index 000000000000..69acb222bb57 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LiteUART serial controller + +maintainers: + - Karol Gugala + - Mateusz Holenko + +description: | + LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports + multiple CPU architectures, currently including e.g. OpenRISC and RISC-V. + +properties: + compatible: + const: litex,liteuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + uart0: serial@e0001800 { + compatible = "litex,liteuart"; + reg = <0xe0001800 0x100>; + interrupts = <2>; + }; From patchwork Tue Oct 13 14:46:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 287334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35DE7C433E7 for ; Tue, 13 Oct 2020 14:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B068424892 for ; Tue, 13 Oct 2020 14:46:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="KKqexCh5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727034AbgJMOqc (ORCPT ); Tue, 13 Oct 2020 10:46:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730236AbgJMOqb (ORCPT ); Tue, 13 Oct 2020 10:46:31 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66BA6C0613D2 for ; Tue, 13 Oct 2020 07:46:30 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id a5so20710038ljj.11 for ; Tue, 13 Oct 2020 07:46:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=VCGrvJGaLYrqcsI+Xcoyg2ZlK2Etbe8LNlVQiG020No=; b=KKqexCh5v/N2T1fImUle+pYUIe5fiGQBEoh+9aDi/9sijlD2y2LV1fPpE5/uwAeq13 L7C+mSwJGc6KewHrNP5vWxkNg4kqxfCJfXNZHLj+wmWvoC75oJfQS6LjoKBnm1fn2ZJa s9/N41sZoJOG7pQfbLjw/VgIabBOcAIXloW5Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=VCGrvJGaLYrqcsI+Xcoyg2ZlK2Etbe8LNlVQiG020No=; b=azr/VD5HodG6hWqvlH+3Aaaorh5QVX2epmb/kYvVJvOe/pRWnfjj7Xq1pVxTlcY0u7 gLjfj/IKYdBaKYW6JOykvp0Q7DoPbXbOqR/KU38nQhyLda0TymdG0/PJG1sgBzMn5VHZ /wUeSgqBz2lueaK6kF3QtoatSTkzXSc3N8jgdQJjY8jNr0CPezcogL20n0/M6ukKtWmO T7ilFLtuMwVq96Q6gB4WW2J6LjHjw0KRGB8NuG7cBl02oekiTgm0mQ/u5tzIbK2UJLYo 19o3rbf/Ii2/Qgro02xpkgxc9blgZY3NB+8cCPscPL+1MNNBcaBOMi5vsodzo98E7heA aiFw== X-Gm-Message-State: AOAM531O0E7PFpDgSCJZ1PcaKIjEf/6xsAFjGdFiPtreiBpjHiaY+po3 I2arbkK8KebdTBgRSHOn0AB0bQ== X-Google-Smtp-Source: ABdhPJzMmFCcfFLBoKG7h7cnmSED5g5lMtdjUHwxScl1XxImBpxWOkOxA8Wo0IBqtX8vASMjoOkDVQ== X-Received: by 2002:a2e:82c7:: with SMTP id n7mr10466651ljh.59.1602600388763; Tue, 13 Oct 2020 07:46:28 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id 73sm4521223lff.125.2020.10.13.07.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 07:46:27 -0700 (PDT) Date: Tue, 13 Oct 2020 16:46:21 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v12 5/5] drivers/tty/serial: add LiteUART driver Message-ID: <20201013164454.2002023-5-mholenko@antmicro.com> References: <20201013164454.2002023-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201013164454.2002023-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski This commit adds driver for the FPGA-based LiteUART serial controller from LiteX SoC builder. The current implementation supports LiteUART configured for 32 bit data width and 8 bit CSR bus width. It does not support IRQ. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Reviewed-by: Greg Kroah-Hartman --- Notes: Changes in v12: - added xa_erase call in remove function - used devm_kzalloc instead of kzalloc - simplified probe implementation - switched to non-loop based LiteX CSR accessors - switched config dependency from LITEX_SOC_CONTROLLER to LITEX Changes in v11: - added Reviewed-by tag No changes in v10. No changes in v9. Changes in v8: - fixed help messages in LiteUART's KConfig - removed dependency between LiteUART and LiteX SoC drivers Changed in v7: - added missing include directive Changes in v6: - LiteUART ports now stored in xArray - removed PORT_LITEUART - fixed formatting - removed some unnecessary defines No changes in v5. Changes in v4: - fixed copyright header - removed a wrong dependency on UARTLITE from Kconfig - added a dependency on LITEX_SOC_CONTROLLER to LITEUART in Kconfig Changes in v3: - aliases made optional - used litex_get_reg/litex_set_reg functions instead of macros - SERIAL_LITEUART_NR_PORTS renamed to SERIAL_LITEUART_MAX_PORTS - PORT_LITEUART changed from 122 to 123 - added dependency on LITEX_SOC_CONTROLLER - patch number changed from 4 to 5 No changes in v2. MAINTAINERS | 1 + drivers/tty/serial/Kconfig | 32 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/liteuart.c | 404 ++++++++++++++++++++++++++++++++++ 4 files changed, 438 insertions(+) create mode 100644 drivers/tty/serial/liteuart.c diff --git a/MAINTAINERS b/MAINTAINERS index 8136620d4f35..c0a76996619b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10124,6 +10124,7 @@ M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml F: drivers/soc/litex/litex_soc_ctrl.c +F: drivers/tty/serial/liteuart.c F: include/linux/litex.h LIVE PATCHING diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 9409be982aa6..8bf247e3214a 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1580,6 +1580,38 @@ config SERIAL_MILBEAUT_USIO_CONSOLE receives all kernel messages and warnings and which allows logins in single user mode). +config SERIAL_LITEUART + tristate "LiteUART serial port support" + depends on HAS_IOMEM + depends on OF || COMPILE_TEST + depends on LITEX + select SERIAL_CORE + help + This driver is for the FPGA-based LiteUART serial controller from LiteX + SoC builder. + + Say 'Y' or 'M' here if you wish to use the LiteUART serial controller. + Otherwise, say 'N'. + +config SERIAL_LITEUART_MAX_PORTS + int "Maximum number of LiteUART ports" + depends on SERIAL_LITEUART + default "1" + help + Set this to the maximum number of serial ports you want the driver + to support. + +config SERIAL_LITEUART_CONSOLE + bool "LiteUART serial port console support" + depends on SERIAL_LITEUART=y + select SERIAL_CORE_CONSOLE + help + Say 'Y' or 'M' here if you wish to use the FPGA-based LiteUART serial + controller from LiteX SoC builder as the system console + (the system console is the device which receives all kernel messages + and warnings and which allows logins in single user mode). + Otherwise, say 'N'. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index caf167f0c10a..ed4be0ebab8d 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o +obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/liteuart.c b/drivers/tty/serial/liteuart.c new file mode 100644 index 000000000000..0bf6bff84fff --- /dev/null +++ b/drivers/tty/serial/liteuart.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteUART serial controller (LiteX) Driver + * + * Copyright (C) 2019-2020 Antmicro + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * CSRs definitions (base address offsets + width) + * + * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus, + * 32-bit aligned. + * + * Supporting other configurations might require new definitions or a more + * generic way of indexing the LiteX CSRs. + * + * For more details on how CSRs are defined and handled in LiteX, see comments + * in the LiteX SoC Driver: drivers/soc/litex/litex_soc_ctrl.c + */ +#define OFF_RXTX 0x00 +#define OFF_TXFULL 0x04 +#define OFF_RXEMPTY 0x08 +#define OFF_EV_STATUS 0x0c +#define OFF_EV_PENDING 0x10 +#define OFF_EV_ENABLE 0x14 + +/* events */ +#define EV_TX 0x1 +#define EV_RX 0x2 + +struct liteuart_port { + struct uart_port port; + struct timer_list timer; + u32 id; +}; + +#define to_liteuart_port(port) container_of(port, struct liteuart_port, port) + +static DEFINE_XARRAY_FLAGS(liteuart_array, XA_FLAGS_ALLOC); + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE +static struct console liteuart_console; +#endif + +static struct uart_driver liteuart_driver = { + .owner = THIS_MODULE, + .driver_name = "liteuart", + .dev_name = "ttyLXU", + .major = 0, + .minor = 0, + .nr = CONFIG_SERIAL_LITEUART_MAX_PORTS, +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + .cons = &liteuart_console, +#endif +}; + +static void liteuart_timer(struct timer_list *t) +{ + struct liteuart_port *uart = from_timer(uart, t, timer); + struct uart_port *port = &uart->port; + unsigned char __iomem *membase = port->membase; + unsigned int flg = TTY_NORMAL; + int ch; + unsigned long status; + + while ((status = !litex_read8(membase + OFF_RXEMPTY)) == 1) { + ch = litex_read8(membase + OFF_RXTX); + port->icount.rx++; + + /* necessary for RXEMPTY to refresh its value */ + litex_write8(membase + OFF_EV_PENDING, EV_TX | EV_RX); + + /* no overflow bits in status */ + if (!(uart_handle_sysrq_char(port, ch))) + uart_insert_char(port, status, 0, ch, flg); + + tty_flip_buffer_push(&port->state->port); + } + + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); +} + +static void liteuart_putchar(struct uart_port *port, int ch) +{ + while (litex_read8(port->membase + OFF_TXFULL)) + cpu_relax(); + + litex_write8(port->membase + OFF_RXTX, ch); +} + +static unsigned int liteuart_tx_empty(struct uart_port *port) +{ + /* not really tx empty, just checking if tx is not full */ + if (!litex_read8(port->membase + OFF_TXFULL)) + return TIOCSER_TEMT; + + return 0; +} + +static void liteuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* modem control register is not present in LiteUART */ +} + +static unsigned int liteuart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; +} + +static void liteuart_stop_tx(struct uart_port *port) +{ +} + +static void liteuart_start_tx(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + unsigned char ch; + + if (unlikely(port->x_char)) { + litex_write8(port->membase + OFF_RXTX, port->x_char); + port->icount.tx++; + port->x_char = 0; + } else if (!uart_circ_empty(xmit)) { + while (xmit->head != xmit->tail) { + ch = xmit->buf[xmit->tail]; + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + liteuart_putchar(port, ch); + } + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static void liteuart_stop_rx(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* just delete timer */ + del_timer(&uart->timer); +} + +static void liteuart_break_ctl(struct uart_port *port, int break_state) +{ + /* LiteUART doesn't support sending break signal */ +} + +static int liteuart_startup(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* disable events */ + litex_write8(port->membase + OFF_EV_ENABLE, 0); + + /* prepare timer for polling */ + timer_setup(&uart->timer, liteuart_timer, 0); + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + + return 0; +} + +static void liteuart_shutdown(struct uart_port *port) +{ +} + +static void liteuart_set_termios(struct uart_port *port, struct ktermios *new, + struct ktermios *old) +{ + unsigned int baud; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + /* update baudrate */ + baud = uart_get_baud_rate(port, new, old, 0, 460800); + uart_update_timeout(port, new->c_cflag, baud); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *liteuart_type(struct uart_port *port) +{ + return "liteuart"; +} + +static void liteuart_release_port(struct uart_port *port) +{ +} + +static int liteuart_request_port(struct uart_port *port) +{ + return 0; +} + +static void liteuart_config_port(struct uart_port *port, int flags) +{ + /* + * Driver core for serial ports forces a non-zero value for port type. + * Write an arbitrary value here to accommodate the serial core driver, + * as ID part of UAPI is redundant. + */ + port->type = 1; +} + +static int liteuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (port->type != PORT_UNKNOWN && ser->type != 1) + return -EINVAL; + + return 0; +} + +static const struct uart_ops liteuart_ops = { + .tx_empty = liteuart_tx_empty, + .set_mctrl = liteuart_set_mctrl, + .get_mctrl = liteuart_get_mctrl, + .stop_tx = liteuart_stop_tx, + .start_tx = liteuart_start_tx, + .stop_rx = liteuart_stop_rx, + .break_ctl = liteuart_break_ctl, + .startup = liteuart_startup, + .shutdown = liteuart_shutdown, + .set_termios = liteuart_set_termios, + .type = liteuart_type, + .release_port = liteuart_release_port, + .request_port = liteuart_request_port, + .config_port = liteuart_config_port, + .verify_port = liteuart_verify_port, +}; + +static int liteuart_probe(struct platform_device *pdev) +{ + struct liteuart_port *uart; + struct uart_port *port; + struct xa_limit limit; + int dev_id, ret; + + /* look for aliases; auto-enumerate for free index if not found */ + dev_id = of_alias_get_id(pdev->dev.of_node, "serial"); + if (dev_id < 0) + limit = XA_LIMIT(0, CONFIG_SERIAL_LITEUART_MAX_PORTS); + else + limit = XA_LIMIT(dev_id, dev_id); + + uart = devm_kzalloc(&pdev->dev, sizeof(struct liteuart_port), GFP_KERNEL); + if (!uart) + return -ENOMEM; + + ret = xa_alloc(&liteuart_array, &dev_id, uart, limit, GFP_KERNEL); + if (ret) + return ret; + + uart->id = dev_id; + port = &uart->port; + + /* get membase */ + port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (!port->membase) + return -ENXIO; + + /* values not from device tree */ + port->dev = &pdev->dev; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->ops = &liteuart_ops; + port->regshift = 2; + port->fifosize = 16; + port->iobase = 1; + port->type = PORT_UNKNOWN; + port->line = dev_id; + spin_lock_init(&port->lock); + + return uart_add_one_port(&liteuart_driver, &uart->port); +} + +static int liteuart_remove(struct platform_device *pdev) +{ + struct uart_port *port = platform_get_drvdata(pdev); + struct liteuart_port *uart = to_liteuart_port(port); + + xa_erase(&liteuart_array, uart->id); + + return 0; +} + +static const struct of_device_id liteuart_of_match[] = { + { .compatible = "litex,liteuart" }, + {} +}; +MODULE_DEVICE_TABLE(of, liteuart_of_match); + +static struct platform_driver liteuart_platform_driver = { + .probe = liteuart_probe, + .remove = liteuart_remove, + .driver = { + .name = "liteuart", + .of_match_table = liteuart_of_match, + }, +}; + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + +static void liteuart_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct liteuart_port *uart; + struct uart_port *port; + unsigned long flags; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + port = &uart->port; + + spin_lock_irqsave(&port->lock, flags); + uart_console_write(port, s, count, liteuart_putchar); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int liteuart_console_setup(struct console *co, char *options) +{ + struct liteuart_port *uart; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + if (!uart) + return -ENODEV; + + port = &uart->port; + if (!port->membase) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console liteuart_console = { + .name = "liteuart", + .write = liteuart_console_write, + .device = uart_console_device, + .setup = liteuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &liteuart_driver, +}; + +static int __init liteuart_console_init(void) +{ + register_console(&liteuart_console); + + return 0; +} +console_initcall(liteuart_console_init); +#endif /* CONFIG_SERIAL_LITEUART_CONSOLE */ + +static int __init liteuart_init(void) +{ + int res; + + res = uart_register_driver(&liteuart_driver); + if (res) + return res; + + res = platform_driver_register(&liteuart_platform_driver); + if (res) { + uart_unregister_driver(&liteuart_driver); + return res; + } + + return 0; +} + +static void __exit liteuart_exit(void) +{ + platform_driver_unregister(&liteuart_platform_driver); + uart_unregister_driver(&liteuart_driver); +} + +module_init(liteuart_init); +module_exit(liteuart_exit); + +MODULE_AUTHOR("Antmicro "); +MODULE_DESCRIPTION("LiteUART serial driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform: liteuart");