From patchwork Fri Oct 27 13:31:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 117357 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp777057qgn; Fri, 27 Oct 2017 06:31:57 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SdHPEZ9TyMLd2yQkwi7JOihrFWJDmhRYEHnJKvkVk1gzXoadc4O+zNDkeE43IP+PKWbgZR X-Received: by 10.98.166.205 with SMTP id r74mr481643pfl.285.1509111117879; Fri, 27 Oct 2017 06:31:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509111117; cv=none; d=google.com; s=arc-20160816; b=v3yaN+UITrSxAkCOKicVqp+1dAPx78Bf8231Zl/8raiumimqACb7wX0tS0VPCMaYyl q/LIIWI+Ito7Jur+y0tncx3M8mfe26HIlRgtXD+6JJQ9h0JFAtvxaW5vHXQDXhnUX5v6 QyFm4iPZuV2kuWORNoUcw0BKQmHXuzG04q8E4oLWyV1o23VhIgeUaSkpVEkkv+uncSfE FN8dXYmzPHfBaxUPO4XG0306FYTZaJEyy285NeVW6fXbbtqAtTG3fJmsABvhtVhhOkRi 0cOtWYFAzzXRsfC6CBLKiYsnR6v560H+HfTJ1eiKxyAQw0bSelORvLZp9wdmaHCDs9Jk gBKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:cc:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=+Tr4gyHw4udWC/Z8NYNuG0RcaYgHZVvFd8btSxL9KLs=; b=HmV+gsEeuGjXAe5y2zcsM4vqKkhOOvf77WVaHrEXXZetCPmfitY7r9/kZP+3uL1Fu2 pMdRw9FuDbGMFCkBma1p0xRKdgQ9nFSLkBzZkNcTjRXEswxr9Q2cM923O5LfvJz13nPX iZQ/ZhmqdMcssOj+vr3+qEqjqxsOiLGzoFzZIC89oYsVkBXldgOi7JmX6ee1T7RucryJ QCcs2Yo0HCDDWfuwj6l0PcQqnsUFWytT9a5Sh2+T6MbOeC/kD2Q4GQlQatARg7xaRrrL smyWfQv/a5MYdjIjAQekZLtqt18rN7jRjBg1jTAiXxUoH0v7+4Fw4XtOIS7E4yVnljUX Bt7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=QE1A8Wxr; spf=pass (google.com: domain of gcc-patches-return-465351-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465351-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id l1si4421823pld.541.2017.10.27.06.31.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Oct 2017 06:31:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-465351-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=QE1A8Wxr; spf=pass (google.com: domain of gcc-patches-return-465351-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465351-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; q=dns; s=default; b=DmYrOlVxUdmdpau5 cQ6ZRxK0AULXfJscnmgcTa7347EYd/J9rdf8yHsQk6lhf2mt7OeWiIofZsKPQojw GifkaJwtnzkAbAZerw38/8V26ToCV3Nhs1Scf+QSUCos294pSVAxOOcDP000apLb MmpWnC3MC5mEvvuzwVpKSCLYF9s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; s=default; bh=3gpQwM6SW9UGpHrpWOiAgA oHoeE=; b=QE1A8Wxr/Aa3Pm55TonqaPeRhlutcJt3xkYOr57WpBAcvDfyg5bKKC DkDc6obCR90ExbXL2wdmUssbtIXqAPVSwMOIvpLQEYqwetLiZD6MW89BTga4Pkoh 8n1vdZYwneyguqRKl7evWTKRwc6Fec4IvxuQ/RQTc2IoOhp+Ic+f0= Received: (qmail 78912 invoked by alias); 27 Oct 2017 13:31:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 78589 invoked by uid 89); 27 Oct 2017 13:31:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f181.google.com Received: from mail-wr0-f181.google.com (HELO mail-wr0-f181.google.com) (209.85.128.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Oct 2017 13:31:41 +0000 Received: by mail-wr0-f181.google.com with SMTP id o44so6156184wrf.11 for ; Fri, 27 Oct 2017 06:31:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version; bh=+Tr4gyHw4udWC/Z8NYNuG0RcaYgHZVvFd8btSxL9KLs=; b=HLJUkvoluKvD9v4V8g8tCBwdjPKJovVUlhzWYC7B6F66ZV/smZkMwvZ1jwOa2LaUjc Oj8vjetKq849OrYfwSoxEx1RyxTT1OwYfJHrl42qhTsEeDH1Dz/f7AOtQ+XDOiEnaojm MQCxRwz5NUJrRzfOak6HNwQimIjLH3QTdL7RlNbonKGk9ZlM0g672p/O8dppB8TppjG5 6cqs8Njh5tUR37a2eXZs2YRR3mzLnEO3ig2F9k45UY5aEaAYhUDHtUc+0geySLN094ZO HHX/nQtPoRnRtILj19f4RPvyYGVYQ9k1WnBiWEqQUtciwQRCtPLd+fCiDtNpiuMH/cde 9sFQ== X-Gm-Message-State: AMCzsaVCYNHNV1n8YEsZMrotU5NgcTHw58WAoUOlaGbMmHfWn+nu0uxf vAaHPJo/MLzvL7NpaOXyQceznw== X-Received: by 10.223.136.51 with SMTP id d48mr474437wrd.150.1509111098916; Fri, 27 Oct 2017 06:31:38 -0700 (PDT) Received: from localhost (188.29.164.51.threembb.co.uk. [188.29.164.51]) by smtp.gmail.com with ESMTPSA id b76sm1214817wmg.9.2017.10.27.06.31.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 06:31:38 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [12/nn] [AArch64] Add const_offset field to aarch64_address_info References: <873764d8y3.fsf@linaro.org> Date: Fri, 27 Oct 2017 14:31:35 +0100 In-Reply-To: <873764d8y3.fsf@linaro.org> (Richard Sandiford's message of "Fri, 27 Oct 2017 14:19:48 +0100") Message-ID: <87k1zgaf9k.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch records the integer value of the address offset in aarch64_address_info, so that it doesn't need to be re-extracted from the rtx. The SVE port will make more use of this. The patch also uses poly_int64 routines to manipulate the offset, rather than just handling CONST_INTs. 2017-10-27 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset field. (aarch64_classify_address): Initialize it. Track polynomial offsets. (aarch64_print_operand_address): Use it to check for a zero offset. Reviewed-by: James Greenhalgh Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-10-27 14:13:59.548121066 +0100 +++ gcc/config/aarch64/aarch64.c 2017-10-27 14:14:17.047874812 +0100 @@ -113,6 +113,7 @@ struct aarch64_address_info { enum aarch64_address_type type; rtx base; rtx offset; + poly_int64 const_offset; int shift; enum aarch64_symbol_type symbol_type; }; @@ -4728,6 +4729,8 @@ aarch64_classify_address (struct aarch64 { enum rtx_code code = GET_CODE (x); rtx op0, op1; + poly_int64 offset; + HOST_WIDE_INT const_size; /* On BE, we use load/store pair for all large int mode load/stores. @@ -4756,6 +4759,7 @@ aarch64_classify_address (struct aarch64 info->type = ADDRESS_REG_IMM; info->base = x; info->offset = const0_rtx; + info->const_offset = 0; return aarch64_base_register_rtx_p (x, strict_p); case PLUS: @@ -4765,24 +4769,24 @@ aarch64_classify_address (struct aarch64 if (! strict_p && REG_P (op0) && virt_or_elim_regno_p (REGNO (op0)) - && CONST_INT_P (op1)) + && poly_int_rtx_p (op1, &offset)) { info->type = ADDRESS_REG_IMM; info->base = op0; info->offset = op1; + info->const_offset = offset; return true; } if (may_ne (GET_MODE_SIZE (mode), 0) - && CONST_INT_P (op1) - && aarch64_base_register_rtx_p (op0, strict_p)) + && aarch64_base_register_rtx_p (op0, strict_p) + && poly_int_rtx_p (op1, &offset)) { - HOST_WIDE_INT offset = INTVAL (op1); - info->type = ADDRESS_REG_IMM; info->base = op0; info->offset = op1; + info->const_offset = offset; /* TImode and TFmode values are allowed in both pairs of X registers and individual Q registers. The available @@ -4862,13 +4866,12 @@ aarch64_classify_address (struct aarch64 info->type = ADDRESS_REG_WB; info->base = XEXP (x, 0); if (GET_CODE (XEXP (x, 1)) == PLUS - && CONST_INT_P (XEXP (XEXP (x, 1), 1)) + && poly_int_rtx_p (XEXP (XEXP (x, 1), 1), &offset) && rtx_equal_p (XEXP (XEXP (x, 1), 0), info->base) && aarch64_base_register_rtx_p (info->base, strict_p)) { - HOST_WIDE_INT offset; info->offset = XEXP (XEXP (x, 1), 1); - offset = INTVAL (info->offset); + info->const_offset = offset; /* TImode and TFmode values are allowed in both pairs of X registers and individual Q registers. The available @@ -5899,7 +5902,7 @@ aarch64_print_operand_address (FILE *f, switch (addr.type) { case ADDRESS_REG_IMM: - if (addr.offset == const0_rtx) + if (must_eq (addr.const_offset, 0)) asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]); else asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)],