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[188.29.164.51]) by smtp.gmail.com with ESMTPSA id x185sm606665wmx.35.2017.10.27.06.29.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 06:29:03 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [08/nn] [AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half References: <873764d8y3.fsf@linaro.org> Date: Fri, 27 Oct 2017 14:28:57 +0100 In-Reply-To: <873764d8y3.fsf@linaro.org> (Richard Sandiford's message of "Fri, 27 Oct 2017 14:19:48 +0100") Message-ID: <871slobtye.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch passes the number of units to aarch64_simd_vect_par_cnst_half, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-27 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half): Take the number of units too. * config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise. (aarch64_simd_check_vect_par_cnst_half): Update call accordingly, but check for a vector mode before rather than after the call. * config/aarch64/aarch64-simd.md (aarch64_split_simd_mov) (move_hi_quad_, vec_unpack_hi_) (vec_unpack_lo_mult_lo_) (vec_widen_mult_hi_, vec_unpacks_lo_) (vec_unpacks_hi_, aarch64_saddl2, aarch64_uaddl2) (aarch64_ssubl2, aarch64_usubl2, widen_ssum3) (widen_usum3, aarch64_saddw2, aarch64_uaddw2) (aarch64_ssubw2, aarch64_usubw2, aarch64_sqdmlal2) (aarch64_sqdmlsl2, aarch64_sqdmlal2_lane) (aarch64_sqdmlal2_laneq, aarch64_sqdmlsl2_lane) (aarch64_sqdmlsl2_laneq, aarch64_sqdmlal2_n) (aarch64_sqdmlsl2_n, aarch64_sqdmull2) (aarch64_sqdmull2_lane, aarch64_sqdmull2_laneq) (aarch64_sqdmull2_n): Update accordingly. Reviewed-by: James GReenhalgh Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:04.192082112 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:07.203885483 +0100 @@ -403,7 +403,7 @@ const char *aarch64_output_move_struct ( rtx aarch64_return_addr (int, rtx); rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT); bool aarch64_simd_mem_operand_p (rtx); -rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool); +rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool); rtx aarch64_tls_get_addr (void); tree aarch64_fold_builtin (tree, int, tree *, bool); unsigned aarch64_dbx_register_number (unsigned); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-10-27 14:12:04.193939530 +0100 +++ gcc/config/aarch64/aarch64.c 2017-10-27 14:12:07.205742901 +0100 @@ -12007,12 +12007,12 @@ aarch64_simd_scalar_immediate_valid_for_ Low Mask: { 2, 3 } { 0, 1 } High Mask: { 0, 1 } { 2, 3 } -*/ + + MODE Is the mode of the vector and NUNITS is the number of units in it. */ rtx -aarch64_simd_vect_par_cnst_half (machine_mode mode, bool high) +aarch64_simd_vect_par_cnst_half (machine_mode mode, int nunits, bool high) { - int nunits = GET_MODE_NUNITS (mode); rtvec v = rtvec_alloc (nunits / 2); int high_base = nunits / 2; int low_base = 0; @@ -12041,14 +12041,15 @@ aarch64_simd_vect_par_cnst_half (machine aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode, bool high) { - rtx ideal = aarch64_simd_vect_par_cnst_half (mode, high); + if (!VECTOR_MODE_P (mode)) + return false; + + rtx ideal = aarch64_simd_vect_par_cnst_half (mode, GET_MODE_NUNITS (mode), + high); HOST_WIDE_INT count_op = XVECLEN (op, 0); HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0); int i = 0; - if (!VECTOR_MODE_P (mode)) - return false; - if (count_op != count_ideal) return false; Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:04.193010821 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:07.203885483 +0100 @@ -252,8 +252,8 @@ (define_expand "aarch64_split_simd_movmode, dst); rtx dst_high_part = gen_highpart (mode, dst); - rtx lo = aarch64_simd_vect_par_cnst_half (mode, false); - rtx hi = aarch64_simd_vect_par_cnst_half (mode, true); + rtx lo = aarch64_simd_vect_par_cnst_half (mode, , false); + rtx hi = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_simd_mov_from_low (dst_low_part, src, lo)); @@ -1436,7 +1436,7 @@ (define_expand "move_hi_quad_" (match_operand: 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); if (BYTES_BIG_ENDIAN) emit_insn (gen_aarch64_simd_move_hi_quad_be_ (operands[0], operands[1], p)); @@ -1520,7 +1520,7 @@ (define_expand "vec_unpack_hi_ (ANY_EXTEND: (match_operand:VQW 1 "register_operand"))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_simd_vec_unpack_hi_ (operands[0], operands[1], p)); DONE; @@ -1532,7 +1532,7 @@ (define_expand "vec_unpack_lo_ (ANY_EXTEND: (match_operand:VQW 1 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); emit_insn (gen_aarch64_simd_vec_unpack_lo_ (operands[0], operands[1], p)); DONE; @@ -1652,7 +1652,7 @@ (define_expand "vec_widen_mult_lo_ (match_operand:VQW 2 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); emit_insn (gen_aarch64_simd_vec_mult_lo_ (operands[0], operands[1], operands[2], p)); @@ -1679,7 +1679,7 @@ (define_expand "vec_widen_mult_hi_ (match_operand:VQW 2 "register_operand" ""))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_simd_vec_mult_hi_ (operands[0], operands[1], operands[2], p)); @@ -2083,7 +2083,7 @@ (define_expand "vec_unpacks_lo_" (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], operands[1], p)); DONE; @@ -2106,7 +2106,7 @@ (define_expand "vec_unpacks_hi_" (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], operands[1], p)); DONE; @@ -3027,7 +3027,7 @@ (define_expand "aarch64_saddl2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_saddl_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3039,7 +3039,7 @@ (define_expand "aarch64_uaddl2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_uaddl_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3051,7 +3051,7 @@ (define_expand "aarch64_ssubl2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_ssubl_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3063,7 +3063,7 @@ (define_expand "aarch64_usubl2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_usubl_hi_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3089,7 +3089,7 @@ (define_expand "widen_ssum3" (match_operand: 2 "register_operand" "")))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); rtx temp = gen_reg_rtx (GET_MODE (operands[0])); emit_insn (gen_aarch64_saddw_internal (temp, operands[2], @@ -3117,7 +3117,7 @@ (define_expand "widen_usum3" (match_operand: 2 "register_operand" "")))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); rtx temp = gen_reg_rtx (GET_MODE (operands[0])); emit_insn (gen_aarch64_uaddw_internal (temp, operands[2], @@ -3178,7 +3178,7 @@ (define_expand "aarch64_saddw2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_saddw2_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3190,7 +3190,7 @@ (define_expand "aarch64_uaddw2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_uaddw2_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3203,7 +3203,7 @@ (define_expand "aarch64_ssubw2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_ssubw2_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3215,7 +3215,7 @@ (define_expand "aarch64_usubw2" (match_operand:VQW 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_usubw2_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -3735,7 +3735,7 @@ (define_expand "aarch64_sqdmlal2" (match_operand:VQ_HSI 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlal2_internal (operands[0], operands[1], operands[2], operands[3], p)); DONE; @@ -3748,7 +3748,7 @@ (define_expand "aarch64_sqdmlsl2" (match_operand:VQ_HSI 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlsl2_internal (operands[0], operands[1], operands[2], operands[3], p)); DONE; @@ -3816,7 +3816,7 @@ (define_expand "aarch64_sqdmlal2_lanemode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlal2_lane_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3831,7 +3831,7 @@ (define_expand "aarch64_sqdmlal2_laneqmode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlal2_laneq_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3846,7 +3846,7 @@ (define_expand "aarch64_sqdmlsl2_lanemode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlsl2_lane_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3861,7 +3861,7 @@ (define_expand "aarch64_sqdmlsl2_laneqmode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlsl2_laneq_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3894,7 +3894,7 @@ (define_expand "aarch64_sqdmlal2_n (match_operand: 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlal2_n_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -3908,7 +3908,7 @@ (define_expand "aarch64_sqdmlsl2_n (match_operand: 3 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmlsl2_n_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4062,7 +4062,7 @@ (define_expand "aarch64_sqdmull2" (match_operand:VQ_HSI 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmull2_internal (operands[0], operands[1], operands[2], p)); DONE; @@ -4123,7 +4123,7 @@ (define_expand "aarch64_sqdmull2_lanemode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmull2_lane_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4137,7 +4137,7 @@ (define_expand "aarch64_sqdmull2_laneqmode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmull2_laneq_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -4170,7 +4170,7 @@ (define_expand "aarch64_sqdmull2_n (match_operand: 2 "register_operand" "w")] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); emit_insn (gen_aarch64_sqdmull2_n_internal (operands[0], operands[1], operands[2], p)); DONE;