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[209.132.180.67]) by mx.google.com with ESMTP id d196si5504266pfd.534.2017.10.23.08.22.46; Mon, 23 Oct 2017 08:22:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=Wjm9aChU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932192AbdJWPWp (ORCPT + 6 others); Mon, 23 Oct 2017 11:22:45 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:40056 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932111AbdJWPWo (ORCPT ); Mon, 23 Oct 2017 11:22:44 -0400 Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-10.nifty.com with ESMTP id v9NFLpLC017908; Tue, 24 Oct 2017 00:21:52 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v9NFLpLC017908 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1508772112; bh=4j8xmidnO3Mxr5b27JsI+LyaBt0/SVt/agro38+gSao=; h=From:To:Cc:Subject:Date:From; b=Wjm9aChUuJK4ypsd6FV+wDrMlw9FUkgWBqTJr7Zw1rg97Vw99t1auEnepTsA0l62Z 8souy+/r5PvLJWMaze/QZnwAHYjKIP7FVafJDuUudUP+cvG001h/e1SXVZcDDvktnT xULROfqaWLlK1Mt8QF1XEuQP16XWzlZznh1ZcjNNsMg2PHjN6uUnIBCYCkIOktnl67 8y+KdoqYeEFNbAe9P1hhM33UKuSLqUwefExNye1CFdI9v18mll2sH2cxhHWhb+okdi 4jTYMc5A1+gDdJPU9OcsbAuKmaYrdBuYuuiMfBzHzqqgi7FNpddEMszGt55oqPLoT0 rXLG9DbBLHLsg== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH] arm64: dts: uniphier: add eMMC hardware reset provider node Date: Tue, 24 Oct 2017 00:21:37 +0900 Message-Id: <1508772097-18752-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mmc-pwrseq-emmc node to perform standard eMMC hardware reset procedure. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 8 ++++++++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 7 +++++++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 8 ++++++++ 3 files changed, 23 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 5fde6f5..e8bd39c 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include + /memreserve/ 0x80000000 0x02000000; / { @@ -96,6 +98,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -310,6 +317,7 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index aae64d2..e7e9826 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -7,6 +7,7 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include #include /memreserve/ 0x80000000 0x02000000; @@ -169,6 +170,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -416,6 +422,7 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 7e990e3..6297a2d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include + /memreserve/ 0x80000000 0x02000000; / { @@ -124,6 +126,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -317,6 +324,7 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>;