From patchwork Mon Oct 23 09:58:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116662 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4451780qgn; Mon, 23 Oct 2017 02:59:48 -0700 (PDT) X-Received: by 10.98.20.80 with SMTP id 77mr12749936pfu.307.1508752788524; Mon, 23 Oct 2017 02:59:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508752788; cv=none; d=google.com; s=arc-20160816; b=CeaGhEagKx1Br6KfO4dyXes1D16qD5N7hlQfbPpybeZjhJBLxBe4tq6CWw3WhN+nQO GozsnUvjGkF9KquxzmW7d0hzQL6EnIJzivs0yTi0BpXGlHT0E10pxk2ILHWpjBMbizmV 7WjQXzsnREbp1mmo/jzfeljq+mJQGgd4IHL4SiJsBxWvvpGA5FUeI52Z4ga5LPyoAmbK PMGO5q8FME/47vv/j601tpc2RPl7tMC7XKZsHME4hVc8xQc4Ty47JtX+8+4Oesn3K0Pq aHu94zC6sMWz0yA1fBN46dzZCXEG/TW8PyVX81Y0oJcu87HGh7ddyiXuhxTk/w8SV0d+ h9ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=QHCzf9adhk7AuaHsf/ymE9R7gEgRKGYhfjgDQTNByDw=; b=fXDU+tE6zVY2FEEyvEZwWJxL+CKYN//+qZ0scSCj76mXMKl5uDXhoecV9ohgO3L0WA KvCwZwfi+/4IMhD+UhFH9lD7nSv4V310W6pJOObC7mNDbeWMDoztZFbo6VGCq2sGAhj+ 6+DDBB8jG+jzNF3Gu3a5ntrTfPPwJXsd+z6qO+z+jRz8SoiN4xVxMOayMbKaXcq7CLn9 o+CnBFhogyGCDM1njAex6VFfmaom7hQ8BgLQHr2dSgS//tZN71td5ZP/z5MH1reKkrGw Chwz8N8aJK4w6kUl6dBNZ/u8MqcEVd7yqTTr9BNwlDe3ex271LONgY2L9z2c8dJuoBXM a0Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Spe5xnSV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b89si5088218pfd.354.2017.10.23.02.59.48; Mon, 23 Oct 2017 02:59:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Spe5xnSV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751395AbdJWJ7o (ORCPT + 27 others); Mon, 23 Oct 2017 05:59:44 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:49714 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751282AbdJWJ7l (ORCPT ); Mon, 23 Oct 2017 05:59:41 -0400 Received: by mail-wr0-f193.google.com with SMTP id g90so16698211wrd.6 for ; Mon, 23 Oct 2017 02:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QHCzf9adhk7AuaHsf/ymE9R7gEgRKGYhfjgDQTNByDw=; b=Spe5xnSVx5J8gZHYBcNuX2jLD7iGW82jEritK9AGXdBViY+onTc8Z1AViicy17VgV6 sgowJRiSi/rs2+vffHLi/g6f6LqwRuYgUJODXTm1g1uUtkrPUFuqW4fxtH/EwwtH11ZZ xSo2XwQ1swQiqAgxqmB0ppqUvUkhaKTb2bgR0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QHCzf9adhk7AuaHsf/ymE9R7gEgRKGYhfjgDQTNByDw=; b=QqZ0zdJYaEJ1z5O2GK60bSELlTDit87lI5V0i+tikx7qD/N8J8qAC+uZwQAu86NgfQ sNAObYmlLfnMpfW2jyafIGHlu7sA9bA+m/z3Rc61E+/RhNqReplLQmveqAE1ATecryWx E6NfjoImYb1TD9f5MSiGKzit3spLc8za/l+DFvPTGguZ4SwphPz6J5Ys+ckQSzOrGaak lkptINqy0bsrLLa8SCkmofGSj1D6gJAsE4jXTY8rPsj0evoz7/h5qfy4cNep95AjlKYt 0UrDNJOHtoQccTWElLR3zoV0WdYDmlxUTxTzhREvMnumf78oufVi43N0AIhiHiiMQrQt Ytmw== X-Gm-Message-State: AMCzsaUipW+5DRrB6rvqo+uPDhszZn3nKqYy8IHrHeclAelHE2PGQjZP +62GxaxvXBJXaudbiYdzU5chWw== X-Google-Smtp-Source: ABhQp+TyWNoviOcw78krslydlsrmvfoEinvkgGNrFaJI4EyMi2y32jwRYKv964w7r7QhzyEunh6fCg== X-Received: by 10.223.201.8 with SMTP id m8mr2761741wrh.260.1508752780114; Mon, 23 Oct 2017 02:59:40 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.33]) by smtp.gmail.com with ESMTPSA id q188sm3626900wmb.43.2017.10.23.02.59.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 02:59:39 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v7 1/6] timer: add timer_of_exit function Date: Mon, 23 Oct 2017 11:58:37 +0200 Message-Id: <1508752722-4489-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add this exit function to be able to undo what have been done in timer_of_init(). Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-of.c | 12 ++++++++++++ drivers/clocksource/timer-of.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index c79122d..7c64a5c1 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -176,3 +176,15 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) timer_base_exit(&to->of_base); return ret; } + +void timer_of_exit(struct timer_of *to) +{ + if (to->flags & TIMER_OF_IRQ) + timer_irq_exit(&to->of_irq); + + if (to->flags & TIMER_OF_CLOCK) + timer_clk_exit(&to->of_clk); + + if (to->flags & TIMER_OF_BASE) + timer_base_exit(&to->of_base); +} diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index e0d7272..44f57e0 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -66,4 +66,7 @@ static inline unsigned long timer_of_period(struct timer_of *to) extern int __init timer_of_init(struct device_node *np, struct timer_of *to); + +extern void timer_of_exit(struct timer_of *to); + #endif From patchwork Mon Oct 23 09:58:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116667 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4452885qgn; Mon, 23 Oct 2017 03:00:51 -0700 (PDT) X-Received: by 10.98.63.213 with SMTP id z82mr12370656pfj.10.1508752851262; Mon, 23 Oct 2017 03:00:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508752851; cv=none; d=google.com; s=arc-20160816; b=qWMtj/XfDQKXdDqnlLdQL7ubsAAPG17rsVNydOUCJd3rg4H/MeDJww2+2i4Y4ghIQO aRND83cndQ2Gw+VL+3am1pcWE9+4GXF8GLDtWPBwHDRfjFqR18IersE1DZScWkGVvhwb 3EHt1FaPW1zRX77uDNpBMLI7OFOt8Tf9AuEzhe6YU+kMEmDnyoqFuAdLY+i2ALWCin38 PIyiWqJ170whjp97h8KZBLnrhEuIxs70JzcTY6Z9qSLgsarQcYG8Ux2XaR3RZxgSrdok OvbvkL0Nxs8qVPWEVvww8BRwBLRYy5nFHMkeSYmBjrR6mcSZUy+cTwSRdRySVlbxsiZR /Vgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=duOElaXLqNI7zUhXo1IO74aUmnDuHfjMUfMf3xNAWNQ=; b=MI4+JCQ4ujqhFfIYcJzbKwZwpRFSYtADCaOochPA9FrTMKs9Pg8p4E/ycLsgf3WU+j WK0yflLFHbPuL0kJFAf+GMLFuA0PuwWxuuOqXKJctWtQIGf2J1Ff+pD6Pf5ocxSeLNYf oYxxkseY6QBxZme2+Ub038pgLtv77aZfriFApsFOn0I/FRdWL5Uur9ViFQgpLsB8cXF2 LvahhfT0PBTuMlAX8Xf9RlUIRgx3Roklw1ngc1U7FfDLeGVbDLEYpdukxj7sfOyqmFzP TQc56YMwjRzz1hvNISCh/74vJ6BkhMUKfJpvDJc1dTfMyOfeMGtILN7vp4io0iwO5hoh 4zDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ejTDiLmK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This allow to remove custom proprietary structure. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 160 ++++++++++++++------------------------ 2 files changed, 58 insertions(+), 103 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cc60620..755c0cc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -289,6 +289,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..fc61fd1 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -17,6 +17,8 @@ #include #include +#include "timer-of.h" + #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 @@ -34,117 +36,84 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, base + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static int __init stm32_clockevent_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); + unsigned long max_delta; + int ret, bits, prescaler = 1; + struct timer_of *to; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; + to->clkevt.rating = 200; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; + + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; bits = 32; @@ -152,38 +121,23 @@ static int __init stm32_clockevent_init(struct device_node *np) prescaler = 1024; bits = 16; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_period(to), 0x1, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + node, bits); - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: +err: + kfree(to); return ret; } From patchwork Mon Oct 23 09:58:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116666 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4452498qgn; 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Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 115 ++++++++++++++++++++++++++++---------- 1 file changed, 87 insertions(+), 28 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index d8e5636..b00987f 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -42,28 +44,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if (next - now > evt) + return -ETIME; + + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -75,12 +93,57 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), MIN_DELTA, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long max_arr; @@ -92,12 +155,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -122,16 +186,11 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), - MIN_DELTA, ~0U); + stm32_clockevent_init(to); return 0; @@ -143,4 +202,4 @@ static int __init stm32_clockevent_init(struct device_node *node) return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Mon Oct 23 09:58:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116665 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4452087qgn; Mon, 23 Oct 2017 03:00:09 -0700 (PDT) X-Received: by 10.99.175.26 with SMTP id w26mr11674387pge.11.1508752809654; Mon, 23 Oct 2017 03:00:09 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id u9si4696074pgc.615.2017.10.23.03.00.09; Mon, 23 Oct 2017 03:00:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CKiDK5m1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751552AbdJWKAG (ORCPT + 27 others); Mon, 23 Oct 2017 06:00:06 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:45386 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751424AbdJWJ7u (ORCPT ); Mon, 23 Oct 2017 05:59:50 -0400 Received: by mail-wm0-f67.google.com with SMTP id q124so8381319wmb.0 for ; Mon, 23 Oct 2017 02:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=CKiDK5m18CIZ+ejijzMHf6wrf/jF3Kii4CSkHLvXrPiVxjZ2FmJcmKD9WSkwEhahjV /4d223PBhCPhCVBk21Q7OCy+uuo1eRJjWjdjKUDd9L511dBgeNd8V3OKYNNtKudUbBj9 TkyjWuaxQuzzJPp8EcML6fOg13xkP5fBaoHO0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=ditTdU42r32zeIk7v9N66w7/LfDikwUHDUrCZWOalsAd62YKdScd66QtPoMveG1dcw xPsU19kMrK9+rQbqRTUsNuwJ/nX0gZZilMRHKcQqQApESFYiJYkFWSZyPlXcIVcrKkaS rGF5wrZML/gIBeYmn0+MTCJ2aXlguoe4wYxSBBTyEuNF5LQHqPPZOFdBpkahr6dmVqNz xV3Wsjve+zkxd/bfb/niF0OPuKqQcGPwuDnpV5nJIBuL/ZX3gCtcRmdUlQauAPjPfdNP xSw26eVIvyBbMMG0qUiBXkIHG1Okvg+Tfy41K5xsvc7Y+AZpBGHcWDCllmgrYQlvU1gP m8ow== X-Gm-Message-State: AMCzsaXtZK/hEpu12PZagYxQgLmCfK9OGkShgil3fHFyQQ3d5cWO+0f4 KciXKmgmOS/xLTepwqomp7O+hQ== X-Google-Smtp-Source: ABhQp+RBVUkMqnH0s8uCx3a2hD8WmSP7I2qP26XEFvosVQWWnLY/LZUXmS6OlzQA/63vmyEtYq3ivg== X-Received: by 10.28.55.71 with SMTP id e68mr5126319wma.139.1508752789593; Mon, 23 Oct 2017 02:59:49 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.33]) by smtp.gmail.com with ESMTPSA id q188sm3626900wmb.43.2017.10.23.02.59.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 02:59:49 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v7 6/6] arm: dts: stm32: remove useless clocksource nodes Date: Mon, 23 Oct 2017 11:58:42 +0200 Message-Id: <1508752722-4489-7-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index dd7e99b..ac9a3e6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5633860..a9077e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;