From patchwork Wed Sep 23 10:08:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 258053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17718C2D0A8 for ; Wed, 23 Sep 2020 10:08:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDBD82145D for ; Wed, 23 Sep 2020 10:08:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="O6iUG/KN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726659AbgIWKIw (ORCPT ); Wed, 23 Sep 2020 06:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726338AbgIWKIv (ORCPT ); Wed, 23 Sep 2020 06:08:51 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79D0CC0613CE for ; Wed, 23 Sep 2020 03:08:51 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id y2so21401496lfy.10 for ; Wed, 23 Sep 2020 03:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=3Ll9U6XrekbR5N3wlwKdoF0YKO9JdUUYPqiXJDeJs4c=; b=O6iUG/KN2HvKkUXkbGE3fNwU8S3Rt/ohW6Eyp0wCBl8tY4Q6vMkRKgX8EfgmId2kCk tubtFIHXJz9ELsf4Te9Mo+1zHQp+Afx45nyhGoSKThC22xgpifvXKw99W8pEwhqNDf9c IqY1OeS5KojgrZonBO4eXIdMiDSgWEEqgOBQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=3Ll9U6XrekbR5N3wlwKdoF0YKO9JdUUYPqiXJDeJs4c=; b=n6ajx/QEtqHSXNEPWnjSyq0ODz9Hzd4K32TqLLADS9d7w9wM12Nw0GAb2KY9jd0ptA YXw+SqSljAZoqOQCQil01ZqTju52L9SruDSlqgmhocJxQ/zBlKOoEuKmoFg5oSeM/LFA JDojY2MH03W0QQN4YKsPXzHSY0gR8F/J+qDYlk0/iYYL9jEXK6ea4FJZdjh1gj1spatF 8jvMs5exSJxo5ld3pfQuiv5BRFIKqg1L8yC2VZLR4PtLGx88PWq0Zy0KyRgGi9VimjOb pOTWi9W0AJL8uJtFVab6SBRD8WOCCZMGgrTzoJvtdEVVHDmgawVxXW1ZQyjSu6GlUmyb Vu9w== X-Gm-Message-State: AOAM5316xhZ9YlYSwnBu6RH9wxDD+gYeFMhkO+JQkDFgkfreGaPVQ+2D 3HklTKKhgwo5gayCPEWpTIKQdw== X-Google-Smtp-Source: ABdhPJykDnr4AHhFLrBFZZTYH/AlZyw2KDRT9Q4hNGss2vPY67UUrpL5j/7cloUMalVS83MiVnQSnA== X-Received: by 2002:a05:6512:1090:: with SMTP id j16mr2867180lfg.3.1600855729829; Wed, 23 Sep 2020 03:08:49 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id b13sm4569584lfa.92.2020.09.23.03.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 03:08:49 -0700 (PDT) Date: Wed, 23 Sep 2020 12:08:43 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v11 1/5] dt-bindings: vendor: add vendor prefix for LiteX Message-ID: <20200923120817.1667149-1-mholenko@antmicro.com> References: <20200923120817.1667149-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200923120817.1667149-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski Add vendor prefix for LiteX SoC builder. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Acked-by: Rob Herring --- Notes: No changes in v11. No changes in v10. No changes in v9. No changes in v8. No changes in v7. No changes in v6. No changes in v5. No changes in v4. Changes in v3: - added Acked-by tag No changes in v2. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d3891386d671..9aae6c56d7a3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -571,6 +571,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^litex,.*": + description: LiteX SoC builder "^lltc,.*": description: Linear Technology Corporation "^logicpd,.*": From patchwork Wed Sep 23 10:08:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 296996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B5F0C4727E for ; Wed, 23 Sep 2020 10:09:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13011214D8 for ; Wed, 23 Sep 2020 10:09:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="tcJZLeee" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726670AbgIWKJD (ORCPT ); Wed, 23 Sep 2020 06:09:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726516AbgIWKJC (ORCPT ); Wed, 23 Sep 2020 06:09:02 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 670DFC0613D1 for ; Wed, 23 Sep 2020 03:09:02 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id d15so21419602lfq.11 for ; Wed, 23 Sep 2020 03:09:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=YV40cowgKYQsE/dctRxya7aokqQdDkJKMCXMJgCmuao=; b=tcJZLeeeBUEIzP12lEZlavx1cQUBugRhU4Hscm5qYVLJQx4qN5STqy30aeU3P2Ik55 SDaTmWjEVACymaxvWtYkQqssJBrJsxXX+QyT75USkSI1NRspEU4uxss+5//ii1bUhf8p RbdvFS3qrXrxFZJ8VbWcajRb3LDuhedxn0lw0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=YV40cowgKYQsE/dctRxya7aokqQdDkJKMCXMJgCmuao=; b=EJM1cGql4KJ5qnpQEx+a7z8YXNEdy12Uh/6s7W4IGalXfJ0+ALXdAgykHpNt98OA7w xBwAyMF0rqDNPSpcaUdzF9yQSKMfwT6uMYLxh/VGALueWa+FuKwiAEXmjr88MKE+p5L7 Dsg6CzOMhpKe+vbvXHKsyM3p4yz5MqLQa8KMXRflGNaG3X86LrCiHuy7XDsw9qyX0g0g 6N4MH5RwC2IvT9j7lDG9o5DKqFgEqqsYFd9ehXnr37pCq2Vha3uiOHnlQ2bIcx6MthfO tBVcSzC8zb7sRwmc5Ek8kXNDQYtrYExbK8EpbFNbpx63h/7NQ+qfi7qirsoeUBz4i1Mz hmjg== X-Gm-Message-State: AOAM530eJ9ySOGHZwSg0D+Xel8Dslje/rJSQ9NfGIon+oKqAhdEYm46v WFP8bLe6hW3a0PgP7KT7dBjzzA== X-Google-Smtp-Source: ABdhPJx4idkoyyn/iWQCyKkfv5WqoeS2/VAjvcTDmHzCKhiWxMKpNArRpHPADC1fwIvxQC52GO3tfg== X-Received: by 2002:a19:a41a:: with SMTP id q26mr2954392lfc.121.1600855740817; Wed, 23 Sep 2020 03:09:00 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id y6sm4535624lfh.106.2020.09.23.03.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 03:09:00 -0700 (PDT) Date: Wed, 23 Sep 2020 12:08:54 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v11 2/5] dt-bindings: soc: document LiteX SoC Controller bindings Message-ID: <20200923120817.1667149-2-mholenko@antmicro.com> References: <20200923120817.1667149-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200923120817.1667149-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pawel Czarnecki Add documentation for LiteX SoC Controller bindings. Signed-off-by: Pawel Czarnecki Signed-off-by: Mateusz Holenko Reviewed-by: Rob Herring --- Notes: No changes in v11. No changes in v10. Changes in v9: - fixed the `reg` node notation in the DT example No changes in v8. No changes in v7. Changes in v6: - fixed license header Changes in v5: - added reviewed-by tag Changes in v4: - changes compatible to "litex,soc-controller" - fixed yaml's header - removed unnecessary sections from yaml - fixed indentation in yaml This commit has been introduced in v3 of the patchset. .../soc/litex/litex,soc-controller.yaml | 39 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml b/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml new file mode 100644 index 000000000000..53121c1fbe4d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2020 Antmicro +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: LiteX SoC Controller driver + +description: | + This is the SoC Controller driver for the LiteX SoC Builder. + It's purpose is to verify LiteX CSR (Control&Status Register) access + operations and provide function for other drivers to read/write CSRs + and to check if those accessors are ready to use. + +maintainers: + - Karol Gugala + - Mateusz Holenko + +properties: + compatible: + const: litex,soc-controller + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + soc_ctrl0: soc-controller@f0000000 { + compatible = "litex,soc-controller"; + reg = <0xf0000000 0xC>; + status = "okay"; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7b58ca29cc80..39be98db7418 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9835,6 +9835,12 @@ L: kunit-dev@googlegroups.com S: Maintained F: lib/list-test.c +LITEX PLATFORM +M: Karol Gugala +M: Mateusz Holenko +S: Maintained +F: Documentation/devicetree/bindings/*/litex,*.yaml + LIVE PATCHING M: Josh Poimboeuf M: Jiri Kosina From patchwork Wed Sep 23 10:09:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 258052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 573C5C2D0A8 for ; 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[77.65.79.196]) by smtp.gmail.com with ESMTPSA id p4sm4624500lfr.68.2020.09.23.03.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 03:09:11 -0700 (PDT) Date: Wed, 23 Sep 2020 12:09:06 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v11 3/5] drivers/soc/litex: add LiteX SoC Controller driver Message-ID: <20200923120817.1667149-3-mholenko@antmicro.com> References: <20200923120817.1667149-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200923120817.1667149-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pawel Czarnecki This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder. Co-developed-by: Mateusz Holenko Signed-off-by: Mateusz Holenko Signed-off-by: Pawel Czarnecki --- Notes: Changes in v11: - removed an unnecessary comment left over from previous version - changed a multi-line comment to comply with the formatting rules - use WARN instad of BUG on a failed CSR validation Changes in v10: - added casting to avoid sparse warnings in the SoC Controller's driver Changes in v9: - added exporting of the `litex_set_reg`/`litex_get_reg` symbols Changes in v8: - removed `litex_check_accessors()` helper function - added crashing (BUG) on the failed LiteX CSR access test No changes in v7. Changes in v6: - added dependency on OF || COMPILE_TEST - used le32_to_cpu(readl(addr)) instead of __raw_readl and writel(cpu_to_le32(value), addr) instead of __raw_writel to take advantage of memory barriers provided by readl/writel Changes in v5: - removed helper accessors and used __raw_readl/__raw_writel instead - fixed checking for errors in litex_soc_ctrl_probe Changes in v4: - fixed indent in Kconfig's help section - fixed copyright header - changed compatible to "litex,soc-controller" - simplified litex_soc_ctrl_probe - removed unnecessary litex_soc_ctrl_remove This commit has been introduced in v3 of the patchset. It includes a simplified version of common 'litex.h' header introduced in v2 of the patchset. MAINTAINERS | 2 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/litex/Kconfig | 15 +++ drivers/soc/litex/Makefile | 3 + drivers/soc/litex/litex_soc_ctrl.c | 194 +++++++++++++++++++++++++++++ include/linux/litex.h | 24 ++++ 7 files changed, 240 insertions(+) create mode 100644 drivers/soc/litex/Kconfig create mode 100644 drivers/soc/litex/Makefile create mode 100644 drivers/soc/litex/litex_soc_ctrl.c create mode 100644 include/linux/litex.h diff --git a/MAINTAINERS b/MAINTAINERS index 39be98db7418..4d70a1b22a87 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9840,6 +9840,8 @@ M: Karol Gugala M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml +F: drivers/soc/litex/litex_soc_ctrl.c +F: include/linux/litex.h LIVE PATCHING M: Josh Poimboeuf diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..d097d070f579 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..0b16108823ef 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/litex/Kconfig b/drivers/soc/litex/Kconfig new file mode 100644 index 000000000000..c974ec3846bc --- /dev/null +++ b/drivers/soc/litex/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License_Identifier: GPL-2.0 + +menu "Enable LiteX SoC Builder specific drivers" + +config LITEX_SOC_CONTROLLER + tristate "Enable LiteX SoC Controller driver" + depends on OF || COMPILE_TEST + help + This option enables the SoC Controller Driver which verifies + LiteX CSR access and provides common litex_get_reg/litex_set_reg + accessors. + All drivers that use functions from litex.h must depend on + LITEX_SOC_CONTROLLER. + +endmenu diff --git a/drivers/soc/litex/Makefile b/drivers/soc/litex/Makefile new file mode 100644 index 000000000000..98ff7325b1c0 --- /dev/null +++ b/drivers/soc/litex/Makefile @@ -0,0 +1,3 @@ +# SPDX-License_Identifier: GPL-2.0 + +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex_soc_ctrl.o diff --git a/drivers/soc/litex/litex_soc_ctrl.c b/drivers/soc/litex/litex_soc_ctrl.c new file mode 100644 index 000000000000..08330c9872b0 --- /dev/null +++ b/drivers/soc/litex/litex_soc_ctrl.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteX SoC Controller Driver + * + * Copyright (C) 2020 Antmicro + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The parameters below are true for LiteX SoC + * configured for 8-bit CSR Bus, 32-bit aligned. + * + * Supporting other configurations will require + * extending the logic in this header. + */ +#define LITEX_REG_SIZE 0x4 +#define LITEX_SUBREG_SIZE 0x1 +#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8) + +static DEFINE_SPINLOCK(csr_lock); + +/* + * LiteX SoC Generator, depending on the configuration, + * can split a single logical CSR (Control & Status Register) + * into a series of consecutive physical registers. + * + * For example, in the configuration with 8-bit CSR Bus, + * 32-bit aligned (the default one for 32-bit CPUs) a 32-bit + * logical CSR will be generated as four 32-bit physical registers, + * each one containing one byte of meaningful data. + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + * + * The purpose of `litex_set_reg`/`litex_get_reg` is to implement + * the logic of writing to/reading from the LiteX CSR in a single + * place that can be then reused by all LiteX drivers. + */ +void litex_set_reg(void __iomem *reg, unsigned long reg_size, + unsigned long val) +{ + unsigned long shifted_data, shift, i; + unsigned long flags; + + spin_lock_irqsave(&csr_lock, flags); + + for (i = 0; i < reg_size; ++i) { + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + shifted_data = val >> shift; + + writel((u32 __force)cpu_to_le32(shifted_data), reg + (LITEX_REG_SIZE * i)); + } + + spin_unlock_irqrestore(&csr_lock, flags); +} +EXPORT_SYMBOL_GPL(litex_set_reg); + +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size) +{ + unsigned long shifted_data, shift, i; + unsigned long result = 0; + unsigned long flags; + + spin_lock_irqsave(&csr_lock, flags); + + for (i = 0; i < reg_size; ++i) { + shifted_data = le32_to_cpu((__le32 __force)readl(reg + (LITEX_REG_SIZE * i))); + + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + result |= (shifted_data << shift); + } + + spin_unlock_irqrestore(&csr_lock, flags); + + return result; +} +EXPORT_SYMBOL_GPL(litex_get_reg); + +#define SCRATCH_REG_OFF 0x04 +#define SCRATCH_REG_SIZE 4 +#define SCRATCH_REG_VALUE 0x12345678 +#define SCRATCH_TEST_VALUE 0xdeadbeef + +/* + * Check LiteX CSR read/write access + * + * This function reads and writes a scratch register in order + * to verify if CSR access works. + * + * In case any problems are detected, the driver should panic. + * + * Access to the LiteX CSR is, by design, done in CPU native + * endianness. The driver should not dynamically configure + * access functions when the endianness mismatch is detected. + * Such situation indicates problems in the soft SoC design + * and should be solved at the LiteX generator level, + * not in the software. + */ +static int litex_check_csr_access(void __iomem *reg_addr) +{ + unsigned long reg; + + reg = litex_get_reg(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_SIZE); + + if (reg != SCRATCH_REG_VALUE) { + panic("Scratch register read error! Expected: 0x%x but got: 0x%lx", + SCRATCH_REG_VALUE, reg); + return -EINVAL; + } + + litex_set_reg(reg_addr + SCRATCH_REG_OFF, + SCRATCH_REG_SIZE, SCRATCH_TEST_VALUE); + reg = litex_get_reg(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_SIZE); + + if (reg != SCRATCH_TEST_VALUE) { + panic("Scratch register write error! Expected: 0x%x but got: 0x%lx", + SCRATCH_TEST_VALUE, reg); + return -EINVAL; + } + + /* restore original value of the SCRATCH register */ + litex_set_reg(reg_addr + SCRATCH_REG_OFF, + SCRATCH_REG_SIZE, SCRATCH_REG_VALUE); + + pr_info("LiteX SoC Controller driver initialized"); + + return 0; +} + +struct litex_soc_ctrl_device { + void __iomem *base; +}; + +static const struct of_device_id litex_soc_ctrl_of_match[] = { + {.compatible = "litex,soc-controller"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match); + +static int litex_soc_ctrl_probe(struct platform_device *pdev) +{ + int result; + struct device *dev; + struct device_node *node; + struct litex_soc_ctrl_device *soc_ctrl_dev; + + dev = &pdev->dev; + node = dev->of_node; + if (!node) + return -ENODEV; + + soc_ctrl_dev = devm_kzalloc(dev, sizeof(*soc_ctrl_dev), GFP_KERNEL); + if (!soc_ctrl_dev) + return -ENOMEM; + + soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(soc_ctrl_dev->base)) + return PTR_ERR(soc_ctrl_dev->base); + + result = litex_check_csr_access(soc_ctrl_dev->base); + if (result) { + /* LiteX CSRs access is broken which means that + * none of LiteX drivers will most probably + * operate correctly + */ + WARN(1, "Failed to validate CSR registers, the system is probably broken.\n"); + } + + return result; +} + +static struct platform_driver litex_soc_ctrl_driver = { + .driver = { + .name = "litex-soc-controller", + .of_match_table = of_match_ptr(litex_soc_ctrl_of_match) + }, + .probe = litex_soc_ctrl_probe, +}; + +module_platform_driver(litex_soc_ctrl_driver); +MODULE_DESCRIPTION("LiteX SoC Controller driver"); +MODULE_AUTHOR("Antmicro "); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..72061018c172 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Implementation of the functions is provided by + * the LiteX SoC Controller driver. + * + * Copyright (C) 2019-2020 Antmicro + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include +#include +#include + +void litex_set_reg(void __iomem *reg, unsigned long reg_sz, unsigned long val); + +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_sz); + + +#endif /* _LINUX_LITEX_H */ From patchwork Wed Sep 23 10:09:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 296995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3347C2D0A8 for ; Wed, 23 Sep 2020 10:09:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F9EC2145D for ; Wed, 23 Sep 2020 10:09:29 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[77.65.79.196]) by smtp.gmail.com with ESMTPSA id m22sm4940941lji.36.2020.09.23.03.09.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 03:09:22 -0700 (PDT) Date: Wed, 23 Sep 2020 12:09:17 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v11 4/5] dt-bindings: serial: document LiteUART bindings Message-ID: <20200923120817.1667149-4-mholenko@antmicro.com> References: <20200923120817.1667149-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200923120817.1667149-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski Add documentation for LiteUART devicetree bindings. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Reviewed-by: Rob Herring --- Notes: No changes in v11. No changes in v10. No changes in v9. No changes in v8. No changes in v7. Changes in v6: - fixed license header No changes in v5. No changes in v4. Changes in v3: - added Reviewed-by tag - patch number changed from 3 to 4 - removed changes in MAINTAINERS file (moved to patch #2) Changes in v2: - binding description rewritten to a yaml schema file - added interrupt line - fixed unit address - patch number changed from 2 to 3 .../bindings/serial/litex,liteuart.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/litex,liteuart.yaml diff --git a/Documentation/devicetree/bindings/serial/litex,liteuart.yaml b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml new file mode 100644 index 000000000000..69acb222bb57 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LiteUART serial controller + +maintainers: + - Karol Gugala + - Mateusz Holenko + +description: | + LiteUART serial controller is a part of LiteX FPGA SoC builder. It supports + multiple CPU architectures, currently including e.g. OpenRISC and RISC-V. + +properties: + compatible: + const: litex,liteuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + uart0: serial@e0001800 { + compatible = "litex,liteuart"; + reg = <0xe0001800 0x100>; + interrupts = <2>; + }; From patchwork Wed Sep 23 10:09:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 258051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E584DC2D0A8 for ; Wed, 23 Sep 2020 10:09:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A221E21BE5 for ; Wed, 23 Sep 2020 10:09:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="VPyO/dwu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726738AbgIWKJh (ORCPT ); Wed, 23 Sep 2020 06:09:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726475AbgIWKJg (ORCPT ); Wed, 23 Sep 2020 06:09:36 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 740E0C0613CE for ; Wed, 23 Sep 2020 03:09:36 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id q8so21413097lfb.6 for ; Wed, 23 Sep 2020 03:09:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=2MLAtHkIwXoMDAnNHI0//3bw0H44xAw4S18EfXPbxd8=; b=VPyO/dwughB+oev9ZHKv2Hnv9QVNdaNb/Vhri1u0elWeRSYuLNPuM+vv/KI1GTWboQ 3cgjyS8uadk7qDRizXmCFl/PDnG+orxmJmFm2I0KWQ6pJDkAqzOYVS85uCBpp5iD1P4C qitdC+TikJw8C2+y8d3SULco4GshPH1NPQBy4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=2MLAtHkIwXoMDAnNHI0//3bw0H44xAw4S18EfXPbxd8=; b=bD1d2KyqsZrNEjCNqQ6ta75XIYm6zAns6wFf4mp2bE2A1wbyhWlUi7tROFQLHNT3/s zk3Q4NaNt6xWKr3F+hql3vqPcPbpTlT9s6gkMicPE4gugM8QAswVxSzpGplaiPyRN5er 0nfVPyjxUiz+W0/5SJqvIkW/bEZQTp3z8nlvMJzGKXJKZp2AH2Aq9rh8k5Cfw1hzfr5a +zgHFVWAMlfva1a8VCWgTf+ajQO+bO6EHSr4iQQXJFfCc8TubGD1h2erjKgsd2vi/eee CYu43QzqVfdP7GTc5sefOH3xkcYmvwE9NgPf/jm+wCtcdZ9A9esJ4FWKq8eZgu7axTYB cQ0Q== X-Gm-Message-State: AOAM533tNH+laOyHAAtPtX3ta26kuCp0Q4bLqbd4hzM0CpzTCjlOsaFT u75rR7qMEdyQoaEM9X21Y6EZcA== X-Google-Smtp-Source: ABdhPJyNfmQEoZAXDIY8NTN/JLJFgZnSQ7OMLUKwjiEEVhbCGqbL3RhHiaEIN8rzPFycHLkQlzrmpg== X-Received: by 2002:ac2:50cd:: with SMTP id h13mr3097475lfm.437.1600855774790; Wed, 23 Sep 2020 03:09:34 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id e8sm1396050ljk.25.2020.09.23.03.09.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 03:09:33 -0700 (PDT) Date: Wed, 23 Sep 2020 12:09:28 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v11 5/5] drivers/tty/serial: add LiteUART driver Message-ID: <20200923120817.1667149-5-mholenko@antmicro.com> References: <20200923120817.1667149-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200923120817.1667149-0-mholenko@antmicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski This commit adds driver for the FPGA-based LiteUART serial controller from LiteX SoC builder. The current implementation supports LiteUART configured for 32 bit data width and 8 bit CSR bus width. It does not support IRQ. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Reviewed-by: Greg Kroah-Hartman --- Notes: Changes in v11: - added Reviewed-by tag No changes in v10. No changes in v9. Changes in v8: - fixed help messages in LiteUART's KConfig - removed dependency between LiteUART and LiteX SoC drivers Changed in v7: - added missing include directive Changes in v6: - LiteUART ports now stored in xArray - removed PORT_LITEUART - fixed formatting - removed some unnecessary defines No changes in v5. Changes in v4: - fixed copyright header - removed a wrong dependency on UARTLITE from Kconfig - added a dependency on LITEX_SOC_CONTROLLER to LITEUART in Kconfig Changes in v3: - aliases made optional - used litex_get_reg/litex_set_reg functions instead of macros - SERIAL_LITEUART_NR_PORTS renamed to SERIAL_LITEUART_MAX_PORTS - PORT_LITEUART changed from 122 to 123 - added dependency on LITEX_SOC_CONTROLLER - patch number changed from 4 to 5 No changes in v2. MAINTAINERS | 1 + drivers/tty/serial/Kconfig | 32 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/liteuart.c | 402 ++++++++++++++++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 drivers/tty/serial/liteuart.c diff --git a/MAINTAINERS b/MAINTAINERS index 4d70a1b22a87..1387cefc63ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9841,6 +9841,7 @@ M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml F: drivers/soc/litex/litex_soc_ctrl.c +F: drivers/tty/serial/liteuart.c F: include/linux/litex.h LIVE PATCHING diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index adf9e80e7dc9..17aaf0afb27a 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1562,6 +1562,38 @@ config SERIAL_MILBEAUT_USIO_CONSOLE receives all kernel messages and warnings and which allows logins in single user mode). +config SERIAL_LITEUART + tristate "LiteUART serial port support" + depends on HAS_IOMEM + depends on OF || COMPILE_TEST + depends on LITEX_SOC_CONTROLLER + select SERIAL_CORE + help + This driver is for the FPGA-based LiteUART serial controller from LiteX + SoC builder. + + Say 'Y' or 'M' here if you wish to use the LiteUART serial controller. + Otherwise, say 'N'. + +config SERIAL_LITEUART_MAX_PORTS + int "Maximum number of LiteUART ports" + depends on SERIAL_LITEUART + default "1" + help + Set this to the maximum number of serial ports you want the driver + to support. + +config SERIAL_LITEUART_CONSOLE + bool "LiteUART serial port console support" + depends on SERIAL_LITEUART=y + select SERIAL_CORE_CONSOLE + help + Say 'Y' or 'M' here if you wish to use the FPGA-based LiteUART serial + controller from LiteX SoC builder as the system console + (the system console is the device which receives all kernel messages + and warnings and which allows logins in single user mode). + Otherwise, say 'N'. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index d056ee6cca33..9f8ba419ff3b 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o +obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/liteuart.c b/drivers/tty/serial/liteuart.c new file mode 100644 index 000000000000..b087e6a32106 --- /dev/null +++ b/drivers/tty/serial/liteuart.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteUART serial controller (LiteX) Driver + * + * Copyright (C) 2019-2020 Antmicro + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * CSRs definitions (base address offsets + width) + * + * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus, + * 32-bit aligned. + * + * Supporting other configurations might require new definitions or a more + * generic way of indexing the LiteX CSRs. + * + * For more details on how CSRs are defined and handled in LiteX, see comments + * in the LiteX SoC Driver: drivers/soc/litex/litex_soc_ctrl.c + */ +#define OFF_RXTX 0x00 +#define OFF_TXFULL 0x04 +#define OFF_RXEMPTY 0x08 +#define OFF_EV_STATUS 0x0c +#define OFF_EV_PENDING 0x10 +#define OFF_EV_ENABLE 0x14 + +/* events */ +#define EV_TX 0x1 +#define EV_RX 0x2 + +struct liteuart_port { + struct uart_port port; + struct timer_list timer; +}; + +#define to_liteuart_port(port) container_of(port, struct liteuart_port, port) + +static DEFINE_XARRAY_FLAGS(liteuart_array, XA_FLAGS_ALLOC); + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE +static struct console liteuart_console; +#endif + +static struct uart_driver liteuart_driver = { + .owner = THIS_MODULE, + .driver_name = "liteuart", + .dev_name = "ttyLXU", + .major = 0, + .minor = 0, + .nr = CONFIG_SERIAL_LITEUART_MAX_PORTS, +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + .cons = &liteuart_console, +#endif +}; + +static void liteuart_timer(struct timer_list *t) +{ + struct liteuart_port *uart = from_timer(uart, t, timer); + struct uart_port *port = &uart->port; + unsigned char __iomem *membase = port->membase; + unsigned int flg = TTY_NORMAL; + int ch; + unsigned long status; + + while ((status = !litex_get_reg(membase + OFF_RXEMPTY, 1)) == 1) { + ch = litex_get_reg(membase + OFF_RXTX, 1); + port->icount.rx++; + + /* necessary for RXEMPTY to refresh its value */ + litex_set_reg(membase + OFF_EV_PENDING, 1, EV_TX | EV_RX); + + /* no overflow bits in status */ + if (!(uart_handle_sysrq_char(port, ch))) + uart_insert_char(port, status, 0, ch, flg); + + tty_flip_buffer_push(&port->state->port); + } + + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); +} + +static void liteuart_putchar(struct uart_port *port, int ch) +{ + while (litex_get_reg(port->membase + OFF_TXFULL, 1)) + cpu_relax(); + + litex_set_reg(port->membase + OFF_RXTX, 1, ch); +} + +static unsigned int liteuart_tx_empty(struct uart_port *port) +{ + /* not really tx empty, just checking if tx is not full */ + if (!litex_get_reg(port->membase + OFF_TXFULL, 1)) + return TIOCSER_TEMT; + + return 0; +} + +static void liteuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* modem control register is not present in LiteUART */ +} + +static unsigned int liteuart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; +} + +static void liteuart_stop_tx(struct uart_port *port) +{ +} + +static void liteuart_start_tx(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + unsigned char ch; + + if (unlikely(port->x_char)) { + litex_set_reg(port->membase + OFF_RXTX, 1, port->x_char); + port->icount.tx++; + port->x_char = 0; + } else if (!uart_circ_empty(xmit)) { + while (xmit->head != xmit->tail) { + ch = xmit->buf[xmit->tail]; + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + liteuart_putchar(port, ch); + } + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static void liteuart_stop_rx(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* just delete timer */ + del_timer(&uart->timer); +} + +static void liteuart_break_ctl(struct uart_port *port, int break_state) +{ + /* LiteUART doesn't support sending break signal */ +} + +static int liteuart_startup(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* disable events */ + litex_set_reg(port->membase + OFF_EV_ENABLE, 1, 0); + + /* prepare timer for polling */ + timer_setup(&uart->timer, liteuart_timer, 0); + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + + return 0; +} + +static void liteuart_shutdown(struct uart_port *port) +{ +} + +static void liteuart_set_termios(struct uart_port *port, struct ktermios *new, + struct ktermios *old) +{ + unsigned int baud; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + /* update baudrate */ + baud = uart_get_baud_rate(port, new, old, 0, 460800); + uart_update_timeout(port, new->c_cflag, baud); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *liteuart_type(struct uart_port *port) +{ + return "liteuart"; +} + +static void liteuart_release_port(struct uart_port *port) +{ +} + +static int liteuart_request_port(struct uart_port *port) +{ + return 0; +} + +static void liteuart_config_port(struct uart_port *port, int flags) +{ + /* + * Driver core for serial ports forces a non-zero value for port type. + * Write an arbitrary value here to accommodate the serial core driver, + * as ID part of UAPI is redundant. + */ + port->type = 1; +} + +static int liteuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (port->type != PORT_UNKNOWN && ser->type != 1) + return -EINVAL; + + return 0; +} + +static const struct uart_ops liteuart_ops = { + .tx_empty = liteuart_tx_empty, + .set_mctrl = liteuart_set_mctrl, + .get_mctrl = liteuart_get_mctrl, + .stop_tx = liteuart_stop_tx, + .start_tx = liteuart_start_tx, + .stop_rx = liteuart_stop_rx, + .break_ctl = liteuart_break_ctl, + .startup = liteuart_startup, + .shutdown = liteuart_shutdown, + .set_termios = liteuart_set_termios, + .type = liteuart_type, + .release_port = liteuart_release_port, + .request_port = liteuart_request_port, + .config_port = liteuart_config_port, + .verify_port = liteuart_verify_port, +}; + +static int liteuart_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct liteuart_port *uart; + struct uart_port *port; + struct xa_limit limit; + int dev_id, ret; + + /* no device tree */ + if (!np) + return -ENODEV; + + /* look for aliases; auto-enumerate for free index if not found */ + dev_id = of_alias_get_id(np, "serial"); + if (dev_id < 0) + limit = XA_LIMIT(0, CONFIG_SERIAL_LITEUART_MAX_PORTS); + else + limit = XA_LIMIT(dev_id, dev_id); + + uart = kzalloc(sizeof(struct liteuart_port), GFP_KERNEL); + if (!uart) + return -ENOMEM; + + ret = xa_alloc(&liteuart_array, &dev_id, uart, limit, GFP_KERNEL); + if (ret) + return ret; + + port = &uart->port; + + /* get membase */ + port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (!port->membase) + return -ENXIO; + + /* values not from device tree */ + port->dev = &pdev->dev; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->ops = &liteuart_ops; + port->regshift = 2; + port->fifosize = 16; + port->iobase = 1; + port->type = PORT_UNKNOWN; + port->line = dev_id; + spin_lock_init(&port->lock); + + return uart_add_one_port(&liteuart_driver, &uart->port); +} + +static int liteuart_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id liteuart_of_match[] = { + { .compatible = "litex,liteuart" }, + {} +}; +MODULE_DEVICE_TABLE(of, liteuart_of_match); + +static struct platform_driver liteuart_platform_driver = { + .probe = liteuart_probe, + .remove = liteuart_remove, + .driver = { + .name = "liteuart", + .of_match_table = liteuart_of_match, + }, +}; + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + +static void liteuart_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct liteuart_port *uart; + struct uart_port *port; + unsigned long flags; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + port = &uart->port; + + spin_lock_irqsave(&port->lock, flags); + uart_console_write(port, s, count, liteuart_putchar); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int liteuart_console_setup(struct console *co, char *options) +{ + struct liteuart_port *uart; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + if (!uart) + return -ENODEV; + + port = &uart->port; + if (!port->membase) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console liteuart_console = { + .name = "liteuart", + .write = liteuart_console_write, + .device = uart_console_device, + .setup = liteuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &liteuart_driver, +}; + +static int __init liteuart_console_init(void) +{ + register_console(&liteuart_console); + + return 0; +} +console_initcall(liteuart_console_init); +#endif /* CONFIG_SERIAL_LITEUART_CONSOLE */ + +static int __init liteuart_init(void) +{ + int res; + + res = uart_register_driver(&liteuart_driver); + if (res) + return res; + + res = platform_driver_register(&liteuart_platform_driver); + if (res) { + uart_unregister_driver(&liteuart_driver); + return res; + } + + return 0; +} + +static void __exit liteuart_exit(void) +{ + platform_driver_unregister(&liteuart_platform_driver); + uart_unregister_driver(&liteuart_driver); +} + +module_init(liteuart_init); +module_exit(liteuart_exit); + +MODULE_AUTHOR("Antmicro "); +MODULE_DESCRIPTION("LiteUART serial driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform: liteuart");