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Tue, 11 Aug 2020 11:27:00 +0000 (GMT) X-AuditID: cbfec7f2-809ff70000001938-2a-5f3280849289 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3B.B3.06017.480823F5; Tue, 11 Aug 2020 12:27:00 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200811112700eusmtip2e9fa1b04b7188e2de2b42fec938f3d8f~qMx2jy6sQ2620926209eusmtip2G; Tue, 11 Aug 2020 11:27:00 +0000 (GMT) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Cc: tomasz.figa@gmail.com, cw00.choi@samsung.com, sboyd@kernel.org, mturquette@baylibre.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com, m.szyprowski@samsung.com, Sylwester Nawrocki Subject: [PATCH 2/2] clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks Date: Tue, 11 Aug 2020 13:26:45 +0200 Message-Id: <20200811112645.24596-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200811112645.24596-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42LZduznOd3WBqN4g54NTBYbZ6xntbj+5Tmr xceee6wWl3fNYbOYcX4fk8XaI3fZLS6ecrU4/Kad1eLftY0sFqt2/WF04PJ4f6OV3WPnrLvs HptWdbJ59G1ZxejxeZNcAGsUl01Kak5mWWqRvl0CV0bHgcnsBS8FKn5PaWJrYPzD28XIySEh YCJx9e9RNhBbSGAFo8Tkt0ldjFxA9hdGiQUrJjBBOJ8ZJeZ/aGGE6Vi34hULRGI5o8THSccY 4Vr27FzBAlLFJmAo0Xu0D6xDREBW4taxn2wgRcwCzUwSn/ubwIqEBRIk1i39CFbEIqAqcePa I1YQm1fAWuLJwy42iHXyEqs3HGAGsTkFbCRe7nsMNkhCoJ1d4s6/a1A3uUh8bv/IDmELS7w6 vgXKlpH4v3M+E0RDM6NEz+7b7BDOBEaJ+8cXQHVbS9w59wtoLAfQfZoS63fpg5gSAo4SzRs9 IUw+iRtvBUGKmYHMSdumM0OEeSU62oQgZqhI/F41nQnClpLofvKfBcL2kFj1/g40tPoZJf4/ 3Mg8gVF+FsKuBYyMqxjFU0uLc9NTiw3zUsv1ihNzi0vz0vWS83M3MQJTyOl/xz/tYPx6KekQ owAHoxIPb4G1YbwQa2JZcWXuIUYJDmYlEV6ns6fjhHhTEiurUovy44tKc1KLDzFKc7AoifMa L3oZKySQnliSmp2aWpBaBJNl4uCUamDMenIyRfGTmEV8XWhlqPuD2wuLfr24biyZ/fPGXdcL PJslb2tWFnAFO06qfLd3Dt+hF7adV9YFTXjUraQ6q/6xXIjc78S41J6LvI2KwqZXqhUcDMWz ryepW2YGGJbW3OksfjGrdVPll0+/XuVWyceIpL3WlHq6cIr6IiYTl2NH94asda0oZVNiKc5I NNRiLipOBAC2W3cCHQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsVy+t/xe7otDUbxBnOOa1tsnLGe1eL6l+es Fh977rFaXN41h81ixvl9TBZrj9xlt7h4ytXi8Jt2Vot/1zayWKza9YfRgcvj/Y1Wdo+ds+6y e2xa1cnm0bdlFaPH501yAaxRejZF+aUlqQoZ+cUltkrRhhZGeoaWFnpGJpZ6hsbmsVZGpkr6 djYpqTmZZalF+nYJehkdByazF7wUqPg9pYmtgfEPbxcjJ4eEgInEuhWvWLoYuTiEBJYySvw6 2wzkcAAlpCTmtyhB1AhL/LnWxQZR84lR4u7rTiaQBJuAoUTv0T5GEFtEQFbi1rGfYEXMAr1M Eu3ft7CAJIQF4iQO9ZwHK2IRUJW4ce0RK4jNK2At8eQhyFSQDfISqzccYAaxOQVsJF7uewwW FwKqmbbrM/MERr4FjAyrGEVSS4tz03OLjfSKE3OLS/PS9ZLzczcxAgN627GfW3Ywdr0LPsQo wMGoxMNbYG0YL8SaWFZcmXuIUYKDWUmE1+ns6Tgh3pTEyqrUovz4otKc1OJDjKZAR01klhJN zgdGW15JvKGpobmFpaG5sbmxmYWSOG+HwMEYIYH0xJLU7NTUgtQimD4mDk6pBkarYh6F+dMk A78lVD1b1tOV1PnmnwynxrujM9obq4WVmI4rrnRKXX0xQeummJm0beWNdevm2N2eZms5ZYbB MuOe+2158XpVheUTC776CSyRVtu20/FWLrtG0xUxgaUzmq77+oovfTp5zoO9TG/+/RJkj+Nh ddJeEtp1Ku01259nP/2jp0RNfKvEUpyRaKjFXFScCACJgNdwfgIAAA== X-CMS-MailID: 20200811112700eucas1p28bccc0c1a9e0c37d08f5f5bcd512cf30 X-Msg-Generator: CA X-RootMTR: 20200811112700eucas1p28bccc0c1a9e0c37d08f5f5bcd512cf30 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200811112700eucas1p28bccc0c1a9e0c37d08f5f5bcd512cf30 References: <20200811112645.24596-1-s.nawrocki@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. With that we have all clocks used in the clk_prepare_enable() calls in the clk provider init callback cached in clk_data.hws[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Signed-off-by: Sylwester Nawrocki --- Depends on patch: [PATCH v2] clk: samsung: Keep top BPLL mux on Exynos542x enabled drivers/clk/samsung/clk-exynos5420.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index bd62087..06841a6 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -712,8 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { SRC_TOP12, 8, 1), MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, SRC_TOP12, 12, 1), - MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1, - CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, + SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", @@ -1649,17 +1649,18 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_subcmus); } + hws = ctx->clk_data.hws; /* * Keep top part of G3D clock path enabled permanently to ensure * that the internal busses get their clock regardless of the * main G3D clock enablement status. */ - clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); /* * Keep top BPLL mux enabled permanently to ensure that DRAM operates * properly. */ - clk_prepare_enable(__clk_lookup("mout_bpll")); + clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); samsung_clk_of_add_provider(np, ctx); }