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Tue, 29 Sep 2020 10:35:43 +0000 Date: Tue, 29 Sep 2020 18:34:31 +0800 From: Jisheng Zhang To: Kishon Vijay Abraham I , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Ard Biesheuvel Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/2] PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled Message-ID: <20200929183431.0efda17c@xhacker.debian> In-Reply-To: <20200929183403.060d1853@xhacker.debian> References: <20200929183403.060d1853@xhacker.debian> X-Mailer: Claws Mail 3.17.6 (GTK+ 2.24.32; x86_64-pc-linux-gnu) X-Originating-IP: [124.74.246.114] X-ClientProxiedBy: TYBP286CA0025.JPNP286.PROD.OUTLOOK.COM (2603:1096:404:10a::13) To DM6PR03MB4555.namprd03.prod.outlook.com (2603:10b6:5:102::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from xhacker.debian (124.74.246.114) by TYBP286CA0025.JPNP286.PROD.OUTLOOK.COM (2603:1096:404:10a::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.32 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: A7eff9x2FZvV2hNZ747ORp+g+J7bkT0tL/4fZvOj+H83ZA9gXKiBua6s478znB9i1VpNuF4hVF+28MxCAJxqA4S3QzITm0XdZLoJjTcKe8CmQmMeu82TBN7/pD+874h5nx/VIzAEtEcXD+ky3cMcvA/mNeMoGfdVwsfZh6YqtlqHW+AzycACL1ZdhFRclQ61YmBG/yQN/yZDpQbDTGbS5gdwiF149jmb082gSKEtuPYjXYoqJhLk4VgUPJZqim70aNfN2JtrtxifMcc+GSXRzFD2UEWiM1jIk9L1hC/e+r+tteES5OjdaAP5BYBsiIzd63y7v8YX9fVzcOYJ+pgBALc1H3Dmon+9PLOvN1yacfvnzZnpDIiA2SN9C5lAqbj1Cc1gNKkrG7Aji7BXUikAWTR0cIy4LhZNVYxHdBMcutxQdHReXONN0ZtYS/GTlj5RUgGt2uabqf/0TdAadhIs9Sr4Mz6Tzvtb3SdnwbANFIfqH6z2+5mO+t5Px4C9JtvZ7OwyavxRnmAURe54w29DmXLmhp8COOkPv09sETGXpuoM7AJ1azPLozd2+8ejv/dSyitduG+THv5jc8T9xEPmsXzPyA+l7UQOlenP7tEmUQlqBbF8WMaUVxeTyMWLd+hdK2yJK8+Z+UaW6HObI8iWhA== X-OriginatorOrg: synaptics.com X-MS-Exchange-CrossTenant-Network-Message-Id: 66449bdc-4263-4fd2-328d-08d864636aba X-MS-Exchange-CrossTenant-AuthSource: DM6PR03MB4555.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2020 10:35:43.1730 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335d1fbc-2124-4173-9863-17e7051a2a0e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gyXCbNL6bXQIn9cn8+HlXIqhCeMfsq1ZvqsfKlea2BYoj3DJc3H5FimIilPyYl3cF1juKmoPTX1yTrl5068Zlg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB5292 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK and PCIE_MSI_INTR0_ENABLE registers. Signed-off-by: Jisheng Zhang Reviewed-by: Rob Herring Acked-by: Gustavo Pimentel --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9dafecba347f..f08f4d97f321 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -632,7 +632,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - if (!pp->ops->msi_host_init) { + if (pci_msi_enabled() && !pp->ops->msi_host_init) { num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; /* Initialize IRQ Status array */ From patchwork Tue Sep 29 10:34:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 295496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA2DC4346E for ; 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dkim=none (message not signed) header.d=none; ti.com; dmarc=none action=none header.from=synaptics.com; Received: from DM6PR03MB4555.namprd03.prod.outlook.com (2603:10b6:5:102::17) by DM6PR03MB5292.namprd03.prod.outlook.com (2603:10b6:5:240::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.32; Tue, 29 Sep 2020 10:36:07 +0000 Received: from DM6PR03MB4555.namprd03.prod.outlook.com ([fe80::e494:740f:155:4a38]) by DM6PR03MB4555.namprd03.prod.outlook.com ([fe80::e494:740f:155:4a38%7]) with mapi id 15.20.3433.032; Tue, 29 Sep 2020 10:36:07 +0000 Date: Tue, 29 Sep 2020 18:34:58 +0800 From: Jisheng Zhang To: Kishon Vijay Abraham I , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Ard Biesheuvel Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] PCI: dwc: Fix MSI page leakage in suspend/resume Message-ID: <20200929183458.37f91a38@xhacker.debian> In-Reply-To: <20200929183403.060d1853@xhacker.debian> References: <20200929183403.060d1853@xhacker.debian> X-Mailer: Claws Mail 3.17.6 (GTK+ 2.24.32; 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The Root Complex may lose power during suspend-to-RAM, so when we resume, we want to redo the latter but not the former. If designware based driver (for example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the msi page will be leaked. As pointed out by Rob and Ard, there's no need to allocate a page for the MSI address, we could use an address in the driver data. To avoid map the MSI msg again during resume, we move the map MSI msg from dw_pcie_msi_init() to dw_pcie_host_init(). Signed-off-by: Jisheng Zhang --- drivers/pci/controller/dwc/pci-dra7xx.c | 16 +++++++++- .../pci/controller/dwc/pcie-designware-host.c | 32 +++++++++---------- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index dc387724cf08..688e5e88784e 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -490,7 +490,9 @@ static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = { static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; u32 ctrl, num_ctrls; + int ret; pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip; @@ -506,7 +508,19 @@ static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) ~0); } - return dw_pcie_allocate_domains(pp); + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + pp->msi_data = dma_map_single(dev, pp->msi_msg, sizeof(pp->msi_msg), + DMA_FROM_DEVICE); + ret = dma_mapping_error(dev, pp->msi_data); + if (ret) { + dev_err(dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + dw_pcie_free_msi(pp); + } + return ret; } static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f08f4d97f321..27bbeee5718f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -288,26 +288,17 @@ void dw_pcie_free_msi(struct pcie_port *pp) irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); - if (pp->msi_page) - __free_page(pp->msi_page); + if (pp->msi_data) { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg), + DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); + } } void dw_pcie_msi_init(struct pcie_port *pp) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct device *dev = pci->dev; - u64 msi_target; - - pp->msi_page = alloc_page(GFP_KERNEL); - pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, pp->msi_data)) { - dev_err(dev, "Failed to map MSI data\n"); - __free_page(pp->msi_page); - pp->msi_page = NULL; - return; - } - msi_target = (u64)pp->msi_data; + u64 msi_target = (u64)pp->msi_data; /* Program the msi_data */ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, @@ -440,6 +431,15 @@ int dw_pcie_host_init(struct pcie_port *pp) irq_set_chained_handler_and_data(pp->msi_irq, dw_chained_msi_isr, pp); + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + if (dma_mapping_error(pci->dev, pp->msi_data)) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + goto err_free_msi; + } } else { ret = pp->ops->msi_host_init(pp); if (ret < 0) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index f911760dcc69..cd9e76904c58 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -194,8 +194,8 @@ struct pcie_port { int msi_irq; struct irq_domain *irq_domain; struct irq_domain *msi_domain; + u16 msi_msg; dma_addr_t msi_data; - struct page *msi_page; struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS];