From patchwork Fri Sep 25 01:56:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5Yav6ZSQ?= X-Patchwork-Id: 256309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44F0FC4346E for ; Fri, 25 Sep 2020 02:08:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 086D320888 for ; Fri, 25 Sep 2020 02:08:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726738AbgIYCIE (ORCPT ); Thu, 24 Sep 2020 22:08:04 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:59056 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbgIYCIE (ORCPT ); Thu, 24 Sep 2020 22:08:04 -0400 X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 08P1uSsnD001620, This message is accepted by code: ctloc85258 Received: from RSEXMBS01.realsil.com.cn ([172.29.17.195]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 08P1uSsnD001620 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Fri, 25 Sep 2020 09:56:28 +0800 Received: from localhost (172.29.40.150) by RSEXMBS01.realsil.com.cn (172.29.17.195) with Microsoft SMTP Server id 15.1.2044.4; Fri, 25 Sep 2020 09:56:27 +0800 From: To: , , CC: , , Christoph Hellwig , Rui Feng Subject: [PATCH 1/3] mmc: core: Initial support for SD express card/host Date: Fri, 25 Sep 2020 09:56:26 +0800 Message-ID: <1600998986-13575-1-git-send-email-rui_feng@realsil.com.cn> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [172.29.40.150] Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ulf Hansson In the SD specification v7.10 the SD express card has been added. This new type of removable SD card, can be managed via a PCIe/NVMe based interface, while also allowing backwards compatibility towards the legacy SD interface. To keep the backwards compatibility, it's required to start the initialization through the legacy SD interface. If it turns out that the mmc host and the SD card, both supports the PCIe/NVMe interface, then a switch should be allowed. Therefore, let's introduce some basic support for this type of SD cards to the mmc core. The mmc host, should set MMC_CAP2_SD_EXP if it supports this interface and MMC_CAP2_SD_EXP_1_2V, if also 1.2V is supported, as to inform the core about it. To deal with the switch to the PCIe/NVMe interface, the mmc host is required to implement a new host ops, ->init_sd_express(). Based on the initial communication between the host and the card, host->ios.timing is set to either MMC_TIMING_SD_EXP or MMC_TIMING_SD_EXP_1_2V, depending on if 1.2V is supported or not. In this way, the mmc host can check these values in its ->init_sd_express() ops, to know how to proceed with the handover. Note that, to manage card insert/removal, the mmc core sticks with using the ->get_cd() callback, which means it's the host's responsibility to make sure it provides valid data, even if the card may be managed by PCIe/NVMe at the moment. As long as the card seems to be present, the mmc core keeps the card powered on. Cc: Greg Kroah-Hartman Cc: Arnd Bergmann Cc: Christoph Hellwig Cc: Rui Feng Signed-off-by: Ulf Hansson Reviewed-by: Greg Kroah-Hartman --- drivers/mmc/core/core.c | 15 ++++++++++-- drivers/mmc/core/host.h | 6 +++++ drivers/mmc/core/sd_ops.c | 49 +++++++++++++++++++++++++++++++++++++-- drivers/mmc/core/sd_ops.h | 1 + include/linux/mmc/host.h | 7 ++++++ 5 files changed, 74 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 8ccae6452b9c..6673c0f33cc7 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2137,8 +2137,12 @@ static int mmc_rescan_try_freq(struct mmc_host *host, unsigned freq) mmc_go_idle(host); - if (!(host->caps2 & MMC_CAP2_NO_SD)) - mmc_send_if_cond(host, host->ocr_avail); + if (!(host->caps2 & MMC_CAP2_NO_SD)) { + if (mmc_send_if_cond_pcie(host, host->ocr_avail)) + goto out; + if (mmc_card_sd_express(host)) + return 0; + } /* Order's important: probe SDIO, then SD, then MMC */ if (!(host->caps2 & MMC_CAP2_NO_SDIO)) @@ -2153,6 +2157,7 @@ static int mmc_rescan_try_freq(struct mmc_host *host, unsigned freq) if (!mmc_attach_mmc(host)) return 0; +out: mmc_power_off(host); return -EIO; } @@ -2280,6 +2285,12 @@ void mmc_rescan(struct work_struct *work) goto out; } + /* If an SD express card is present, then leave it as is. */ + if (mmc_card_sd_express(host)) { + mmc_release_host(host); + goto out; + } + for (i = 0; i < ARRAY_SIZE(freqs); i++) { unsigned int freq = freqs[i]; if (freq > host->f_max) { diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h index 5e3b9534ffb2..ba407617ed23 100644 --- a/drivers/mmc/core/host.h +++ b/drivers/mmc/core/host.h @@ -77,5 +77,11 @@ static inline bool mmc_card_hs400es(struct mmc_card *card) return card->host->ios.enhanced_strobe; } +static inline bool mmc_card_sd_express(struct mmc_host *host) +{ + return host->ios.timing == MMC_TIMING_SD_EXP || + host->ios.timing == MMC_TIMING_SD_EXP_1_2V; +} + #endif diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index 22bf528294b9..d61ff811218c 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -158,7 +158,8 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) return err; } -int mmc_send_if_cond(struct mmc_host *host, u32 ocr) +static int __mmc_send_if_cond(struct mmc_host *host, u32 ocr, u8 pcie_bits, + u32 *resp) { struct mmc_command cmd = {}; int err; @@ -171,7 +172,7 @@ int mmc_send_if_cond(struct mmc_host *host, u32 ocr) * SD 1.0 cards. */ cmd.opcode = SD_SEND_IF_COND; - cmd.arg = ((ocr & 0xFF8000) != 0) << 8 | test_pattern; + cmd.arg = ((ocr & 0xFF8000) != 0) << 8 | pcie_bits << 8 | test_pattern; cmd.flags = MMC_RSP_SPI_R7 | MMC_RSP_R7 | MMC_CMD_BCR; err = mmc_wait_for_cmd(host, &cmd, 0); @@ -186,6 +187,50 @@ int mmc_send_if_cond(struct mmc_host *host, u32 ocr) if (result_pattern != test_pattern) return -EIO; + if (resp) + *resp = cmd.resp[0]; + + return 0; +} + +int mmc_send_if_cond(struct mmc_host *host, u32 ocr) +{ + return __mmc_send_if_cond(host, ocr, 0, NULL); +} + +int mmc_send_if_cond_pcie(struct mmc_host *host, u32 ocr) +{ + u32 resp = 0; + u8 pcie_bits = 0; + int ret; + + if (host->caps2 & MMC_CAP2_SD_EXP) { + /* Probe card for SD express support via PCIe. */ + pcie_bits = 0x10; + if (host->caps2 & MMC_CAP2_SD_EXP_1_2V) + /* Probe also for 1.2V support. */ + pcie_bits = 0x30; + } + + ret = __mmc_send_if_cond(host, ocr, pcie_bits, &resp); + if (ret) + return 0; + + /* Continue with the SD express init, if the card supports it. */ + resp &= 0x3000; + if (pcie_bits && resp) { + if (resp == 0x3000) + host->ios.timing = MMC_TIMING_SD_EXP_1_2V; + else + host->ios.timing = MMC_TIMING_SD_EXP; + + /* + * According to the spec the clock shall also be gated, but + * let's leave this to the host driver for more flexibility. + */ + return host->ops->init_sd_express(host, &host->ios); + } + return 0; } diff --git a/drivers/mmc/core/sd_ops.h b/drivers/mmc/core/sd_ops.h index 2194cabfcfc5..3ba7b3cf4652 100644 --- a/drivers/mmc/core/sd_ops.h +++ b/drivers/mmc/core/sd_ops.h @@ -16,6 +16,7 @@ struct mmc_host; int mmc_app_set_bus_width(struct mmc_card *card, int width); int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr); int mmc_send_if_cond(struct mmc_host *host, u32 ocr); +int mmc_send_if_cond_pcie(struct mmc_host *host, u32 ocr); int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca); int mmc_app_send_scr(struct mmc_card *card); int mmc_sd_switch(struct mmc_card *card, int mode, int group, diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index c5b6e97cb21a..905cddc5e6f3 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -60,6 +60,8 @@ struct mmc_ios { #define MMC_TIMING_MMC_DDR52 8 #define MMC_TIMING_MMC_HS200 9 #define MMC_TIMING_MMC_HS400 10 +#define MMC_TIMING_SD_EXP 11 +#define MMC_TIMING_SD_EXP_1_2V 12 unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ @@ -172,6 +174,9 @@ struct mmc_host_ops { */ int (*multi_io_quirk)(struct mmc_card *card, unsigned int direction, int blk_size); + + /* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */ + int (*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios); }; struct mmc_cqe_ops { @@ -357,6 +362,8 @@ struct mmc_host { #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ MMC_CAP2_HS200_1_2V_SDR) +#define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ +#define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ From patchwork Fri Sep 25 01:57:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5Yav6ZSQ?= X-Patchwork-Id: 295373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3F5FC4363D for ; Fri, 25 Sep 2020 02:08:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A057C20888 for ; Fri, 25 Sep 2020 02:08:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726730AbgIYCID (ORCPT ); Thu, 24 Sep 2020 22:08:03 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:59026 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbgIYCID (ORCPT ); Thu, 24 Sep 2020 22:08:03 -0400 X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 08P1vYAS1002084, This message is accepted by code: ctloc85258 Received: from RSEXMBS01.realsil.com.cn ([172.29.17.195]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 08P1vYAS1002084 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Fri, 25 Sep 2020 09:57:34 +0800 Received: from localhost (172.29.40.150) by RSEXMBS01.realsil.com.cn (172.29.17.195) with Microsoft SMTP Server id 15.1.2044.4; Fri, 25 Sep 2020 09:57:33 +0800 From: To: , , CC: , , Rui Feng Subject: [PATCH 2/3] misc: rtsx: Add SD Express mode support for RTS5261 Date: Fri, 25 Sep 2020 09:57:32 +0800 Message-ID: <1600999052-13634-1-git-send-email-rui_feng@realsil.com.cn> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [172.29.40.150] Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Rui Feng RTS5261 support legacy SD mode and SD Express mode. In SD7.x, SD association introduce SD Express as a new mode. This patch makes RTS5261 support SD Express mode. Signed-off-by: Rui Feng --- drivers/misc/cardreader/rts5261.c | 4 ++++ drivers/misc/cardreader/rts5261.h | 23 ----------------------- drivers/misc/cardreader/rtsx_pcr.c | 5 +++++ include/linux/rtsx_pci.h | 28 ++++++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 23 deletions(-) diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c index 471961487ff8..536c90d4fd76 100644 --- a/drivers/misc/cardreader/rts5261.c +++ b/drivers/misc/cardreader/rts5261.c @@ -738,8 +738,12 @@ void rts5261_init_params(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &pcr->option; struct rtsx_hw_param *hw_param = &pcr->hw_param; + u8 val; pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; + rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val); + if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK)) + pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; pcr->num_slots = 1; pcr->ops = &rts5261_pcr_ops; diff --git a/drivers/misc/cardreader/rts5261.h b/drivers/misc/cardreader/rts5261.h index ebfdd236a553..8d80f0d5d5d6 100644 --- a/drivers/misc/cardreader/rts5261.h +++ b/drivers/misc/cardreader/rts5261.h @@ -65,23 +65,6 @@ #define RTS5261_FW_EXPRESS_TEST_MASK (0x01<<0) #define RTS5261_FW_EA_MODE_MASK (0x01<<5) -/* FW config register */ -#define RTS5261_FW_CFG0 0xFF54 -#define RTS5261_FW_ENTER_EXPRESS (0x01<<0) - -#define RTS5261_FW_CFG1 0xFF55 -#define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01<<7) -#define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01<<6) -#define RTS5261_FAKE_MCU_CLOCK_GATING (0x01<<5) -/*MCU_bus_mode_sel: 0=real 8051 1=fake mcu*/ -#define RTS5261_MCU_BUS_SEL_MASK (0x01<<4) -/*MCU_clock_sel:VerA 00=aux16M 01=aux400K 1x=REFCLK100M*/ -/*MCU_clock_sel:VerB 00=aux400K 01=aux16M 10=REFCLK100M*/ -#define RTS5261_MCU_CLOCK_SEL_MASK (0x03<<2) -#define RTS5261_MCU_CLOCK_SEL_16M (0x01<<2) -#define RTS5261_MCU_CLOCK_GATING (0x01<<1) -#define RTS5261_DRIVER_ENABLE_FW (0x01<<0) - /* FW status register */ #define RTS5261_FW_STATUS 0xFF56 #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) @@ -121,12 +104,6 @@ #define RTS5261_DV3318_19 (0x04<<4) #define RTS5261_DV3318_33 (0x07<<4) -#define RTS5261_LDO1_CFG0 0xFF72 -#define RTS5261_LDO1_OCP_THD_MASK (0x07<<5) -#define RTS5261_LDO1_OCP_EN (0x01<<4) -#define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03<<2) -#define RTS5261_LDO1_OCP_LMT_EN (0x01<<1) - /* CRD6603-433 190319 request changed */ #define RTS5261_LDO1_OCP_THD_740 (0x00<<5) #define RTS5261_LDO1_OCP_THD_800 (0x01<<5) diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index 37ccc67f4914..6e5c16b4b7d1 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -990,6 +990,11 @@ static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) } else { pcr->card_removed |= SD_EXIST; pcr->card_inserted &= ~SD_EXIST; + if (PCI_PID(pcr) == PID_5261) { + rtsx_pci_write_register(pcr, RTS5261_FW_STATUS, + RTS5261_EXPRESS_LINK_FAIL_MASK, 0); + pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; + } } pcr->dma_error_count = 0; } diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h index 745f5e73f99a..cea8147e5992 100644 --- a/include/linux/rtsx_pci.h +++ b/include/linux/rtsx_pci.h @@ -658,6 +658,24 @@ #define PM_WAKE_EN 0x01 #define PM_CTRL4 0xFF47 +#define RTS5261_FW_CFG0 0xFF54 +#define RTS5261_FW_ENTER_EXPRESS (0x01 << 0) + +#define RTS5261_FW_CFG1 0xFF55 +#define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01 << 7) +#define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01 << 6) +#define RTS5261_FAKE_MCU_CLOCK_GATING (0x01 << 5) +#define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4) +#define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4) +#define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2) +#define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2) +#define RTS5261_MCU_CLOCK_GATING (0x01 << 1) +#define RTS5261_DRIVER_ENABLE_FW (0x01 << 0) +#define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2) +#define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2) +#define RTS5261_MCU_CLOCK_GATING (0x01 << 1) +#define RTS5261_DRIVER_ENABLE_FW (0x01 << 0) + #define REG_CFG_OOBS_OFF_TIMER 0xFEA6 #define REG_CFG_OOBS_ON_TIMER 0xFEA7 #define REG_CFG_VCM_ON_TIMER 0xFEA8 @@ -701,6 +719,13 @@ #define RTS5260_DVCC_TUNE_MASK 0x70 #define RTS5260_DVCC_33 0x70 +/*RTS5261*/ +#define RTS5261_LDO1_CFG0 0xFF72 +#define RTS5261_LDO1_OCP_THD_MASK (0x07 << 5) +#define RTS5261_LDO1_OCP_EN (0x01 << 4) +#define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03 << 2) +#define RTS5261_LDO1_OCP_LMT_EN (0x01 << 1) + #define LDO_VCC_CFG1 0xFF73 #define LDO_VCC_REF_TUNE_MASK 0x30 #define LDO_VCC_REF_1V2 0x20 @@ -741,6 +766,8 @@ #define RTS5260_AUTOLOAD_CFG4 0xFF7F #define RTS5260_MIMO_DISABLE 0x8A +/*RTS5261*/ +#define RTS5261_AUX_CLK_16M_EN (1 << 5) #define RTS5260_REG_GPIO_CTL0 0xFC1A #define RTS5260_REG_GPIO_MASK 0x01 @@ -1191,6 +1218,7 @@ struct rtsx_pcr { #define EXTRA_CAPS_MMC_HS200 (1 << 4) #define EXTRA_CAPS_MMC_8BIT (1 << 5) #define EXTRA_CAPS_NO_MMC (1 << 7) +#define EXTRA_CAPS_SD_EXPRESS (1 << 8) u32 extra_caps; #define IC_VER_A 0 From patchwork Fri Sep 25 01:57:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5Yav6ZSQ?= X-Patchwork-Id: 256310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E89E2C4346E for ; Fri, 25 Sep 2020 02:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABA4120BED for ; Fri, 25 Sep 2020 02:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbgIYCIB (ORCPT ); Thu, 24 Sep 2020 22:08:01 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:59024 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbgIYCIA (ORCPT ); Thu, 24 Sep 2020 22:08:00 -0400 X-Greylist: delayed 665 seconds by postgrey-1.27 at vger.kernel.org; Thu, 24 Sep 2020 22:08:00 EDT X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 08P1vhAfB002096, This message is accepted by code: ctloc85258 Received: from RSEXMBS01.realsil.com.cn ([172.29.17.195]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 08P1vhAfB002096 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Fri, 25 Sep 2020 09:57:43 +0800 Received: from localhost (172.29.40.150) by RSEXMBS01.realsil.com.cn (172.29.17.195) with Microsoft SMTP Server id 15.1.2044.4; Fri, 25 Sep 2020 09:57:42 +0800 From: To: , , CC: , , Rui Feng Subject: [PATCH 3/3] mmc: rtsx: Add SD Express mode support for RTS5261 Date: Fri, 25 Sep 2020 09:57:41 +0800 Message-ID: <1600999061-13669-1-git-send-email-rui_feng@realsil.com.cn> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [172.29.40.150] Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Rui Feng RTS5261 support legacy SD mode and SD Express mode. In SD7.x, SD association introduce SD Express as a new mode. This patch makes RTS5261 support SD Express mode. Signed-off-by: Rui Feng --- drivers/mmc/host/rtsx_pci_sdmmc.c | 59 +++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c index 2763a376b054..efde374a4a5e 100644 --- a/drivers/mmc/host/rtsx_pci_sdmmc.c +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c @@ -895,7 +895,9 @@ static int sd_set_bus_width(struct realtek_pci_sdmmc *host, static int sd_power_on(struct realtek_pci_sdmmc *host) { struct rtsx_pcr *pcr = host->pcr; + struct mmc_host *mmc = host->mmc; int err; + u32 val; if (host->power_state == SDMMC_POWER_ON) return 0; @@ -922,6 +924,14 @@ static int sd_power_on(struct realtek_pci_sdmmc *host) if (err < 0) return err; + if (PCI_PID(pcr) == PID_5261) { + val = rtsx_pci_readl(pcr, RTSX_BIPR); + if (val & SD_WRITE_PROTECT) { + pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; + mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); + } + } + host->power_state = SDMMC_POWER_ON; return 0; } @@ -1127,6 +1137,8 @@ static int sdmmc_get_cd(struct mmc_host *mmc) if (val & SD_EXIST) cd = 1; + if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) + mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; mutex_unlock(&pcr->pcr_mutex); return cd; @@ -1308,6 +1320,50 @@ static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) return err; } +static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) +{ + u32 relink_time, val; + struct realtek_pci_sdmmc *host = mmc_priv(mmc); + struct rtsx_pcr *pcr = host->pcr; + + /* + * If card has PCIe availability and WP if off, + * reader switch to PCIe mode. + */ + val = rtsx_pci_readl(pcr, RTSX_BIPR); + if (!(val & SD_WRITE_PROTECT)) { + /* Set relink_time for changing to PCIe card */ + relink_time = 0x8FFF; + + rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); + rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); + rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); + + rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); + rtsx_pci_write_register(pcr, LDO_VCC_CFG0, + RTS5261_LDO1_OCP_THD_MASK, + pcr->option.sd_800mA_ocp_thd); + + if (pcr->ops->disable_auto_blink) + pcr->ops->disable_auto_blink(pcr); + + /* For PCIe/NVMe mode can't enter delink issue */ + pcr->hw_param.interrupt_en &= ~(SD_INT_EN); + rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); + + rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, + RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); + rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, + RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); + rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, + RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK + | RTS5261_MCU_CLOCK_GATING | RTS5261_DRIVER_ENABLE_FW, + RTS5261_MCU_CLOCK_SEL_16M | RTS5261_MCU_CLOCK_GATING + | RTS5261_DRIVER_ENABLE_FW); + } + return 0; +} + static const struct mmc_host_ops realtek_pci_sdmmc_ops = { .pre_req = sdmmc_pre_req, .post_req = sdmmc_post_req, @@ -1317,6 +1373,7 @@ static const struct mmc_host_ops realtek_pci_sdmmc_ops = { .get_cd = sdmmc_get_cd, .start_signal_voltage_switch = sdmmc_switch_voltage, .execute_tuning = sdmmc_execute_tuning, + .init_sd_express = sdmmc_init_sd_express, }; static void init_extra_caps(struct realtek_pci_sdmmc *host) @@ -1338,6 +1395,8 @@ static void init_extra_caps(struct realtek_pci_sdmmc *host) mmc->caps |= MMC_CAP_8_BIT_DATA; if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) mmc->caps2 |= MMC_CAP2_NO_MMC; + if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) + mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; } static void realtek_init_host(struct realtek_pci_sdmmc *host)