From patchwork Mon Aug 3 15:42:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21EE1C433ED for ; Mon, 3 Aug 2020 15:43:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F38072072A for ; Mon, 3 Aug 2020 15:43:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="J9URXn7r" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727936AbgHCPmc (ORCPT ); Mon, 3 Aug 2020 11:42:32 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:1748 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725945AbgHCPmc (ORCPT ); Mon, 3 Aug 2020 11:42:32 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 08:42:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 08:42:31 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 03 Aug 2020 08:42:31 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 3 Aug 2020 15:42:31 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 3 Aug 2020 15:42:31 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 03 Aug 2020 08:42:31 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v8 01/10] media: tegra-video: Fix channel format alignment Date: Mon, 3 Aug 2020 08:42:17 -0700 Message-ID: <1596469346-937-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596469338; bh=8GJbUvoTqNXQhoilqMQO06MgCPv5IgO6eahUeR7/0ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=J9URXn7rMZFZccEKJYxPqRptaEUBofPPMk7FjAt4gq4IjFPO133OgDFVRC4Ln1iev dgVOo41Qo8u23/NX0ixCdh7HocuN8e/ELZDYL+NK6+o7uOiHJBX8qfMSa3PXG6L0Ax 7KWoQ2JvYWh4SUO3LOCyUwrfu0dOpBNcmtqAO4sFmNS/V01+MngwC8pR5xt2LcIb8b rrwzR9//F+2DHmWuzmF7GEtTxTm0xQop31XaJhoc81n+GtPCY0cS8dVG5+tsy4MAX2 /fWtFDqCGD1FwyFPkm3kRA2zlyRebOJjaKTP9l6R4TGgtFCR3vk9/weYNufFM+7jm7 bMgyUc2WyFSvw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 1b5e660..d621ebc 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per From patchwork Mon Aug 3 15:42:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF3FDC433E4 for ; Mon, 3 Aug 2020 15:43:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B07BB207FB for ; Mon, 3 Aug 2020 15:43:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="dF91DR81" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728327AbgHCPnP (ORCPT ); Mon, 3 Aug 2020 11:43:15 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:1755 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727940AbgHCPmd (ORCPT ); Mon, 3 Aug 2020 11:42:33 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 08:42:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 08:42:32 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Aug 2020 08:42:32 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 3 Aug 2020 15:42:32 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 3 Aug 2020 15:42:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 03 Aug 2020 08:42:32 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v8 03/10] media: tegra-video: Update format lookup to offset based Date: Mon, 3 Aug 2020 08:42:19 -0700 Message-ID: <1596469346-937-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596469339; bh=5U56MbpoGgbizDY87xBQZF5BWeIIcAyUuev+l62V8Co=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dF91DR81a20NtX/8TPxKYS5JdyhPM5NFEhUrAbelo90okyZpTMjKJ075GMDrBIr4t oGrj8Vl6n/18imN3fj3F0V0mGi7I6IHGBvQLSwL4+y/ZbqskFEUzek4k8mAwEQHejD maJkre9QTS2lWeJKQ67u+rBM+0NfeOom/EP1CYxcFhX08d8lNMX8paZEZ1uoD9r3Vz sg85q5/YfIaCRbxdCrXOepubxQwrUeOAmPd7ST8U4ZpZVQ4m0qpqTv1uqebBMoWZwZ dQl/0p7YZjpweeHfI0qFU7zfVGWhgIZl3LhuQwdvlrQowEskFjol8gsYD+arWxP/I4 HfDjZtaaFK5GA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra VI supported video formats are more for non TPG and there can be multiple pixel formats for the same media bus format. This patch updates the helper function for format lookup based on mbus code from pre-defined Tegra supported format list to look from the specified list index offset. Offset based look up is used with sensor device graph (non TPG) where format enumeration can list all supported formats for the specific sensor mbus codes. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 0197f4e..52d751f 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -53,11 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) } static int tegra_get_format_idx_by_code(struct tegra_vi *vi, - unsigned int code) + unsigned int code, + unsigned int offset) { unsigned int i; - for (i = 0; i < vi->soc->nformats; ++i) { + for (i = offset; i < vi->soc->nformats; ++i) { if (vi->soc->video_formats[i].code == code) return i; } @@ -598,11 +599,12 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_zero(chan->tpg_fmts_bitmap, MAX_FORMAT_NUM); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_SRGGB10_1X10); + MEDIA_BUS_FMT_SRGGB10_1X10, 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); index = tegra_get_format_idx_by_code(chan->vi, - MEDIA_BUS_FMT_RGB888_1X32_PADHI); + MEDIA_BUS_FMT_RGB888_1X32_PADHI, + 0); bitmap_set(chan->tpg_fmts_bitmap, index, 1); } From patchwork Mon Aug 3 15:42:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1C92C433DF for ; Mon, 3 Aug 2020 15:43:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D5D920825 for ; Mon, 3 Aug 2020 15:43:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="B5PQJu+D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728024AbgHCPmf (ORCPT ); Mon, 3 Aug 2020 11:42:35 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:1767 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727982AbgHCPme (ORCPT ); Mon, 3 Aug 2020 11:42:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 08:42:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 08:42:34 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 03 Aug 2020 08:42:34 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 3 Aug 2020 15:42:33 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 3 Aug 2020 15:42:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 03 Aug 2020 08:42:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v8 05/10] media: tegra-video: Separate CSI stream enable and disable implementations Date: Mon, 3 Aug 2020 08:42:21 -0700 Message-ID: <1596469346-937-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596469340; bh=uZgxrGDkUOMRSXaG0qPPXkX0uRgXXAAvq4AEaGdQuMg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=B5PQJu+DTgGLMJ0RGrPt79gOFq0SEWDe+YNVFPe9cJSl0HIgkUTn43R6iG0vAOC+K cfpVxI/VniwJwDTUrmAwczlIn3RvpmrQTjO15VUv9OU8XxdahdQTJE3n4e7F0VtQ4l koV6t5OuVrQK+to0evMYDK06oxudYpPXdmPib26nf7Y6pSD0h0jF95bNr9I31SVWIk wSMA4XYGoLbY68MBOwCTnw0KtwoeO2R5GP88U2UTVDM6x0nzzzHmNduBQnqzru6LhH f4BelJc6M4U4AinEwHR0fwAO9cFz9VIc0oT0ps10C9x/X6vjLEwnBVmT15CtgRE3lg 0pbBuIZFE2mLQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch separates implementation of CSI stream enable and disable into separate functions for readability. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 51 ++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index fb667df..cfe6187 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -232,34 +232,53 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } -static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) +static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); struct tegra_csi *csi = csi_chan->csi; - int ret = 0; + int ret; + + ret = pm_runtime_get_sync(csi->dev); + if (ret < 0) { + dev_err(csi->dev, "failed to get runtime PM: %d\n", ret); + pm_runtime_put_noidle(csi->dev); + return ret; + } csi_chan->pg_mode = chan->pg_mode; - if (enable) { - ret = pm_runtime_get_sync(csi->dev); - if (ret < 0) { - dev_err(csi->dev, - "failed to get runtime PM: %d\n", ret); - pm_runtime_put_noidle(csi->dev); - return ret; - } + ret = csi->ops->csi_start_streaming(csi_chan); + if (ret < 0) + goto rpm_put; - ret = csi->ops->csi_start_streaming(csi_chan); - if (ret < 0) - goto rpm_put; + return 0; - return 0; - } +rpm_put: + pm_runtime_put(csi->dev); + return ret; +} + +static int tegra_csi_disable_stream(struct v4l2_subdev *subdev) +{ + struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); + struct tegra_csi *csi = csi_chan->csi; csi->ops->csi_stop_streaming(csi_chan); -rpm_put: pm_runtime_put(csi->dev); + + return 0; +} + +static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) +{ + int ret; + + if (enable) + ret = tegra_csi_enable_stream(subdev); + else + ret = tegra_csi_disable_stream(subdev); + return ret; } From patchwork Mon Aug 3 15:42:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34050C433E5 for ; Mon, 3 Aug 2020 15:42:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1343720678 for ; Mon, 3 Aug 2020 15:42:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Hk7O5fwZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728090AbgHCPmh (ORCPT ); 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Mon, 03 Aug 2020 08:42:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v8 09/10] media: tegra-video: Add CSI MIPI pads calibration Date: Mon, 3 Aug 2020 08:42:25 -0700 Message-ID: <1596469346-937-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596469343; bh=wjMru0Xx0/s2zVzJbM4fA0J8mm4jBcYWSEZ8/rkyVEY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Hk7O5fwZ5UFFHsLNdNoILraiI1EkkAoK4BZdbIJuxKcOo2InG/x5t8eEwNDJ5qHr8 +S4zbtHXJHPtsRbCwiqLAdGmS9zbmrrX9QjH6E/Uf1V1jLv7cYmdRD1eQraT87EGsm ksymOlhnDua5Cc2n6mzNTm78cOCI/H2LgMizBMdrADMIkvPi1Wc/IE3lPm+9A1LY73 2gVMCcL9pDIPRywJWZS6KxvE1HCDSQjYgo1hlk3SyiTJA41TLyhyS8YOWdTtHNbnqd nyvl6DrWvRZ/DYIBxJZMzxyTJmnPHUMu2KyvZmiAnJfyYcKGkNE/9T4I330KDuRIeR x8zWBnnMkFhhA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CSI MIPI pads need to be enabled and calibrated for capturing from the external sensor or transmitter. MIPI CAL unit calibrates MIPI pads pull-up, pull-down and termination impedances. Calibration is done by co-work of MIPI BIAS pad and MIPI CAL control unit. Triggering calibration start can happen any time after MIPI pads are enabled but calibration results will be latched and applied to MIPI pads by MIPI CAL unit only when the link is in LP11 state and then calibration status register gets updated. This patch enables CSI MIPI pads and calibrates them during streaming. Tegra CSI receiver is able to catch the very first clock transition. So, CSI receiver is always enabled prior to sensor streaming and trigger of calibration start is done during CSI subdev streaming and status of calibration is verified after sensor stream on. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/TODO | 1 - drivers/staging/media/tegra-video/csi.c | 61 +++++++++++++++++++++++++++++++-- drivers/staging/media/tegra-video/csi.h | 2 ++ drivers/staging/media/tegra-video/vi.c | 28 ++++++++++++--- 4 files changed, 84 insertions(+), 8 deletions(-) diff --git a/drivers/staging/media/tegra-video/TODO b/drivers/staging/media/tegra-video/TODO index 97a19b4..98d3c7d 100644 --- a/drivers/staging/media/tegra-video/TODO +++ b/drivers/staging/media/tegra-video/TODO @@ -1,5 +1,4 @@ TODO list -* Add Tegra CSI MIPI pads calibration. * Add MIPI clock Settle time computation based on the data rate. * Add support for Ganged mode. * Add RAW10 packed video format support to Tegra210 video formats. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 4176933..76b4311 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -240,7 +240,7 @@ static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); struct tegra_csi *csi = csi_chan->csi; - int ret; + int ret, err; ret = pm_runtime_get_sync(csi->dev); if (ret < 0) { @@ -249,13 +249,47 @@ static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) return ret; } + if (csi_chan->mipi) { + ret = tegra_mipi_enable(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to enable MIPI pads: %d\n", ret); + goto rpm_put; + } + + /* + * CSI MIPI pads PULLUP, PULLDN and TERM impedances need to + * be calibrated after power on. + * So, trigger the calibration start here and results will + * be latched and applied to the pads when link is in LP11 + * state during start of sensor streaming. + */ + ret = tegra_mipi_start_calibration(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to start MIPI calibration: %d\n", ret); + goto disable_mipi; + } + } + csi_chan->pg_mode = chan->pg_mode; ret = csi->ops->csi_start_streaming(csi_chan); if (ret < 0) - goto rpm_put; + goto cancel_calibration; return 0; +cancel_calibration: + if (csi_chan->mipi) + tegra_mipi_cancel_calibration(csi_chan->mipi); +disable_mipi: + if (csi_chan->mipi) { + err = tegra_mipi_disable(csi_chan->mipi); + if (err < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", err); + } + rpm_put: pm_runtime_put(csi->dev); return ret; @@ -265,9 +299,17 @@ static int tegra_csi_disable_stream(struct v4l2_subdev *subdev) { struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); struct tegra_csi *csi = csi_chan->csi; + int err; csi->ops->csi_stop_streaming(csi_chan); + if (csi_chan->mipi) { + err = tegra_mipi_disable(csi_chan->mipi); + if (err < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", err); + } + pm_runtime_put(csi->dev); return 0; @@ -313,6 +355,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; + int ret = 0; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -331,7 +374,16 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; } - return 0; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + chan->mipi = tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret = PTR_ERR(chan->mipi); + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } + + return ret; } static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) @@ -503,6 +555,9 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) struct tegra_csi_channel *chan, *tmp; list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { + if (chan->mipi) + tegra_mipi_free(chan->mipi); + subdev = &chan->subdev; if (subdev->dev) { if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 78a5110..0d50fc3 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -50,6 +50,7 @@ struct tegra_csi; * @framerate: active framerate for TPG * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format + * @mipi: mipi device for corresponding csi channel pads */ struct tegra_csi_channel { struct list_head list; @@ -65,6 +66,7 @@ struct tegra_csi_channel { unsigned int framerate; unsigned int h_blank; unsigned int v_blank; + struct tegra_mipi_device *mipi; }; /** diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 29a172f..7547295 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -191,6 +191,7 @@ tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan) static int tegra_channel_enable_stream(struct tegra_vi_channel *chan) { struct v4l2_subdev *csi_subdev, *src_subdev; + struct tegra_csi_channel *csi_chan; int ret; /* @@ -206,14 +207,33 @@ static int tegra_channel_enable_stream(struct tegra_vi_channel *chan) if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) return 0; + csi_chan = v4l2_get_subdevdata(csi_subdev); + /* + * TRM has incorrectly documented to wait for done status from + * calibration logic after CSI interface power on. + * As per the design, calibration results are latched and applied + * to the pads only when the link is in LP11 state which will happen + * during the sensor stream-on. + * CSI subdev stream-on triggers start of MIPI pads calibration. + * Wait for calibration to finish here after sensor subdev stream-on + * and in case of sensor stream-on failure, cancel the calibration. + */ src_subdev = tegra_channel_get_remote_source_subdev(chan); ret = v4l2_subdev_call(src_subdev, video, s_stream, true); - if (ret < 0 && ret != -ENOIOCTLCMD) { - v4l2_subdev_call(csi_subdev, video, s_stream, false); - return ret; - } + if (ret < 0 && ret != -ENOIOCTLCMD) + goto err_disable_csi_stream; + + ret = tegra_mipi_finish_calibration(csi_chan->mipi); + if (ret < 0) + dev_warn(csi_chan->csi->dev, + "MIPI calibration failed: %d\n", ret); return 0; + +err_disable_csi_stream: + tegra_mipi_cancel_calibration(csi_chan->mipi); + v4l2_subdev_call(csi_subdev, video, s_stream, false); + return ret; } static int tegra_channel_disable_stream(struct tegra_vi_channel *chan) From patchwork Mon Aug 3 15:42:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D02BBC433DF for ; Mon, 3 Aug 2020 15:43:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA66D2072A for ; Mon, 3 Aug 2020 15:43:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="PG4hxvt/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728219AbgHCPmy (ORCPT ); Mon, 3 Aug 2020 11:42:54 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:5022 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728060AbgHCPmh (ORCPT ); Mon, 3 Aug 2020 11:42:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 08:41:48 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 08:42:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Aug 2020 08:42:37 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 3 Aug 2020 15:42:36 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 3 Aug 2020 15:42:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 03 Aug 2020 08:42:36 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v8 10/10] media: tegra-video: Compute settle times based on the clock rate Date: Mon, 3 Aug 2020 08:42:26 -0700 Message-ID: <1596469346-937-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596469308; bh=roUn4OftC01Up9y6dlWJXGmDtepFSh32F4qmSVfXZBY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=PG4hxvt/r6JYxOH7qwbfUR55E0zVB/0XV4jQK5z5DvTXcfFgzctqvOa0VgQkTjuT0 FAJTCVxBrkXP2T/ocrTNMKF3MDCLjlbXo4HaskvkftWJze7t+CuE5X6YayWpfaDeSm olrYG2RRkDQbybIRhRVFMOVEkNHAcvD1YChAy+ZlZSlknDz+Zmd4ADN5keDuZAc/3K 84rHc3vNwblwI4kOlmz/RuFcey5T2xxcBUzHZIr90/7rq+5UmBkTocCuafoCumPiQY ViO2Ww5toR53FeJn0xTkrfcOrPM8w6Jg/EcTOWxLYbGZJYUGk2XwPQsKECh1wnSa0x ROhd3Lpz/KAnA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Settle time determines the number of cil clock cyles to wait after LP00 when moving from LP to HS. This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil clock rate and pixel rate from the sensor and programs them during streaming. T-CLK-SETTLE time is the interval during which receiver will ignore any HS transitions on clock lane starting from the beginning of T-CLK-PREPARE. T-HS-SETTLE time is the interval during which recevier will ignore any HS transitions on data lane starting from the beginning of T-HS-PREPARE. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/TODO | 1 - drivers/staging/media/tegra-video/csi.c | 55 ++++++++++++++++++++++++++++ drivers/staging/media/tegra-video/csi.h | 5 +++ drivers/staging/media/tegra-video/tegra210.c | 17 ++++++++- 4 files changed, 75 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/tegra-video/TODO b/drivers/staging/media/tegra-video/TODO index 98d3c7d..c821081 100644 --- a/drivers/staging/media/tegra-video/TODO +++ b/drivers/staging/media/tegra-video/TODO @@ -1,5 +1,4 @@ TODO list -* Add MIPI clock Settle time computation based on the data rate. * Add support for Ganged mode. * Add RAW10 packed video format support to Tegra210 video formats. * Add support for suspend and resume. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 76b4311..93875cb 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -19,6 +19,8 @@ #include "csi.h" #include "video.h" +#define MHZ 1000000 + static inline struct tegra_csi * host1x_client_to_csi(struct host1x_client *client) { @@ -235,6 +237,59 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } +static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) +{ + struct tegra_vi_channel *chan; + struct v4l2_subdev *src_subdev; + struct v4l2_ctrl *ctrl; + + chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); + if (ctrl) + return v4l2_ctrl_g_ctrl_int64(ctrl); + + return 0; +} + +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time) +{ + struct tegra_csi *csi = csi_chan->csi; + unsigned int cil_clk_mhz; + unsigned int pix_clk_mhz; + int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + + cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; + pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; + + /* + * CLK Settle time is the interval during which HS receiver should + * ignore any clock lane HS transitions, starting from the beginning + * of T-CLK-PREPARE. + * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns + * + * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns + * midpoint = 197.5 ns + */ + *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; + + /* + * THS Settle time is the interval during which HS receiver should + * ignore any data lane HS transitions, starting from the beginning + * of THS-PREPARE. + * + * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI + * and 145ns+10UI. + * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI + * midpoint = 115ns + 8UI + */ + if (pix_clk_mhz) + *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz + / (2 * pix_clk_mhz) - 5000) / 1000; +} + static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 0d50fc3..c65ff73 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -51,6 +51,7 @@ struct tegra_csi; * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format * @mipi: mipi device for corresponding csi channel pads + * @pixel_rate: active pixel rate from the sensor on this channel */ struct tegra_csi_channel { struct list_head list; @@ -67,6 +68,7 @@ struct tegra_csi_channel { unsigned int h_blank; unsigned int v_blank; struct tegra_mipi_device *mipi; + unsigned int pixel_rate; }; /** @@ -147,4 +149,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; #endif void tegra_csi_error_recover(struct v4l2_subdev *subdev); +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 253bf33..ac066c0 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -7,6 +7,7 @@ * This source file contains Tegra210 supported video formats, * VI and CSI SoC specific data, operations and registers accessors. */ +#include #include #include #include @@ -98,6 +99,8 @@ #define BRICK_CLOCK_B_4X (0x2 << 16) #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 +#define CLK_SETTLE_MASK GENMASK(13, 8) +#define THS_SETTLE_MASK GENMASK(5, 0) #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c #define TEGRA_CSI_CIL_STATUS 0x010 #define TEGRA_CSI_CILX_STATUS 0x014 @@ -770,8 +773,14 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) { struct tegra_csi *csi = csi_chan->csi; unsigned int portno = csi_chan->csi_port_num; + u8 clk_settle_time = 0; + u8 ths_settle_time = 10; u32 val; + if (!csi_chan->pg_mode) + tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + &ths_settle_time); + csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); /* clean up status */ @@ -782,7 +791,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) /* CIL PHY registers setup */ cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); - cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); /* * The CSI unit provides for connection of up to six cameras in @@ -801,7 +812,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) BRICK_CLOCK_A_4X); cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); - cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); } else {