From patchwork Wed Oct 18 12:58:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116294 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp6035526qgn; Wed, 18 Oct 2017 05:59:29 -0700 (PDT) X-Received: by 10.84.218.79 with SMTP id f15mr15030103plm.145.1508331569505; Wed, 18 Oct 2017 05:59:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508331569; cv=none; d=google.com; s=arc-20160816; b=0MHiiuQBnACO0puNmyS+v/Ph3m/0Uiy6K3429Q3m5vQ3wde56RYKwF65DD1kjMldVr 3ZeyiiebkUuRhTcfSt9AybCfy12cw+Xcrz3pEODR/Efa/laOw3cIhPCisq/1e/DvRcPs zmyp8O5SN8D7cIES6emFcTj7RsbO7JIiHfwzp0VzVl3UHWSZy7jOkd1XhPHURPJWbToJ z8/mybki1umxvGY+rvNgS2C2kNiTOAxMlKwPJ+MQ81t0agtOwLltqDXib00BXU6t9tjy E1EX1JKzWCNGQwk81sCZL3GNWnCKAeaaTVcarcG3VMgWlb1j9KH2y73vYaO54+Yr6F1+ RoZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=H+pJc4RGt6CV0ok8rvOE0E/DXt8/UQd5YBdF/oAwdE4=; b=ikjvjTQDCOclJzIVKFuIxhvRP0HEn9fy04FWAi4H9GscKVvN6Bd4zkDM+9/vyVwIwr qXSeMSyjaI2QoKu6O8R9J3fhmOX0HRROQp2P+EPS5POKPP+SPesYWVJ+gixCXjdPZ5Lu Oku705N6EsQaJcXvfsIR7EQb46s0tFaXbg2lNBxcqoEjHGQYrrKdJk38+RAPA5l0xHV3 5mjA+3LjpBmR8QCOZlNWnwo/ivWrF67NA7fu5Q14dSJkm6O5xOE0KNX6sSzLy8PzEABx qRWzBDyDR857EUWYI3GGVZoi2s8km0O39diLly+6ykA3wf/ZYieC1zmNrNMV1w/HLO3I fVUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jpb0nWAM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x1si2755909pff.566.2017.10.18.05.59.29; Wed, 18 Oct 2017 05:59:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jpb0nWAM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752540AbdJRM71 (ORCPT + 6 others); Wed, 18 Oct 2017 08:59:27 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:48009 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752368AbdJRM6k (ORCPT ); Wed, 18 Oct 2017 08:58:40 -0400 Received: by mail-wr0-f195.google.com with SMTP id y39so4935020wrd.4 for ; Wed, 18 Oct 2017 05:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dz0D++f5CTxWW+vKs5vINIqQ5xCBJX7Tlg618+Xjh+8=; b=jpb0nWAMxBtnn7P4UjtnE9Mc+sP1S8AVvd0hzJxjg0W7LI4MvyJLoeSi2xJeCxYxZ5 4EkyL2BYFtQpjn8YbYAHJ+UTpkA5T1mQjxeRN2xbefWWRkFzjd7dc5XZqc0E93qdmPl0 a9z4SsDp7DbwEHGZQ7JykvEFKrUH02AceXsLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dz0D++f5CTxWW+vKs5vINIqQ5xCBJX7Tlg618+Xjh+8=; b=leo0dn7T4o0SeK2LCmoomQkTyWs0aTd2gS7NCx1f/e3YmUxGtspKC1KvdqyZ1hgFOY L4C3JlaX58/BzxtYcf1qNNg/7pIb6OxheRAmxNsMesyb1GtmZJPddZWEXf8Wmp+1vuTc c2sAki4wrMA6oRPNu9PLElruOGPygw8Bkw2yn5OLIFy5TmFeDRWMbm3ZRcl/UC2wnjIH AAY+gi/w8Rs24ls2ZRW3TrT9+pYDEJ0z8BLIsCiZDu+xClD/Wt/FnH7ISabnTSSfMEA+ AX4VwmkIpJEGDc6qrkJ5wZJqoScIhOuKpaGV7UTWQEMTk3zY0Rsg3HdD0OFsatH/g7fS 5iRA== X-Gm-Message-State: AMCzsaUqmTYyWL/FqseSCxil6XRbGbCoZ6Qusqw8sAga0jetiL2p8JyC iqh6759EKeECnfk4vBTFMQfZfg== X-Google-Smtp-Source: ABhQp+TctQGmSosa0XDtPZTOBXXmvgWLtqZHpSIPrW9W359aVC53jYoSzSK8hixgRI05u7MZcXAvdg== X-Received: by 10.223.154.180 with SMTP id a49mr1463040wrc.96.1508331519087; Wed, 18 Oct 2017 05:58:39 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:38 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 2/5] clocksource: stm32: convert driver to timer_of Date: Wed, 18 Oct 2017 14:58:23 +0200 Message-Id: <1508331506-23782-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert driver to use timer_of helpers. This allow to remove custom proprietary structure. Increase min delta value because if it is too small it could generate too much interrupts and the system will not be able to catch them all. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 160 ++++++++++++++------------------------ 2 files changed, 58 insertions(+), 103 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cc60620..755c0cc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -289,6 +289,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..67dcf48 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -17,6 +17,8 @@ #include #include +#include "timer-of.h" + #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 @@ -34,117 +36,84 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, base + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static int __init stm32_clockevent_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); + unsigned long max_delta; + int ret, bits, prescaler = 1; + struct timer_of *to; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; + to->clkevt.rating = 200; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; + + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; bits = 32; @@ -152,38 +121,23 @@ static int __init stm32_clockevent_init(struct device_node *np) prescaler = 1024; bits = 16; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_period(to), 0x60, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + node, bits); - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: +err: + kfree(to); return ret; } From patchwork Wed Oct 18 12:58:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116293 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp6035500qgn; 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[209.132.180.67]) by mx.google.com with ESMTP id x1si2755909pff.566.2017.10.18.05.59.28; Wed, 18 Oct 2017 05:59:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eGV+X/YR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752499AbdJRM70 (ORCPT + 6 others); Wed, 18 Oct 2017 08:59:26 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:54449 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752434AbdJRM6r (ORCPT ); Wed, 18 Oct 2017 08:58:47 -0400 Received: by mail-wr0-f193.google.com with SMTP id o44so4917444wrf.11 for ; Wed, 18 Oct 2017 05:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=eGV+X/YRusgMqunTfs2dWDH8KpzKITHYO7eSp8ujkQI1uZWBYBQiiYS2j6mlQCITAt eyX0AIUhzkZOEih6aMuQF/DXsBOg14z+0/wRe2fLuYoefa6TlFrUe5sTMLwl0xeXfvBD T1z5f+M/HH7qesfM08uiJAjyw2rprNwI7HkTU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=jO/PUm/lP5AKcTVd7g7jUgjFzNRDxEo25lrwyKMIweFH17ncEII8Y3TSqAMC1SYEqh ALpwVDgjMUJEvx1ZtjUNWUKux5AC/dTtcjBidWa9Ks4SMqP3YCw+cyykB0nrUBr4zDkB 0kYT7pHFaXNrBwkDp1dVzPLjqg7QHrYmDMd69koDY58bZDsSQuieqqv5R9McFulpQGH9 9OGXTju2KtQIlwEbr+6c2VAHnUquPTybbMOxvfXc6LTCUyZM7V1dOuKLR3Ia4BVEQevh Fwgmy9evT9D2zOylrS/Ec6MxteGnemJiegGGr1ArvglfAxTpfUbNUeRt2s+8BReRzsJH VFmw== X-Gm-Message-State: AMCzsaWvIAMHwGBHgUI1Bmp1dRdWjsP6YwTKUzqLK0+pN8GAFkWM2yCW STImBEsrM3IXahKx54sr9f8QZQ== X-Google-Smtp-Source: ABhQp+RWhRBlVLU9lFL01emym+fL+JrfuLntIl0+p8i9I/tC+7RkzQGH2bcNRdCBHQd7UmtKgdKclA== X-Received: by 10.223.143.66 with SMTP id p60mr7287876wrb.142.1508331526482; Wed, 18 Oct 2017 05:58:46 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:45 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 5/5] arm: dts: stm32: remove useless clocksource nodes Date: Wed, 18 Oct 2017 14:58:26 +0200 Message-Id: <1508331506-23782-6-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index dd7e99b..ac9a3e6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5633860..a9077e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;