From patchwork Wed Oct 18 12:58:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116291 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp6034896qgn; Wed, 18 Oct 2017 05:58:47 -0700 (PDT) X-Received: by 10.99.52.194 with SMTP id b185mr13546337pga.170.1508331527237; Wed, 18 Oct 2017 05:58:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508331527; cv=none; d=google.com; s=arc-20160816; b=GOO21dfH1ei1z9eIt+mHRLhRCvpuq4pG+inqA+ka/wG9jYro4gtr5PbW/pw/5nnbbt +HraZqCI1iIYMfPHNuFX2N1ydSvczRED/3vaqOfKb/OjIxOmsGvn7+RC+iPyPqWmS+rO VR5AhTb6bRCB2YV7F6mUlLGEI1skrzKBPG39LQaKA+BfxqtQ+UgHwHmQA4qdPM6RFVWA Qm2MCEn8A2V4lA4JCrSPuvIst/v695JNCx53nkj/Rig7tRKDxnacACz4WfNIRtmRxeft tLrru7XqvUfC9TMltgj0ai/3zbK+kLOWhG/OhGos6Tx5yeKVryMRvGe/3GfMG6x6B+0x B1XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=od9nt3TZLoey7ZnzBpSvV/zjEzuYhIahtFPf0ZLNM/8=; b=Woi9SIrJpGc2ApPfeMrpiO9tjlwYTnOssx3hLnc3HZ0Sx4uBr6pekJq80h6cbEL/M7 YsVEEbhlGVkzASMcbgR8fsaMM0Sh31H6Una6AJ9SvYaSlFTkxCCIFIBuiGhM9T38ISUz FPaOjPeQzMGy9N/VhMpv0cZwJC8dVr0OzYhkCsGiYOKpCBtONHmTB8I48mFVR8+UOgOc zCJXS7bsaBtRb8pHx9aH1mHP6dm70LGDw0xw+kk8vm6CzN7YNYUtCo56wu16hZ+4VIF1 4T6WdMLZC2IHWtqlDJDB0DbfB2b9gJzK5geIBU3M30ODvoKOkEzwd9IBNRwncSzxMqlg klpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yk2fLTl8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n1si6914790pge.830.2017.10.18.05.58.46; Wed, 18 Oct 2017 05:58:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yk2fLTl8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752409AbdJRM6l (ORCPT + 27 others); Wed, 18 Oct 2017 08:58:41 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:48002 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752347AbdJRM6h (ORCPT ); Wed, 18 Oct 2017 08:58:37 -0400 Received: by mail-wr0-f195.google.com with SMTP id y39so4934848wrd.4 for ; Wed, 18 Oct 2017 05:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=od9nt3TZLoey7ZnzBpSvV/zjEzuYhIahtFPf0ZLNM/8=; b=Yk2fLTl8DVe7AQTsHJyPvTGaHtEdmCz99T1LdfCU+68FtnLQ8yBbdtX58gf+gEqCkN 9QWPSrNr55MbeVV9afnT2P21QIW5YzfBZ6awNEqnJiVtppKIxxTzqJXy89oJ8pUAzcXd EMXhBI/jzMlWlAm46H2WkpYIVModf7Tt8VD9c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=od9nt3TZLoey7ZnzBpSvV/zjEzuYhIahtFPf0ZLNM/8=; b=bHjBNP9lQYoGekFISR/DsepGu4aZ8HLzKNp/H+x3dnAvrFlGEoqTp4RXHMHydTqLyi 4SWP1SQFm++AN2WYmjtePaWnVgcjUrrpjCxV4P4mHkXzLOfwyJfnh/ldn6vhdZtqik3M UzqgXrl5SmeOnuz92zM3alb1LP02ZqbKZ6YrNOP5hKatRNRdG9vz56JJnw3jsMlxslyr itBlb1bUD/FVVC9slCgvKOUlLKHiBWXu0v1h5hjswGM5zy24+II0vsnySpO8cC6hkK8e UpaOPMQVXgO1O/3vdCLPg61RZYNgoM3HT3NIW3i0TKDacQoqz4QjJv3JGPtvFWH4/jQL YJbw== X-Gm-Message-State: AMCzsaXQG7Ey+JSFyN4SfyeiSf5RRkKdkzehDMmBdVpyxlCk+084WqeL suxasHUe9Tqv/AVqF9fhHE6X6w== X-Google-Smtp-Source: ABhQp+QnLD7eofUJmN1KBhpctrkMnQefYodERPwfuUHtwNjkXlKes/nAwc7A/SUxedDvpSuJ7t4oJA== X-Received: by 10.223.128.3 with SMTP id 3mr6275553wrk.196.1508331516459; Wed, 18 Oct 2017 05:58:36 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:35 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 1/5] timer: add timer_of_deinit function Date: Wed, 18 Oct 2017 14:58:22 +0200 Message-Id: <1508331506-23782-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add this deinit function to be able to undo what have been done in timer_of_init(). Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-of.c | 12 ++++++++++++ drivers/clocksource/timer-of.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index c79122d..14404a0 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -176,3 +176,15 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) timer_base_exit(&to->of_base); return ret; } + +void timer_of_deinit(struct timer_of *to) +{ + if (to->flags & TIMER_OF_IRQ) + timer_irq_exit(&to->of_irq); + + if (to->flags & TIMER_OF_CLOCK) + timer_clk_exit(&to->of_clk); + + if (to->flags & TIMER_OF_BASE) + timer_base_exit(&to->of_base); +} diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index e0d7272..3833ab1 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -66,4 +66,7 @@ static inline unsigned long timer_of_period(struct timer_of *to) extern int __init timer_of_init(struct device_node *np, struct timer_of *to); + +extern void timer_of_deinit(struct timer_of *to); + #endif From patchwork Wed Oct 18 12:58:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116292 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp6035055qgn; Wed, 18 Oct 2017 05:58:57 -0700 (PDT) X-Received: by 10.98.75.77 with SMTP id y74mr11057942pfa.78.1508331537757; Wed, 18 Oct 2017 05:58:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508331537; cv=none; d=google.com; s=arc-20160816; b=DpAHgxXG/h6XFirJxeZMTS11BIU8GUCzbahX1+T1sO/LCMAM06V/h98sSZggwfOFnl bMki+My1ha+Vftotu9zELCaP7iYdLFf4WvVVwUA0ACOLYm8K3g+oVFIL7T+ObjJLRZOY L91X9WJ1d01sCoVLturys2eqcBYAgeCcEXNs1IFnIa5zITWNASXjZ2tihwwyD/oZXavm EVyr3/vKQi5sOL4DT62spvREQnrxw6yLUf5VGwRsChDwgDsu2cih8t3R7RFEwv+oC7kj P6ShSpOKRNgC6AE03x8WtpJPFjj3dnjki4OqazItZ6cCRT00O/eQGu/bk4oPcbU8FI4l CdpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kxSAjGL/a34TNgfjLAncz+CWDVEX3RnZVjD4dYHs6uY=; b=BlXnEUXDmNz9FTOb1QWDPsPTHWg/+7N8x0K8Wkvqb2HZN0elp7ryiJ5Fe+VE/o/UHH h6db86GxQ0M3NnTKunHnrT6KNysZGLp1jQI67rPdFZkJ4uLnI6vZf3DuggcQcUWR8MGH Ok3ysBTKISpOCbdCAnuW8hZTyheeFAZyjkRlB9jpP5LNoxXrriU1XT018Io/1L3zKOA7 CwB43HMB8GRMR5145zh+Q2CZhsD4lqSi34Fcxi+wtwQjazVbMtRRmIwEnZqt5Wvkdagh 3Gr3oJUwTVHTi4TuQ5YQGcxAu8JkNhgePpCCefUM3p/fhZBjG3SOMbl6nZ8B1uLb5HlV CS7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSC7llOi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n1si6914790pge.830.2017.10.18.05.58.57; Wed, 18 Oct 2017 05:58:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSC7llOi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdJRM6x (ORCPT + 27 others); Wed, 18 Oct 2017 08:58:53 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44529 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752365AbdJRM6m (ORCPT ); Wed, 18 Oct 2017 08:58:42 -0400 Received: by mail-wr0-f193.google.com with SMTP id l24so4935027wre.1 for ; Wed, 18 Oct 2017 05:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kxSAjGL/a34TNgfjLAncz+CWDVEX3RnZVjD4dYHs6uY=; b=CSC7llOi+CSDuvI0eDkuyYgJvqEHxa5VFcAJ16okMfkclPLjJAd3ScfZesQU8/S7/E e1miExDxX90kpNHUrpdJMpZGr7fBfjFYkFLsXws9MwVvcIZTfTXUo5cStz3zJ1lyNsiB Sbr44Ga3s2z6S1+C8wr48SDu3fsEuYtVBZuIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kxSAjGL/a34TNgfjLAncz+CWDVEX3RnZVjD4dYHs6uY=; b=p5SBc012ej21xJxJp/13ga7BhuKU/q7+fO3E4gzLSEBt9mTtSxC5uTO5IqAmmKbP3z bE4btosO4+mQDMLhCBur7Zf7viCtjH82pMP99HHs4iTVi7kLMdgZPw2BCX+oEH3GE2Er hU/RSV++5cn682Hx+6zYbyJL9UXUdIfrBvwqZe0PYjjBleZdlhalmZ5idO3MjXYxDq/U DbphTj3iZtR+LdBkhUNIPwOi2RTSsaj9nHyfIxs5us4v+G4ljThMP19NWcQOTTzuqkMi 4Ilen0Yc6tz6w7cXATl0rMHGMfEXqECArwpUW9YEw5x/9/zY9wfXygetZzTQj+QLP5TT B81w== X-Gm-Message-State: AMCzsaWSdwxYORZeETIYviNVMnRAphUBbFthhI2Szv16Bavb4wpHJY8h ItquiUq5tdy+uf/EG16iksKP/Q== X-Google-Smtp-Source: ABhQp+RAyW47WVG6h4B6M7+mzJef8uPRDsNJy9U2hXALlcd5WA+HVDx6IQU2449tgnb7JK8d96+qtg== X-Received: by 10.223.195.110 with SMTP id e43mr6342802wrg.219.1508331521655; Wed, 18 Oct 2017 05:58:41 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:41 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 3/5] clocksource: stm32: only use 32 bits timers Date: Wed, 18 Oct 2017 14:58:24 +0200 Message-Id: <1508331506-23782-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 16 bits hardware are not enough accure to be used. Do no allow them to be probed by tested max counter value. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 67dcf48..c834648 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -81,9 +81,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -113,29 +113,27 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + ret = -EINVAL; + goto deinit; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), 0x60, ~0U); return 0; +deinit: + timer_of_deinit(to); err: kfree(to); return ret; From patchwork Wed Oct 18 12:58:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116295 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp6036630qgn; Wed, 18 Oct 2017 06:00:31 -0700 (PDT) X-Received: by 10.84.195.3 with SMTP id i3mr3976080pld.322.1508331631435; Wed, 18 Oct 2017 06:00:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508331631; cv=none; d=google.com; s=arc-20160816; b=glJdtET7mBkovq33agIcXjlf3fpnefQr2i2KZNmqg0Qto65xD33SIMzirjl6kouO/g tLZnA0KdW4GvZKsS6oDYfljx1RThsZKoQUNoaFHY/OOw+4aXVw94BQXjUo/O1U9Fwiwh NtQ0OqFaMdWxpXAs2E8DGAakCzT4nacRDUp47eKcG/Uooj0Qoj6CKUYFImNXDF2jexiB KTftrwYQdgOPYtmQQFFXCki+txvXN8jTarNs1eHvAsqXTmtNv+YvZC0C1pVVQXlDy6Ns hq/o3+wrr7MSQftkq1KPDgmV8OyV6y+mf+If+Wnk9d+GsKOvx61d0Ix/nTY+zLhDHNwp exow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b2ZXBCMGXDODfkEbKoIUO/eZxRKwIRuUa2KAQO4UfHU=; b=QZ6h8UkiK+VlSi35Ss7Znhe7sNa3Nd6Do0wjr6X80V0hqxl2y6GZ31ijsKBFBVWJ3W DUxLeaZc+36/Wyck5tHX5zKksMZFM54tkCuPSQxyP2tW6QtlnGDrzEDEwIJI8orlwfcj hReLtJaKGbSIaAFpJNZpTvgls3npgK7GzOHzcCbaGywKzvGpyPHsEt7GqollWqH04NEQ vWbwdGy0+v4AJ6qepsZxfU+vp+HkP4Bh+Xe0cXDPnI5fX1vTXGDHDX5nQHEGfsiaNpn7 Z0orsHTiqobxXamIXqbbirwi36/8tMQS1feaO5UW3EFidH4TD/uhGDi7pRrkEku2fAjE wKtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FnLkGsNl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s19si6879551pgn.150.2017.10.18.06.00.31; Wed, 18 Oct 2017 06:00:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FnLkGsNl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752590AbdJRM73 (ORCPT + 27 others); Wed, 18 Oct 2017 08:59:29 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:43984 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752427AbdJRM6r (ORCPT ); Wed, 18 Oct 2017 08:58:47 -0400 Received: by mail-wr0-f195.google.com with SMTP id p46so4931512wrb.0 for ; Wed, 18 Oct 2017 05:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b2ZXBCMGXDODfkEbKoIUO/eZxRKwIRuUa2KAQO4UfHU=; b=FnLkGsNlYoDQARIJi5cfHxoOQ/T9khwtP9QtPLgAoDQW+jaVs5FCkoZZU6cGFFmSbH JaQ+yuvv2jsdBKBljtFQW/jS53HTOsFwQQc6GR8QxH6spL4WnRIwDw/7V5PX2B1kuqtU XnxgAtFJBXWR1/IIMwgNRkKP1Aibx4PPa573c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b2ZXBCMGXDODfkEbKoIUO/eZxRKwIRuUa2KAQO4UfHU=; b=CcrL9c8byyk7z1SZZBNZAycQZnBxuawNu88/f9azVmHPqU1Uq2vzmks94usK17AQgn EUPWASjOVkeD5S0zOhigZDarH1etHXTUMWw2Qqlxa/2WhE+k7ijOg5/O70wZva692nLS n+9HoP8LkxfWAMY1fzRAJ+Aw/h79r41NzaHUxz3U6e2lflxWujozfRs2Ep7q5vSBtfTB RupB+0ZsrEonrQL6Nwsv/1wjlasaSFJ25Ygippl8WZ2nrQeRCaEkPd13E2+QhMF1RXFy mzGj3XEN4s4c1NSAXpe4xw0+Linlwxy4NOaAvfo38j/6iyXBi/d1oUa4sJ2PsQ89LSLO tJWQ== X-Gm-Message-State: AMCzsaX8OjtOZXVdWv9CVWlzMQj3Wagt6SDKMJ81WiWKcYGCvy+8HurV 1OkH+DiR4Yo5rlh20LS8IpdksA== X-Google-Smtp-Source: ABhQp+TPxG9sKqUpPwkgS61l3I1WAaMdupYO63BPFXurA0jb3iKraxB2A2RHHpfEzJaOy8Sx4mQYxg== X-Received: by 10.223.165.19 with SMTP id i19mr7207843wrb.151.1508331524211; Wed, 18 Oct 2017 05:58:44 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.70.168]) by smtp.gmail.com with ESMTPSA id m23sm14169908wrm.75.2017.10.18.05.58.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 05:58:43 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v6 4/5] clocksource: stm32: add clocksource support Date: Wed, 18 Oct 2017 14:58:25 +0200 Message-Id: <1508331506-23782-5-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508331506-23782-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework driver code to be able to implement clocksource and clockevent on the same hardware block. Before this patch only the counter of the hardware block was used to generate clock events. Now counter will be used to provide a 32 bits clock source and a comparator will provide clock events. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 104 ++++++++++++++++++++++++++++---------- 1 file changed, 76 insertions(+), 28 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index c834648..461b3ba 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -40,30 +42,34 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long cnt; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + cnt = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(cnt + evt, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} - return 0; +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + return stm32_clock_event_set_next_event(0, evt); } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) @@ -73,12 +79,57 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x60, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long max_arr; @@ -90,12 +141,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -120,15 +172,11 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, ~0U); + stm32_clockevent_init(to); return 0; @@ -139,4 +187,4 @@ static int __init stm32_clockevent_init(struct device_node *node) return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);