From patchwork Wed Sep 30 10:51:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 255545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBFDBC47427 for ; Wed, 30 Sep 2020 10:51:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 816A62076E for ; Wed, 30 Sep 2020 10:51:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=temperror (0-bit key) header.d=phytec.de header.i=@phytec.de header.b="c78Wx227" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729617AbgI3Kvp (ORCPT ); Wed, 30 Sep 2020 06:51:45 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:58446 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729205AbgI3Kvp (ORCPT ); Wed, 30 Sep 2020 06:51:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1601463099; x=1604055099; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=dzg7oLQPWCGjeAIksjtJZdy7ElG4yvKdUuApBlBIjbg=; b=c78Wx227XDwx+Z777O6T43ECjiHQtO+Cjxw2YJWXsVMi6+MWGUnA6OoNLUPM5FG2 RBsSHepIYKGN4U+5HnZcT8w/8/9VHzTOEV7awSaBNXYudCK2FRC/2K5oXAPnOV9f B3p2s7tocVT98iDi33jQKqVGRJHKi82ljqeqwI7hvPk=; X-AuditID: c39127d2-269ff70000001c25-d0-5f74633b52a9 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 0E.89.07205.B33647F5; Wed, 30 Sep 2020 12:51:39 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020093012513957-526322 ; Wed, 30 Sep 2020 12:51:39 +0200 From: Stefan Riedmueller To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Sakari Ailus , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Enrico Scholz , Stefan Riedmueller Subject: [PATCH v2 2/5] media: mt9p031: Read back the real clock rate Date: Wed, 30 Sep 2020 12:51:30 +0200 Message-Id: <20200930105133.139981-2-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200930105133.139981-1-s.riedmueller@phytec.de> References: <20200930105133.139981-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 30.09.2020 12:51:39, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 30.09.2020 12:51:39 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGLMWRmVeSWpSXmKPExsWyRoCBS9c6uSTeYFGnqcXeYxdYLDonLmG3 uLxrDptFz4atrBbLNv1hsvi05RuTA5vH7I6ZrB6bVnWyecw7GeixYuV/Jo/Pm+QCWKO4bFJS czLLUov07RK4Mk52cBRM4694tfs/UwPjLZ4uRg4OCQETiSc7lLoYOTmEBLYxSnz6E93FyAVk X2OUWPbqMgtIgk3ASGLBtEYmEFtEwEKid9F0RhCbWeAro8S6s9kgtrCAq0R/xzFmEJtFQFXi 5J5pbCA2r4CtxIxjv1lBbAkBeYmZl76zg9icAnYSp+//YgW5QQio5uLkLIhyQYmTM5+wgNwg IXCFUeLCxhVQvUISpxefZYbYqy2xbOFr5gmMArOQ9MxCklrAyLSKUSg3Mzk7tSgzW68go7Ik NVkvJXUTIzBsD09Uv7SDsW+OxyFGJg7GQ4wSHMxKIryHEkvihXhTEiurUovy44tKc1KLDzFK c7AoifNu4C0JExJITyxJzU5NLUgtgskycXBKNTDGyXVyGnc/0Do57YLIHo5Jm3qNymen/imY 1j577sbr+zcKhdZt2j63+EHKl7bkPR78bgEZJ1zFthQee+Rc9OtWHXdIo7NzRFQdV9/xyVMs F6tMY1xk/9Lt9NniVyHx50xvGinlrK1Y8rNoca7jjSC9tZsfbSiI/p4+QTvozYPtP78y/att WVGtxFKckWioxVxUnAgA9L/RdUkCAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Enrico Scholz The real and requested clock can differ and because it is used to calculate PLL values, the real clock rate should be read. Signed-off-by: Enrico Scholz Signed-off-by: Stefan Riedmueller Reviewed-by: Laurent Pinchart --- No changes in v2 --- drivers/media/i2c/mt9p031.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 2e6671ef877c..b4c042f418c1 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -255,6 +255,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + unsigned long ext_freq; int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); @@ -265,13 +266,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ext_freq = clk_get_rate(mt9p031->clk); + /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. */ - if (pdata->ext_freq > limits.ext_clock_max) { + if (ext_freq > limits.ext_clock_max) { unsigned int div; - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); div = roundup_pow_of_two(div) / 2; mt9p031->clk_div = min_t(unsigned int, div, 64); @@ -280,7 +283,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } - mt9p031->pll.ext_clock = pdata->ext_freq; + mt9p031->pll.ext_clock = ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true; From patchwork Wed Sep 30 10:51:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 255544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BAE6C4727E for ; Wed, 30 Sep 2020 10:52:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C43D92074B for ; Wed, 30 Sep 2020 10:51:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=temperror (0-bit key) header.d=phytec.de header.i=@phytec.de header.b="T/ZxTko4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729304AbgI3Kv7 (ORCPT ); Wed, 30 Sep 2020 06:51:59 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:58446 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729643AbgI3Kv4 (ORCPT ); Wed, 30 Sep 2020 06:51:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1601463114; x=1604055114; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=8Ne0Cho+Zmb2A9HZaNjT+Nce0O3XMfwK2n40tLuNhBo=; b=T/ZxTko4U9TO4DTF93T7JZ6IDG6lcDrC+hAZXTZ0kCg+859hv3NDR+oV6EhsLk+k LpaIiY7OPHNwSBY+TXQmM/XYA1sH58JPieHrD10gHOzRioH/lWe1ONZmhUFNrpyl cmeA2hUb7pRw01ZXzPpzjx/9NGfI/3GMiFNy+Aun/EY=; X-AuditID: c39127d2-253ff70000001c25-d4-5f74634a4d88 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 2F.89.07205.A43647F5; Wed, 30 Sep 2020 12:51:54 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020093012515375-526326 ; Wed, 30 Sep 2020 12:51:53 +0200 From: Stefan Riedmueller To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Sakari Ailus , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Christian Hemp , Stefan Riedmueller Subject: [PATCH v2 4/5] media: mt9p031: Make pixel clock polarity configurable by DT Date: Wed, 30 Sep 2020 12:51:32 +0200 Message-Id: <20200930105133.139981-4-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200930105133.139981-1-s.riedmueller@phytec.de> References: <20200930105133.139981-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 30.09.2020 12:51:53, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 30.09.2020 12:51:54 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsWyRoCBS9cruSTeYMtdFovOiUvYLS7vmsNm 0bNhK6vFsk1/mCw+bfnG5MDqMbtjJqvHplWdbB7zTgZ6fN4kF8ASxWWTkpqTWZZapG+XwJXR euc3a8Eh6Yo1q44yNzAuFu9i5OSQEDCRmH/wMzOILSSwjVHi70z5LkYuIPsao8TJD2vZQRJs AkYSC6Y1MoHYIgIWEr2LpjOCFDELPGeUmLN9FyNIQlggROL3jh5WEJtFQFXifutqNhCbV8BW 4l/rDlaIbfISMy99BxvKKWAncfr+L6A4B9A2W4mLk7MgygUlTs58wgIyX0LgCqPElGvPmSB6 hSROLz4LdimzgLbEsoWvmScwCsxC0jMLSWoBI9MqRqHczOTs1KLMbL2CjMqS1GS9lNRNjMBA PTxR/dIOxr45HocYmTgYDzFKcDArifAeSiyJF+JNSaysSi3Kjy8qzUktPsQozcGiJM67gbck TEggPbEkNTs1tSC1CCbLxMEp1cCYwz3RRKjQfGLR5k1ymutOWKfEtZcGm+oWaU9/+uTCy0S7 S+kzzCa/XHV20SW9hHXyxwvYHtnUKf/7WtnvN7+lwHG5t++i9IlennYXBW8KqQhV3rY/mDRz Sliyw+qjb+6wL99YxPL7kvmRszO5WtadPqL9YCcHq7fVpVVLnBUFv8/2VJw+gbNRiaU4I9FQ i7moOBEA6E/jSkICAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Christian Hemp Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp Signed-off-by: Stefan Riedmueller --- Changes in v2: - Initialise endpoint bus_type field to V4L2_MBUS_PARALLEL since the sensor only supports a parallel interface --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9p031.c | 20 +++++++++++++++++++- include/media/i2c/mt9p031.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c7ba76fee599..7c026daeacf0 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1103,6 +1103,7 @@ config VIDEO_MT9P031 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the Aptina (Micron) mt9p031 5 Mpixel camera. diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index de36025260a8..d10457361e6c 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aptina-pll.h" @@ -399,6 +400,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) return ret; } + /* Configure the pixel clock polarity */ + if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + return v4l2_ctrl_handler_setup(&mt9p031->ctrls); } @@ -1062,8 +1071,11 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { static struct mt9p031_platform_data * mt9p031_get_pdata(struct i2c_client *client) { - struct mt9p031_platform_data *pdata; + struct mt9p031_platform_data *pdata = NULL; struct device_node *np; + struct v4l2_fwnode_endpoint endpoint = { + .bus_type = V4L2_MBUS_PARALLEL + }; if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) return client->dev.platform_data; @@ -1072,6 +1084,9 @@ mt9p031_get_pdata(struct i2c_client *client) if (!np) return NULL; + if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) + goto done; + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) goto done; @@ -1079,6 +1094,9 @@ mt9p031_get_pdata(struct i2c_client *client) of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); + pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + done: of_node_put(np); return pdata; diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h index 7c29c53aa988..f933cd0be8e5 100644 --- a/include/media/i2c/mt9p031.h +++ b/include/media/i2c/mt9p031.h @@ -10,6 +10,7 @@ struct v4l2_subdev; * @target_freq: Pixel clock frequency */ struct mt9p031_platform_data { + unsigned int pixclk_pol:1; int ext_freq; int target_freq; };