From patchwork Wed Oct 18 07:43:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116236 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5771963qgn; Wed, 18 Oct 2017 00:44:32 -0700 (PDT) X-Received: by 10.84.240.6 with SMTP id y6mr12814538plk.78.1508312672276; Wed, 18 Oct 2017 00:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508312672; cv=none; d=google.com; s=arc-20160816; b=R8LLvI6mJSRQyI3IV2K4zgaILgNhKwYoRZZjob9m6rR90u1vHfV0hdlTdxjtlI28b+ z9uZF99ENSrF5HSaXBkdewqd0oh57SKzQPgX6nK3sgxKdeN4tsCwgegdW6I3wtwoQoIM leuemakIPPLT4cWb91wpG0c188iO8ImgZFUt5HInh0/MG2OCACCs93HlRIHdQzop5StC ZJ0LDK9Ef4RGi0TMORnN8LLeLLtK77Pdf43SN6FfEgVpAQtsMUBKm72MDleRR3cMvqbq e2thO+8NgVTB2ZXrj9VSP8Y+w9PCXSqPNKeyaIlt6MEyE89zCLus0/N38/tZrvUo3wRE ImOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=DIsnmKOBRsG/kSECWHAGcIBsh1tQmnm92nfHBvX0Ghk=; b=Qy18PVDBX61CGszGegNAU1PVP6breSS3Z3knBgXxTOve0x1NfQjvKI351P+m8WkVFM wHUfNPM6lOkampeCKwtQuGC3cas8BKgsWb7vqz4qLxLA3+vXcCa2O+17S+kJlZ0fBhsF 6F9kdehIlbdepYB+G7G7qSAZR12hCCx6D+8RR+Af9QD2GgytYpCv4Y/uoQ4Sbom+rQ/m QSW8RX8lavY8jBDkJuxNoqRgUxt6EthzSB6bmCaLX1IPIuRl9dcNxFzhgOtx66qZScek i2YKS2QnssACFbrOq2qgP3tQj59HmwhiV5ORFygu/Eo8j/4QK8d1IXy/yt2nnFV/GXQK C3Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tg+BZ95q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w18si6571656pgq.366.2017.10.18.00.44.32; Wed, 18 Oct 2017 00:44:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tg+BZ95q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762540AbdJRHoG (ORCPT + 27 others); Wed, 18 Oct 2017 03:44:06 -0400 Received: from mail-wr0-f179.google.com ([209.85.128.179]:48894 "EHLO mail-wr0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762471AbdJRHn4 (ORCPT ); Wed, 18 Oct 2017 03:43:56 -0400 Received: by mail-wr0-f179.google.com with SMTP id u5so4014026wrc.5 for ; Wed, 18 Oct 2017 00:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DIsnmKOBRsG/kSECWHAGcIBsh1tQmnm92nfHBvX0Ghk=; b=Tg+BZ95qMS6JWQak8wEf5ybeE29DcjPolrDJSIj6QvMzvbUBriVPl90iXH5zKH02b8 7SIl+w/zAeEIcLXKXc9klkd50slI34dl2w0R9GFOqRH8s7ATsnZsWiglbU+4/TW1SNOW SM0mHKEnns8uIUGdoIstTY6RZAMktnQxSxkEw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DIsnmKOBRsG/kSECWHAGcIBsh1tQmnm92nfHBvX0Ghk=; b=F7x+f9AbiJIsKHg8GVgfuavs+7osQsfB7jCfwrdtCCmhAaJUmj6Wt7enUh6ij27/6R Yj9d1DaGOTz4s2uexbfbCEYPYrKRCT524PQ8HRMkJh86AqECuTIK/pxpuMhLC4Gk5dtN bJ3HFvRZM5pOebK3Paqbo79nN2LCzX9W0EJzKHfCPMME889NTrrAXuwV4AiYCoZy885D bQRZjA20Unz21J0MuCYIobLoQHBoS5A4pxMrZocCxTl70QjwSkE1f2q4Y+2jrfUiPtcN 220ciSG1igJNFzjtAC339No9cwsbm648iEg31sDOrJkG59fU60cYmV94fc/R/wOhX1zH xg7Q== X-Gm-Message-State: AMCzsaW8cGXkyzeLFF/QE9tA+59kiZROMdhBdVnBwpOgiNQqOAzpXyiJ oEu6lZ1oWM5PNXBB2wYSS5PTSA== X-Google-Smtp-Source: ABhQp+QepTgrh/oySXeLi6v+0yZ1CgTkHTJ0UNm7vW4jSLkXvWV/x/HaQtiy+c2JYdAWiEwNvoUU4w== X-Received: by 10.223.182.80 with SMTP id i16mr6539684wre.110.1508312634638; Wed, 18 Oct 2017 00:43:54 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.78.118]) by smtp.gmail.com with ESMTPSA id v78sm7855063wmv.48.2017.10.18.00.43.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 00:43:54 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v5 1/4] clocksource: stm32: convert driver to timer_of Date: Wed, 18 Oct 2017 09:43:31 +0200 Message-Id: <1508312614-27750-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert driver to use timer_of helpers. This allow to remove custom proprietary structure. Increase min delta value because if it is too small it could generate too much interrupts and the system will not be able to catch them all. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 162 +++++++++++++------------------------- 2 files changed, 57 insertions(+), 106 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cc60620..755c0cc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -289,6 +289,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..abff21c 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -17,6 +17,8 @@ #include #include +#include "timer-of.h" + #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 @@ -34,117 +36,84 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, base + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static int __init stm32_clockevent_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); + unsigned long max_delta; + int ret, bits, prescaler = 1; + struct timer_of *to; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; + to->clkevt.rating = 200; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + return ret; + + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; bits = 32; @@ -152,39 +121,20 @@ static int __init stm32_clockevent_init(struct device_node *np) prescaler = 1024; bits = 16; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_period(to), 0x60, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); - - return ret; - -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: - return ret; + node, bits); + + return 0; } TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); From patchwork Wed Oct 18 07:43:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116235 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5771755qgn; Wed, 18 Oct 2017 00:44:10 -0700 (PDT) X-Received: by 10.101.65.75 with SMTP id x11mr12910963pgp.388.1508312650635; Wed, 18 Oct 2017 00:44:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508312650; cv=none; d=google.com; s=arc-20160816; b=YInnYCy9QtiF6Kc3JHJouOusD6+bTmctd8opFWEPWO/I/HlUrMhhMUV9lqt7Qm5nNk 3CsEg+Is8wjriDg4uH67+4l1F0Ng8vzcx/79pXa8qEgADsJ8lNLrK9Lj3US2CsKwaiLg zUJTTekpPyyCs3/V1+yg5rCfMW7TVTaCE9NTdXuhJ4vZIOdHE8F2puRu8+afWLseILcU gvjXBSBG81PTsqFNWlDRMAWROjzQJiUiK9XScEXMT30VaRz/GiVCZwpFoTdFCo4YxDgY /FX8lOJsUggH7WFLSeI4/p0tC6kZuRXZoWHWAl9WsqiFM7OO0//OfV3jIh4BlHYjLX9g h5OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6JH4Hn7ZCjUX0f12s9LItjzS3ACqz7dGI7sGncsOL7o=; b=pUEp6puUwiBB6F/pZ2k8DnXF7/506ibAuISpFp+yZ2qWeN9f+oYqfUGSNnUSW8gyMK 6JCIm4HMJ8G/7eWvrYJ/bw8AzI4ozh0dmdKXrTef+NLRRHTsJHJU/NVj1TPZEdvymxPm SMuMJQP+nlXAjB4jmQEAVDnWOm8qSICIO5Nblslqq5gNFkEjiQRSu/oK9OiU2gkQGZtj POEphgoVYGdjHCinbKSbU5+y6kfYiym3/LVBiEAur/7kpnKoqqK+ZBMxjJqL5UvPdHXs YF+pkUWqAo05/MYSfwSp4SHOGMFq/VsUHqBgiKWl0grncgc0wMjejEIyrCkYhzkPaFYQ yddA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PEJBEgcs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w18si6571656pgq.366.2017.10.18.00.44.10; Wed, 18 Oct 2017 00:44:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PEJBEgcs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966868AbdJRHoI (ORCPT + 27 others); Wed, 18 Oct 2017 03:44:08 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:45802 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935677AbdJRHoA (ORCPT ); Wed, 18 Oct 2017 03:44:00 -0400 Received: by mail-wm0-f53.google.com with SMTP id q124so8152693wmb.0 for ; Wed, 18 Oct 2017 00:43:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6JH4Hn7ZCjUX0f12s9LItjzS3ACqz7dGI7sGncsOL7o=; b=PEJBEgcsBfGD/oSexux4FdLzUiMDIZAVEzyUqCfKZkCjuxCZ69Q90ZJZgctANW0ZQh c2b6KvPkUwpyRnM68mTDMIl+RY5B8JNYG3lCVN/SmamYz602IwomaDLYNRp8fYGBdXfz 4mtUY2iXlM49CguOwV6wcdNV9hYx1I4V1Vxeg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6JH4Hn7ZCjUX0f12s9LItjzS3ACqz7dGI7sGncsOL7o=; b=II8kfgULdvjOJVsZakCt9Qps2ni8p1gk6kwDIg89fvZwfMM8oiDW8jn52cwZzsli+2 M5dqfsL4r0T8yjYN7LBJ/zpRcVGMPQEJEal/zyfdsbCsXniVSzD97KKToh5AoLbHe9JH dRoNb0ULZnRwHbS69reHhVt1SiQTTw+VheP4fJiT1CtT+T0+jAT3xgPV0FsBdf07AC6q 9MjjQqbpUTavH7+Ql8FF0HxtdJs5gD4roNY4lkQ4LKrz/vyoomlPUyXtGkrxlWWSrKEC z9ofre4v9UwfgWlPpelFwYRWlvVlY2DsQ9Za0cKP2cBKyWhOwqPkDmf1dbjSRTg3TUQM lDUg== X-Gm-Message-State: AMCzsaWJZ5EmJ6x5EYoWiKPhNyzHAqD6aWLJyoWbs4KdHFJ7bMYcFVTA HAyDe06WwXyBkVexscZQZ/ZSlg== X-Google-Smtp-Source: ABhQp+RMLZgbV4JrrajzJSUY1pkLcTGYWUzC/0WfzfQjR2oeheraeK9Y/04ZD9P/2PrvyJEiw+y4oA== X-Received: by 10.28.30.22 with SMTP id e22mr5438373wme.121.1508312639032; Wed, 18 Oct 2017 00:43:59 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.78.118]) by smtp.gmail.com with ESMTPSA id v78sm7855063wmv.48.2017.10.18.00.43.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 00:43:58 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v5 3/4] clocksource: stm32: add clocksource support Date: Wed, 18 Oct 2017 09:43:33 +0200 Message-Id: <1508312614-27750-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework driver code to be able to implement clocksource and clockevent on the same hardware block. Before this patch only the counter of the hardware block was used to generate clock events. Now counter will be used to provide a 32 bits clock source and a comparator will provide clock events. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 104 ++++++++++++++++++++++++++++---------- 1 file changed, 76 insertions(+), 28 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index f7e4eec..fb84252 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -40,30 +42,34 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long cnt; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + cnt = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(cnt + evt, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} - return 0; +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + return stm32_clock_event_set_next_event(0, evt); } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) @@ -73,12 +79,57 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x60, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; unsigned long max_arr; @@ -90,12 +141,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -119,17 +171,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -EINVAL; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + return ret; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, ~0U); + stm32_clockevent_init(to); return 0; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Wed Oct 18 07:43:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116237 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5772148qgn; Wed, 18 Oct 2017 00:44:48 -0700 (PDT) X-Received: by 10.159.204.139 with SMTP id t11mr14614907plo.121.1508312688455; Wed, 18 Oct 2017 00:44:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508312688; cv=none; d=google.com; s=arc-20160816; b=ZHdSyxctdEBpViz1MHh8YygBMKUiO6NheCxHtZwu67a3yojHH/pvtnM5ZjdugrhRxr dkAC3+Soh6/73R/ud6wc63MAHEV5TbEAcpnTJNGu0pJY126/RxskO2GD0rAJBWkt65uT Sg7QJSEf1TCXNiBLb7Olak9AbN/TKBKRvM9Ul8hevgHATnma3iV7OuBaihuxkAIuklZD N/tAPEbnQOpS/Re9uXW70D7KkKUCKEpX2rIrtI6aVVk7KCjkVLPGZ5N4EWtY+mf5EFMW T1HcxZvDm0Xc+UaZ7d0RT/c0DCeY1BDcvTUOScrSyPhcsMgISruiWx9L6UYDThJ8ZH4v IKIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=gIWPSxDv9HnLB6TufIB4GJXESapUrC/RPiFJ/qfzUXg1yBBgCMB+DixBzGMt8IOOe9 YIbqNFHVJMM5kK96nqLDYaBR2S07OJHPSxMYuk+xOv4Lns0a2/8reENf+i3Zjs9+Pa0J VJ7MPfE8ezexT3+uCWD+yzXl7BgfYKQbgWeV4Quk6zRb5QxPOK15/XVR5EZ0sjL/AYLo faCc1PigCiZdg2lrblcD7bcd9zzenlbsNWTL87SoEETavlcduOqyczBvNnAf2PIT0gJf lKhsDENZYFhf0Ucgqb64kw28jp1CGtb1PO7mUCgJeR3ss1DRU/+xAKMFgSHJi3/apZy5 Tquw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jR7Ezbh3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 90si2316190plc.506.2017.10.18.00.44.48; Wed, 18 Oct 2017 00:44:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jR7Ezbh3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935700AbdJRHoq (ORCPT + 27 others); Wed, 18 Oct 2017 03:44:46 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:57244 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935678AbdJRHoD (ORCPT ); Wed, 18 Oct 2017 03:44:03 -0400 Received: by mail-wm0-f53.google.com with SMTP id l68so8269765wmd.5 for ; Wed, 18 Oct 2017 00:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=jR7Ezbh3lL/bYJ+8Yja21XSjIai2RRvjXY6A4Q/Hdt9aKyuKi3pm+yDs2F+ndyt87F u5uQT2RSutkUkfhnhQasNQ9s22EqMUnu3PeTcmRVCfi/9LRiCHiBSf0zkOrdXla3XrXm jN0jTsp6clCc8/3xglxcyVciYpWtl/Rpbp9Es= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2xZrvZ3e33zZlEvHpmSdoaik8mhBtquzrft5bq99r4U=; b=ri4OUZbMDVxN4KdGrqAhc6uTd+KhuymOfCcXubS3mCqkHzDRxrN1uZjypYtdZ+J0RJ VBwUdDeyq2xgMVBgpo/ocLvoG5ePBUIFd4z9r4zd/SvW2oNphEPPn3UAK0c5X6iaRCDb vlmD6AR3I86o9EuYurzYO69Gj0HjR00C6+V36BCBa8xKjZfwd5By68LofEIkyCk0RTHS 86TA9afUo0kVZSa2/7ECvcY/EXegceYDFEp/ms0W+g5jwXtg0MIwVeTCHF/MUmRIpdnh cny4Jj1E3SXoNgAdm98XsBwcQBnXPHbK11uOxY9i/+qJjvSizpOhpzHg1hcIVAW4a8ql CI3A== X-Gm-Message-State: AMCzsaWhyHrAD28hlCvbAkex9rkeSXtSjGVjoe8cYcUoJflIEl5is0gW VMTILEn7VgDgL0d8yAN6tPHUOA== X-Google-Smtp-Source: ABhQp+Q/NJxGdV+O14hcONpZlnm1Ky+Mx/ZNG8Z18XcnC1ZRUx09TCJzB4yMKhcL5h0dBI3tfCi1fQ== X-Received: by 10.28.236.216 with SMTP id h85mr5983536wmi.100.1508312641538; Wed, 18 Oct 2017 00:44:01 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.78.118]) by smtp.gmail.com with ESMTPSA id v78sm7855063wmv.48.2017.10.18.00.43.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 00:44:01 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v5 4/4] arm: dts: stm32: remove useless clocksource nodes Date: Wed, 18 Oct 2017 09:43:34 +0200 Message-Id: <1508312614-27750-5-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index dd7e99b..ac9a3e6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5633860..a9077e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;