From patchwork Wed Oct 18 11:00:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 116173 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5582702qgn; Tue, 17 Oct 2017 19:57:42 -0700 (PDT) X-Google-Smtp-Source: AOwi7QA/4C7Pr68/KGnCwaLjUGGyYSXtmaYL9YDhJXXzJHXK6M6JDJS91iQJz8XjUSKtQTgN1H05 X-Received: by 10.98.210.5 with SMTP id c5mr13562466pfg.181.1508295461911; Tue, 17 Oct 2017 19:57:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508295461; cv=none; d=google.com; s=arc-20160816; b=bqNcfxtOHDKc/yp2c7YQM+qTzvbnv386bJzVqFCWvBKV6uBSC178LdepUgtf6TjJc3 F4lCokbCoxTPmq4pw4791lzMHSIuPsPuaRnauKVmTbMymQaBdqeGMXGHND82/RBaRzyX +3Mwg3K46ypl/c9TYXto58NucAHOcHo6QpQmK98deDGHU5uZD7yXXz1XZOqizvAdJUHa DCAy7vFndeMiELaVQm+Xn6sd0WDhtvyxEUlCYFPwsPhNptuAvCr5gyLIrWuMRqZxsEU1 KO8x2u2TfraTSNAycSh/OsGDn9kn+25Ugum3qCW1qoguJTyZQDJPI4zYca0kVCwTYbyb 6MbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=vNzFUrHq55MT2gKwPj8EAWgqETETFaRtLmExA2yJubo=; b=e6p0PTf+a44F3Wtjh/bssxLH8VwZfnPLO6Xi7gaVTQC62jqs1/IMRJQ8R5B/6XxRTy XwJzI3SUFpPIJkS6ZErg9GS6/2/u+5s5s9VaLDDH6SxjmyB5aHztEC7wV4b2YB9+lx7C mPCJ9Yr3cRm8uDuPAxi9cM2BsfMH/9GmgsVQI7BxTA4eCXmmCD1sRfbWi4mu+cRoOsyD USvl6pjR9/l2kyUzaVNQKNERXfiNXPYNuDD6ps4sn+236/Z7AKtjLuhZxQkDuJ8kBjCo YwtmszvIq5o4bls1xpyc67I4CibbgW3xnlZNL/V8IF3Q/QRbn2NQtYlwzfI4DmkfrT1p e/iw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si577180plm.686.2017.10.17.19.57.41; Tue, 17 Oct 2017 19:57:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757538AbdJRC5i (ORCPT + 27 others); Tue, 17 Oct 2017 22:57:38 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:8495 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607AbdJRC5g (ORCPT ); Tue, 17 Oct 2017 22:57:36 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJG66699; Wed, 18 Oct 2017 10:57:25 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:03 +0800 From: Jiancheng Xue To: , CC: , , , , , tianshuliang , Jiancheng Xue Subject: [PATCH 1/3] clk: hisilicon: add hisi phase clock support Date: Wed, 18 Oct 2017 07:00:27 -0400 Message-ID: <1508324429-6012-2-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59E6C315.0058, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fc700f37a36af640e9bd69ceff17caa8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: tianshuliang Add a phase clock type for HiSilicon SoCs,which supports clk_set_phase operation. Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue --- drivers/clk/hisilicon/Makefile | 2 +- drivers/clk/hisilicon/clk-hisi-phase.c | 117 +++++++++++++++++++++++++++++++++ drivers/clk/hisilicon/clk.c | 45 +++++++++++++ drivers/clk/hisilicon/clk.h | 22 +++++++ 4 files changed, 185 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/hisilicon/clk-hisi-phase.c -- 2.7.4 diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 1e4c3dd..7189f07 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -2,7 +2,7 @@ # Hisilicon Clock specific Makefile # -obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o +obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c new file mode 100644 index 0000000..436f0a1 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Simple HiSilicon phase clock implementation. + */ +#include +#include +#include +#include +#include +#include "clk.h" + +struct clk_hisi_phase { + struct clk_hw hw; + void __iomem *reg; + u32 *phase_values; + u32 *phase_regs; + u8 phase_num; + u32 mask; + u8 shift; + u8 flags; + spinlock_t *lock; +}; +#define to_clk_hisi_phase(_hw) container_of(_hw, struct clk_hisi_phase, hw) + +static u32 hisi_clk_get_phase_reg(struct clk_hisi_phase *phase, int degrees) +{ + int i; + + for (i = 0; i < phase->phase_num; i++) + if (phase->phase_values[i] == degrees) + return phase->phase_regs[i]; + + return -EINVAL; +} + +static int hisi_clk_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); + u32 val, phase_reg; + unsigned long flags = 0; + + phase_reg = hisi_clk_get_phase_reg(phase, degrees); + if (phase_reg < 0) + return phase_reg; + + if (phase->lock) + spin_lock_irqsave(phase->lock, flags); + else + __acquire(phase->lock); + + val = clk_readl(phase->reg); + val &= ~(phase->mask << phase->shift); + val |= phase_reg << phase->shift; + clk_writel(val, phase->reg); + + if (phase->lock) + spin_unlock_irqrestore(phase->lock, flags); + else + __release(phase->lock); + + return 0; +} + +const struct clk_ops clk_phase_ops = { + .set_phase = hisi_clk_set_phase, +}; + +void clk_unregister_hisi_phase(struct clk *clk) +{ + struct clk_hisi_phase *phase; + struct clk_hw *hw; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + phase = to_clk_hisi_phase(hw); + clk_unregister(clk); +} +EXPORT_SYMBOL_GPL(clk_unregister_hisi_phase); + +struct clk *clk_register_hisi_phase(struct device *dev, + const struct hisi_phase_clock *clks, + void __iomem *base, spinlock_t *lock) +{ + struct clk_hisi_phase *phase; + struct clk *clk; + struct clk_init_data init; + + phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL); + if (!phase) + return ERR_PTR(-ENOMEM); + + init.name = clks->name; + init.ops = &clk_phase_ops; + init.flags = clks->flags | CLK_IS_BASIC; + init.parent_names = clks->parent_names ? &clks->parent_names : NULL; + init.num_parents = clks->parent_names ? 1 : 0; + + phase->reg = base + clks->offset; + phase->shift = clks->shift; + phase->mask = BIT(clks->width) - 1; + phase->lock = lock; + phase->phase_values = clks->phase_values; + phase->phase_regs = clks->phase_regs; + phase->phase_num = clks->phase_num; + phase->hw.init = &init; + + clk = clk_register(NULL, &phase->hw); + return clk; +} +EXPORT_SYMBOL_GPL(clk_register_hisi_phase); diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index b73c1df..e3adfad 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -197,6 +197,51 @@ int hisi_clk_register_mux(const struct hisi_mux_clock *clks, } EXPORT_SYMBOL_GPL(hisi_clk_register_mux); +int hisi_clk_register_phase(struct device *dev, + const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data) +{ + int i; + struct clk *clk; + void __iomem *base = data->base; + + for (i = 0; i < nums; i++) { + clk = clk_register_hisi_phase(dev, + &clks[i], base, &hisi_clk_lock); + + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + goto err; + } + + data->clk_data.clks[clks[i].id] = clk; + } + return 0; + +err: + while (i--) + clk_unregister_hisi_phase(data->clk_data.clks[clks[i].id]); + + return PTR_ERR(clk); +} +EXPORT_SYMBOL_GPL(hisi_clk_register_phase); + +void hisi_clk_unregister_phase(const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data) +{ + struct clk **clocks = data->clk_data.clks; + int i, id; + + for (i = 0; i < nums; i++) { + id = clks[i].id; + + if (clocks[id]) + clk_unregister_hisi_phase(clocks[id]); + } +} +EXPORT_SYMBOL_GPL(hisi_clk_unregister_phase); + int hisi_clk_register_divider(const struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 4e1d1af..bc18730 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -68,6 +68,19 @@ struct hisi_mux_clock { const char *alias; }; +struct hisi_phase_clock { + unsigned int id; + const char *name; + const char *parent_names; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u32 *phase_values; + u32 *phase_regs; + u8 phase_num; +}; + struct hisi_divider_clock { unsigned int id; const char *name; @@ -120,6 +133,15 @@ int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, int, struct hisi_clock_data *); int hisi_clk_register_mux(const struct hisi_mux_clock *, int, struct hisi_clock_data *); +struct clk *clk_register_hisi_phase(struct device *dev, + const struct hisi_phase_clock *clks, + void __iomem *base, spinlock_t *lock); +void clk_unregister_hisi_phase(struct clk *clk); +int hisi_clk_register_phase(struct device *dev, + const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data); +void hisi_clk_unregister_phase(const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data); int hisi_clk_register_divider(const struct hisi_divider_clock *, int, struct hisi_clock_data *); int hisi_clk_register_gate(const struct hisi_gate_clock *, From patchwork Wed Oct 18 11:00:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 116172 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5582650qgn; Tue, 17 Oct 2017 19:57:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDGKfImQX5cSGFdnbmCjUcgeMnU1KAOguZuSh1e4M5bPznbO0fb6udq9Cys5Q8ESyYFcE1S X-Received: by 10.84.130.108 with SMTP id 99mr13898528plc.343.1508295457475; Tue, 17 Oct 2017 19:57:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508295457; cv=none; d=google.com; s=arc-20160816; b=aFHdc89xVpc772aBgEKEhomA8Zz8RjDYEy2IOV+DbbIW1j7XTluoznpR75x5qZ9mR/ KDiN0j98oaiHvsXyyWv2h7kR7mQOpDFzMRKN+PilZZML1eGiQIUFVY1ArthK9U9y+cVJ oV3h++2s1IzFY7JgiAGUXiCIvM+1OT6+ZzlZw/oLe51viNv3PMqHNjIvs28PWvRIjt8q bZ6Gr7T3rh/J6oMrUORD6vdThs9NISP17i9QgW0pM3prA7tYP3iI1MhyBCdIJYJphVj7 0L2KGspt5N0nR5WO1DGzOIWPJJ9IrWsLu8JJfhFvw+usXoehuLflrZYBH10Qzyi28en/ o5ZQ== ARC-Message-Signature: i=1; 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Wed, 18 Oct 2017 10:57:24 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:03 +0800 From: Jiancheng Xue To: , CC: , , , , , tianshuliang , Jiancheng Xue Subject: [PATCH 2/3] clk: hisilicon: add emmc sample and drive clock for hi3798cv200 SoC Date: Wed, 18 Oct 2017 07:00:28 -0400 Message-ID: <1508324429-6012-3-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59E6C315.006D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3d4d91a454f65dda5af82117e416fc17 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: tianshuliang Add emmc sample and emmc drive clock for Hi3798cv200 SoC Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue --- drivers/clk/hisilicon/crg-hi3798cv200.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index ed8bb5f..25d750c 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -83,6 +83,18 @@ static struct hisi_mux_clock hi3798cv200_mux_clks[] = { CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, }, }; +static u32 mmc_phase_reg[] = {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 mmc_phase_val[] = {0, 45, 90, 135, 180, 225, 270, 315}; + +static struct hisi_phase_clock hi3798cv200_phase_clks[] = { + { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_val, + mmc_phase_reg, ARRAY_SIZE(mmc_phase_reg)}, + { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_val, + mmc_phase_reg, ARRAY_SIZE(mmc_phase_reg)}, +}; + static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { /* UART */ { HISTB_UART2_CLK, "clk_uart2", "75m", @@ -179,11 +191,18 @@ static struct hisi_clock_data *hi3798cv200_clk_register( if (ret) goto unregister_fixed_rate; + ret = hisi_clk_register_phase(&pdev->dev, + hi3798cv200_phase_clks, + ARRAY_SIZE(hi3798cv200_phase_clks), + clk_data); + if (ret) + goto unregister_mux; + ret = hisi_clk_register_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks), clk_data); if (ret) - goto unregister_mux; + goto unregister_phase; ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data); @@ -201,6 +220,10 @@ static struct hisi_clock_data *hi3798cv200_clk_register( hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); +unregister_phase: + hisi_clk_unregister_phase(hi3798cv200_phase_clks, + ARRAY_SIZE(hi3798cv200_phase_clks), + clk_data); unregister_gate: hisi_clk_unregister_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks), From patchwork Wed Oct 18 11:00:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 116175 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5582871qgn; Tue, 17 Oct 2017 19:57:58 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Qpr4hyraUEPKpRhvsRMJJhj9Tm2ncm3SK5rZLaOQ/2jFQvKW6JY7L6Q4iR1KDw25kNRsLq X-Received: by 10.84.138.193 with SMTP id 59mr5099488plp.446.1508295478632; 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[209.132.180.67]) by mx.google.com with ESMTP id f4si577180plm.686.2017.10.17.19.57.58; Tue, 17 Oct 2017 19:57:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757636AbdJRC5n (ORCPT + 27 others); Tue, 17 Oct 2017 22:57:43 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:8931 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757541AbdJRC5j (ORCPT ); Tue, 17 Oct 2017 22:57:39 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJG66698; Wed, 18 Oct 2017 10:57:24 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:03 +0800 From: Jiancheng Xue To: , CC: , , , , , Younian Wang Subject: [PATCH 3/3] clk: hisilicon: correct ir clock rate for hi3798cv200 SoC Date: Wed, 18 Oct 2017 07:00:29 -0400 Message-ID: <1508324429-6012-4-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59E6C315.0041, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bcd34a9fcbf4c08560e01e6b678d4b6e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Younian Wang Correct ir clock rate for hi3798cv200 SoC. Signed-off-by: Younian Wang --- drivers/clk/hisilicon/crg-hi3798cv200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 25d750c..61bd941 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -258,7 +258,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { #define HI3798CV200_SYSCTRL_NR_CLKS 16 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { - { HISTB_IR_CLK, "clk_ir", "100m", + { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, { HISTB_TIMER01_CLK, "clk_timer01", "24m", CLK_SET_RATE_PARENT, 0x48, 6, 0, },