From patchwork Wed Sep 16 18:28:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalil Blaiech X-Patchwork-Id: 254721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20D59C43461 for ; Wed, 16 Sep 2020 18:28:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD53A20936 for ; Wed, 16 Sep 2020 18:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727916AbgIPS2w (ORCPT ); Wed, 16 Sep 2020 14:28:52 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:57915 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728043AbgIPS2g (ORCPT ); Wed, 16 Sep 2020 14:28:36 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from kblaiech@mellanox.com) with SMTP; 16 Sep 2020 21:28:28 +0300 Received: from farm-1.mtbu.labs.mlnx (farm-1.mtbu.labs.mlnx [10.15.2.31]) by mtbu-labmailer.labs.mlnx (8.14.4/8.14.4) with ESMTP id 08GISR1v007887; Wed, 16 Sep 2020 14:28:27 -0400 Received: (from kblaiech@localhost) by farm-1.mtbu.labs.mlnx (8.14.7/8.13.8/Submit) id 08GISRrj030673; Wed, 16 Sep 2020 14:28:27 -0400 From: Khalil Blaiech To: Rob Herring , linux-i2c@vger.kernel.org Cc: Khalil Blaiech , Vadim Pasternak Subject: [RESEND PATCH v9 2/2] dt-bindings: i2c: I2C binding for Mellanox BlueField SoC Date: Wed, 16 Sep 2020 14:28:20 -0400 Message-Id: <6c4005b8c0ccba4dc6391d187de4f816562d352b.1600277745.git.kblaiech@mellanox.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: References: In-Reply-To: References: Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Khalil Blaiech Add device tree bindings documentation for Mellanox BlueField I2C SMBus controller. Signed-off-by: Khalil Blaiech --- v5->v6: - Adding description of an extra resource to be consistent with new BlueField-2 SoCs. - Adding an additional example of device instance. v3->v4: - Re-ordering of the property descriptions. - Removing useless register addresses from the resource description. - Definition of default clock-frequency value. - Fixing format issues; removing spaces. - Removing "aliases" from Example section. - Renaming device instance node in Example section. v2->v3: - Removing shared resources from the controller instance. - Updating the 'compatible' property and support the second generation of the Mellanox BlueField SoC. - Fixing file format; replacing spaces with tabs. v1->v2: - Enumeration of the device resources. - Updating the 'compatible' property to make it less generic. - Removing the 'bus' index property and replace it with standard approach to read the bus identifier. - Getting rid of the 'profile' property. - Using 'clock-frequency' property instead of 'bus-freq'. - Convertion of the clock frequency from KHz to Hz. - Removing useless examples. --- .../devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt new file mode 100644 index 0000000..566ea86 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt @@ -0,0 +1,42 @@ +Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs + +Required Properties: + +- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2". + +- reg : address offset and length of the device registers. The + registers consist of the following set of resources: + 1) Smbus block registers. + 2) Cause master registers. + 3) Cause slave registers. + 4) Cause coalesce registers (if compatible isn't set + to "mellanox,i2c-mlxbf1"). + +- interrupts : interrupt number. + +Optional Properties: + +- clock-frequency : bus frequency used to configure timing registers; + allowed values are 100000, 400000 and 1000000; + those are expressed in Hz. Default is 100000. + +Example: + +i2c@2804000 { + compatible = "mellanox,i2c-mlxbf1"; + reg = <0x02804000 0x800>, + <0x02801200 0x020>, + <0x02801260 0x020>; + interrupts = <57>; + clock-frequency = <100000>; +}; + +i2c@2808800 { + compatible = "mellanox,i2c-mlxbf2"; + reg = <0x02808800 0x600>, + <0x02808e00 0x020>, + <0x02808e20 0x020>, + <0x02808e40 0x010>; + interrupts = <57>; + clock-frequency = <400000>; +};