From patchwork Tue Oct 17 16:55:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 116150 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1444722edb; Tue, 17 Oct 2017 09:56:10 -0700 (PDT) X-Received: by 10.99.185.18 with SMTP id z18mr11798237pge.212.1508259370447; Tue, 17 Oct 2017 09:56:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508259370; cv=none; d=google.com; s=arc-20160816; b=0/bNEjIPI/q2nGBOEV3OgLE0yIScVaYCCzkjAWkX5Ar24Nxj921LTaC5Z+tedurrTA K1HsEFa7V3zspQIdDfcbl8igjMGF5cI+S/U9OL5nwPGbyMy5uvRXHGea4COZ2vhCjpzY VkzKr7W+k2YKhJE2+i9tZ1wA54bMdldDr2oi1x+Os73CfqsoIzPOkZeu8S4jUesJfYmS NyJgZjM//Z1RnvRJ/vpAHq3SZHJ43q3fgFLrYg8R+MZt0V96CoLlk35edMvMdoi/doQA yU0eCMtnWlVoVJFo4bcnH+W27dBygkStbrDx6t/eTDpApyfN5so90oUsXvA5lAq6mEij ausQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EQu7PFLjrq2GiEHpKuuMmsW9JiqjM6AT0EmeueAqLhg=; b=jIEQ/Y8vwJfuEIsU/RFOYlRk9K0Grdnz6QdkDq9vOKuSUKOmL69W9WN5i/j+l33kPn FGJboL4jwTGUp1pYp5mwdpAXMa+DGxKVsCk3dy0F6uhUrJKw+crx6ML5aaWg1JF0TULZ 4EpUvt0IoAKW+WYguF9/MgMw5mdJ14Nndpd886GZL9Sa2PP2WELLSK60lWz8nmcSxU/g 2ceBGL9hcYFfgBrxJkgP0JyyI1HqmHrCX54VJ8+ltBqqs+n+AvDYFKBb3pBLqQaNNAfE 80iZD/dF65HsZUpiKwmbI2oDJ/69zxFqnAcdC57w/HBddpJaXHIr6qoOTAKvgHGtVMPL 2KRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=agH1izFS; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i72si6128715pfe.165.2017.10.17.09.56.10; Tue, 17 Oct 2017 09:56:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=agH1izFS; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934132AbdJQQ4J (ORCPT + 6 others); Tue, 17 Oct 2017 12:56:09 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:43503 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934082AbdJQQ4I (ORCPT ); Tue, 17 Oct 2017 12:56:08 -0400 Received: by mail-wm0-f48.google.com with SMTP id m72so9704645wmc.0 for ; Tue, 17 Oct 2017 09:56:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hcoqsPVs5C7Pd8/M04kFqx7qMm95VJSP1qF5aCHerpw=; b=agH1izFSFoZ+S90jz3ZSK4hykMXq5pukksiXoo456oaOhDZ4iI4bl2fXyUcLNODlmg iGCMvlJBxagtL0gGgacAalzFMNuQddc/N1UxZXNODzDbX1WhCYaNhgnKUqSuOpv3yLqC xVLqhbH90D05Ke5802t1AOzVjk75VJvORu6a0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hcoqsPVs5C7Pd8/M04kFqx7qMm95VJSP1qF5aCHerpw=; b=IJi2ps7MsrPPG5PH2hMjTf/ftZOyGV51w2YkYUpM0j7mVft1neMPaKre61CzAg+Kyq SKgcoHrc+KoRBQaO8L7IPO3Nuo+YC8+FW1zcNAiK0jF5LRZSQAjUW+xoRJIOwle291hY 94t57niIgAqt1fmc5gPGdPwWUsdpAXkJW8+lKDPT/v9dUfOpwR0kbUTfNsDGjCj/Khq6 EYeWmLxyXQiSOi0Km7ZMzpONNKEvOG1vZiW6OampL7V2IUhZ71lgkuMSHxwa+9IapSWu HDqkKtBi91xLwyGEJNOd3qNVZQuZF52wBqgyXL3UMdJ8m1BSSqMkW4E7TZ7BliBuxoSX eNcw== X-Gm-Message-State: AMCzsaW6LK2D9PiLMjo9a0AVmqgAOc8YCSt1/vjDfT7PxY9nhfV/r4co uw9nOaTdTl+qw8NTV5/V9gjgwQ== X-Google-Smtp-Source: ABhQp+T3Xb1woWalaMoraN5WTT8jHMe3Loo3zfZXrhVuWz26UKQ3eyqRa0VcXK68F35QWlxDEGMa+g== X-Received: by 10.28.129.194 with SMTP id c185mr3912112wmd.49.1508259367366; Tue, 17 Oct 2017 09:56:07 -0700 (PDT) Received: from localhost.localdomain ([154.144.50.139]) by smtp.gmail.com with ESMTPSA id y84sm5854517wmg.43.2017.10.17.09.56.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Oct 2017 09:56:05 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v5 1/3] drivers/irqchip: gicv3: probe device ID space before quirks handling Date: Tue, 17 Oct 2017 17:55:54 +0100 Message-Id: <20171017165556.30250-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171017165556.30250-1-ard.biesheuvel@linaro.org> References: <20171017165556.30250-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Before adding another SoC whose device ID space deviates from the value presented in the GIC ID registers, let's slightly refactor the code so that the ID registers are probed before that quirks handling executes. This allows us to move the device ID override into the quirk handler itself. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-v3-its.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e8d89343d613..891de07fd4cc 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1650,23 +1650,14 @@ static void its_free_tables(struct its_node *its) static int its_alloc_tables(struct its_node *its) { - u64 typer = gic_read_typer(its->base + GITS_TYPER); - u32 ids = GITS_TYPER_DEVBITS(typer); u64 shr = GITS_BASER_InnerShareable; u64 cache = GITS_BASER_RaWaWb; u32 psz = SZ_64K; int err, i; - if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { - /* - * erratum 22375: only alloc 8MB table size - * erratum 24313: ignore memory access type - */ - cache = GITS_BASER_nCnB; - ids = 0x14; /* 20 bits, 8MB */ - } - - its->device_ids = ids; + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) + /* erratum 24313: ignore memory access type */ + cache = GITS_BASER_nCnB; for (i = 0; i < GITS_BASER_NR_REGS; i++) { struct its_baser *baser = its->tables + i; @@ -2741,6 +2732,8 @@ static void __maybe_unused its_enable_quirk_cavium_22375(void *data) { struct its_node *its = data; + /* erratum 22375: only alloc 8MB table size */ + its->device_ids = 0x14; /* 20 bits, 8MB */ its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; } @@ -2942,6 +2935,7 @@ static int __init its_probe_one(struct resource *res, its->base = its_base; its->phys_base = res->start; its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); + its->device_ids = GITS_TYPER_DEVBITS(typer); its->is_v4 = !!(typer & GITS_TYPER_VLPIS); if (its->is_v4) { if (!(typer & GITS_TYPER_VMOVP)) { From patchwork Tue Oct 17 16:55:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 116151 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1444767edb; Tue, 17 Oct 2017 09:56:14 -0700 (PDT) X-Received: by 10.99.133.200 with SMTP id u191mr11705603pgd.426.1508259374255; Tue, 17 Oct 2017 09:56:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508259374; cv=none; d=google.com; s=arc-20160816; b=ZGOt0JKsPxoBcjJ7+vC6mpMBTu6xB7SbX4fN6UmU3BDHPBRwlBltHbSVfytAkgpiOL b51HBLh5ZfLEBkw1QgMq9Fe0MV8AvZDg0RzqRbWPEXqyMzMCAlSxrifxS+OBg6RJ77mk 5nO+Hnl/ZnhGxzGibXuN9TLQ5N5bu7ln7xdTIa7V4iVjhUAw7+L3bGNPfaXv8PRLO8RG aAoftGTTqN3cYD0X18qWFgkXkcM5qgto68hShQakQWuegAO4VhJImWaB6fBUw5zKpp2d EdNHZ5LJ3i4z5fIUbU18Vid2eCrCanwhLgV+ai/OSqLqKjlsbaFwKseh5pXmI2Smkc2C WsKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MmKOl5SAc5SB6evwTPYxNICjnstxUP7IIORre6iFlwI=; b=R/B1dDRSEuPAyNgTBP4AGGWSi+jp8McIyrkM35BVJZ9M1gzQ5q/hUKKtb91jROCB8K pemCX9HDh2HdUTVxzdqV6EFTpDnXsJ/P0WuaUj0k1ZbzoA15Q7MffNcqhocLRFksUZ4w umBfmuWzgqBExFrGSgBVucnTWD/9mwqYyl21N74K/+IVI0W+giiEuZDSlW+/Ot3P6uOS k3fyvUQdu1831fHWvhXrDPe3YmcGfzCEpvH5oyrL78XvgW1nkLpgjEFnkSeFByZK/j6E GTSMoADPWmbr19ttEGJFxvIwftQQ9JdVHVfNCVm6J7R8+sRydfQHK0g84aMhaFsm87c9 q0gA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jkEXYxcS; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i72si6128715pfe.165.2017.10.17.09.56.14; Tue, 17 Oct 2017 09:56:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jkEXYxcS; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934143AbdJQQ4N (ORCPT + 6 others); Tue, 17 Oct 2017 12:56:13 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:56355 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934082AbdJQQ4M (ORCPT ); Tue, 17 Oct 2017 12:56:12 -0400 Received: by mail-wm0-f52.google.com with SMTP id l68so5224596wmd.5 for ; Tue, 17 Oct 2017 09:56:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5MZeF5H0kxfAkUgudBaKRgw2g16JWJEnv8PWhghXnhE=; b=jkEXYxcSdkJv4lmqUe46G1mT6pbLRk4X16ah272ad5nWiSePR9O7oQhECfvQnVcwmM iqipsU8xJvzqlwTujeCCvxBenBDiL6W+4bqQbiwwhekxFClzKf+HTXiFfe2CZH3LCnes f9Mm3b4oCYaVjpaN95XM2xz5j5QUYQ5cSVvCU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5MZeF5H0kxfAkUgudBaKRgw2g16JWJEnv8PWhghXnhE=; b=ovfA1JBtcafDYdwEyPqsSfGWeRg3kYPjIZ2is+VdqHLnPdyKfMS23BZD7hSVJ+eYIn G7xz7QVjDqEHKRBdH21MDBrVcc2uWmQPkNHrknUhmxX/YnEJ8uqgzWHbTfKLipBfzMSm FK4DPRdMmMfIlEr29DcuF80vxf1R9G9Vn6zLuMKWtQeBJDTzqymUKBp+8I5YEshfHD/V VZykzr9kwQ4XfT4hT3FzT8X+/b/zjAt/ymokRopTY345QLGDnfhAyplGnnqpmDcbj3RU QRQwcr3nDWL8ZAsqUprDe2rph9aS6GvdSPhEblJP/Fulx+0EgTcIFo7rElvQAlDIBC3t +C6Q== X-Gm-Message-State: AMCzsaU++0F9UGnuzc/epFf7L/ApvubVs4dPhCpu2B2cjz6o6/v8DnAm 11s0FUd/PThOlQUfnLwqV279XQ== X-Google-Smtp-Source: ABhQp+QlilykbueSwicJCD7EOB+yOWoDuUECWsGkRpGL/uPd/6C0Ev+288QIxCaX3kYJaRuoNmadHQ== X-Received: by 10.28.105.76 with SMTP id e73mr4476735wmc.116.1508259371002; Tue, 17 Oct 2017 09:56:11 -0700 (PDT) Received: from localhost.localdomain ([154.144.50.139]) by smtp.gmail.com with ESMTPSA id y84sm5854517wmg.43.2017.10.17.09.56.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Oct 2017 09:56:09 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v5 2/3] drivers/irqchip: gic: make quirks matching conditional on init return value Date: Tue, 17 Oct 2017 17:55:55 +0100 Message-Id: <20171017165556.30250-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171017165556.30250-1-ard.biesheuvel@linaro.org> References: <20171017165556.30250-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As it turns out, the IIDR is not sufficient to distinguish between GICv3 implementations when it comes to enabling quirks. So update the prototype of the init() hook to return a bool, and interpret a 'false' return value as no match, in which case the 'enabling workaround' log message should not be printed. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-common.c | 5 +++-- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3-its.c | 12 +++++++++--- 3 files changed, 13 insertions(+), 6 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9ae71804b5dd..30017df5b54c 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -40,8 +40,9 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, for (; quirks->desc; quirks++) { if (quirks->iidr != (quirks->mask & iidr)) continue; - quirks->init(data); - pr_info("GIC: enabling workaround for %s\n", quirks->desc); + if (quirks->init(data)) + pr_info("GIC: enabling workaround for %s\n", + quirks->desc); } } diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 205e5fddf6da..3919cd7c5285 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -23,7 +23,7 @@ struct gic_quirk { const char *desc; - void (*init)(void *data); + bool (*init)(void *data); u32 iidr; u32 mask; }; diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 891de07fd4cc..c34f21c7a38e 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2728,28 +2728,34 @@ static int its_force_quiescent(void __iomem *base) } } -static void __maybe_unused its_enable_quirk_cavium_22375(void *data) +static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) { struct its_node *its = data; /* erratum 22375: only alloc 8MB table size */ its->device_ids = 0x14; /* 20 bits, 8MB */ its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; + + return true; } -static void __maybe_unused its_enable_quirk_cavium_23144(void *data) +static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) { struct its_node *its = data; its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; + + return true; } -static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) +static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) { struct its_node *its = data; /* On QDF2400, the size of the ITE is 16Bytes */ its->ite_size = 16; + + return true; } static const struct gic_quirk its_quirks[] = { From patchwork Tue Oct 17 16:55:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 116152 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1444806edb; Tue, 17 Oct 2017 09:56:17 -0700 (PDT) X-Received: by 10.84.233.69 with SMTP id k5mr12863853plt.189.1508259376975; Tue, 17 Oct 2017 09:56:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508259376; cv=none; d=google.com; s=arc-20160816; b=Wl0LjlbmjCuskoNj9k1ZjtAXRBo1JhYpFC4sOhhfBeVwJMiXge+Z+ncECYQ4KjopFa NNado0u9BhE9yXSoHE5SgY6kMFpisuI9lqyjjr2ud2lliZdFIEoqn1by2bfnmuJ9Gp8e qtsSopeOeHns2dJ3IJL+ix8WIbTXPv9xeIJZH8cDV7uQYZ65Z838t9ueqw/XN8sk7TpA kh5XQi7xr088SVBf8oRkLCAOPbdmx0J1gQWZJqtOT3v8/Q3i2IOviuCsbsaePynYQa+a 4YVWygs04EakuJ0NpxjH9RxRpU0ZNc4mYACbSGYrWOqJcbf+Xudr0jr0rmp12uLELcLN vR1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=2xKQmmVUCiS+r4q6hGwUPkSMByZrYmU6l+FXbeWobB8=; b=KKIAvhr/l3gfhv/SjcenhoH7zXcMFxO1X3oTpwec+Fi5wrl7aNbsQG00xpzsSJkire 1z/sWXmB6a3BH7pPjl+dtOgE57G/NsW1mYxDBfbXWT6UbGHCSpPHQdrf/QgkqqePdg0z n2UCu5S/yf+pB+odAST0vFpanHtZBCzz6AP5m1mkIsTFsZCEwN/m27CMDOpqJwdvDyY0 32q0+UZLfwQFnyC02OqwxyUAZOB+RObhLN2Q65KY/sayXHLfnKG1HhjV2qvXJPERR6d8 7kuc9cOfmHKad5nGp93Zin/Me+joK9SMddXjGcd52EZnGUd9Em8M1cZGlzG6kyiP8yZi A2fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jVbu3tjz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i72si6128715pfe.165.2017.10.17.09.56.16; Tue, 17 Oct 2017 09:56:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jVbu3tjz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934144AbdJQQ4Q (ORCPT + 6 others); Tue, 17 Oct 2017 12:56:16 -0400 Received: from mail-wr0-f176.google.com ([209.85.128.176]:51034 "EHLO mail-wr0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934082AbdJQQ4O (ORCPT ); Tue, 17 Oct 2017 12:56:14 -0400 Received: by mail-wr0-f176.google.com with SMTP id q42so2396834wrb.7 for ; Tue, 17 Oct 2017 09:56:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ELJn5DzE13okxuglSbAYOrhTrvqUaU3kopJf5Xe1EMU=; b=jVbu3tjz418ouC8s9DONeu7fEY7CkKcFgja0qKVrurq3thFmA9TJJjHLXTuKHJWdfJ G1SFNbGnOf3wuQFqmrtnMh3Ff8dUdJRQ0DHjktRAZjZkKDBENyh4oR3iyDA/hxl1Jjlu R4LXX+XcKLLbmLTP+mC6issFoNJaFWCvDG/DU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ELJn5DzE13okxuglSbAYOrhTrvqUaU3kopJf5Xe1EMU=; b=jpuiPJ3Sg+lJoIBNZB414junMFXVa8JCM6U4KyS1F9Cn50wrNPC48MuUlc9HKCHgZY vLGGVMIqOTHYpJ3Pa0e7cHQpD0+yhPOFWLK578GZ08jgYdYoBIDd6xm4iCuTpl4SxBhn BuwAP5ryFXYjZ/wlWliyCY62c8ynMtLzYroOa+yZjoiUqC9zgXzkO7KIBezXTrI34VtP KWyJ4KKo599Ylto3/FKSR2X+w90VaimriCFD8+Szvloe7VPHX5cLaJd7bECkIuAlail6 33IGdsTJOKdyjpQuwHgbhi3nCIzaVI/ShadY41i4EzYY2Ngr7ksZ63u4WBiktcMPugEa k0DQ== X-Gm-Message-State: AMCzsaUjCAET9fwXRbvKwxqhdU/Q8HWB4ErTV3pphF28JtPSqEj+VEal VKcTYM6VDz+c9Ac1Au+O2358Tg== X-Google-Smtp-Source: ABhQp+Tjrm9uIpjpMl/KTNa+UvDWWodZAzuJHmMVnA7miX1r8z8sX1pnn27n1/U4NU8D1GWdA3XnPw== X-Received: by 10.223.179.1 with SMTP id j1mr4458251wrd.105.1508259373403; Tue, 17 Oct 2017 09:56:13 -0700 (PDT) Received: from localhost.localdomain ([154.144.50.139]) by smtp.gmail.com with ESMTPSA id y84sm5854517wmg.43.2017.10.17.09.56.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Oct 2017 09:56:12 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v5 3/3] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Date: Tue, 17 Oct 2017 17:55:56 +0100 Message-Id: <20171017165556.30250-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171017165556.30250-1-ard.biesheuvel@linaro.org> References: <20171017165556.30250-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ arch/arm64/Kconfig | 8 +++ drivers/irqchip/irq-gic-v3-its.c | 72 +++++++++++++++++++- 3 files changed, 82 insertions(+), 2 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..c3e6092f3add 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated + address and size of the pre-ITS window. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index c34f21c7a38e..1172b8583db4 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -83,6 +83,8 @@ struct its_baser { u32 psz; }; +struct its_device; + /* * The ITS structure - contains most of the infrastructure, with the * top-level MSI domain, the command queue, the collections, and the @@ -97,11 +99,15 @@ struct its_node { struct its_cmd_block *cmd_write; struct its_baser tables[GITS_BASER_NR_REGS]; struct its_collection *collections; + struct fwnode_handle *fwnode_handle; + u64 (*get_msi_base)(struct its_device *its_dev); struct list_head its_device_list; u64 flags; u32 ite_size; u32 device_ids; int numa_node; + unsigned int msi_domain_flags; + u32 pre_its_base; /* for Socionext Synquacer */ bool is_v4; }; @@ -1095,6 +1101,13 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); @@ -1102,7 +1115,7 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) u64 addr; its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its->get_msi_base(its_dev); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); @@ -2758,6 +2771,45 @@ static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) return true; } +static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); +} + +static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) +{ + struct its_node *its = data; + u32 pre_its_window[2]; + u32 ids; + + if (!fwnode_property_read_u32_array(its->fwnode_handle, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window))) { + + its->pre_its_base = pre_its_window[0]; + its->get_msi_base = its_irq_get_msi_base_pre_its; + + ids = ilog2(pre_its_window[1]) - 2; + if (its->device_ids > ids) + its->device_ids = ids; + + /* the pre-ITS breaks isolation, so disable MSI remapping */ + its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; + return true; + } + return false; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -2783,6 +2835,19 @@ static const struct gic_quirk its_quirks[] = { .init = its_enable_quirk_qdf2400_e0065, }, #endif +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + { + /* + * The Socionext Synquacer SoC incorporates ARM's own GIC-500 + * implementation, but with a 'pre-ITS' added that requires + * special handling in software. + */ + .desc = "ITS: Socionext Synquacer pre-ITS", + .iidr = 0x0001143b, + .mask = 0xffffffff, + .init = its_enable_quirk_socionext_synquacer, + }, +#endif { } }; @@ -2811,7 +2876,7 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); - inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + inner_domain->flags |= its->msi_domain_flags; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -2965,6 +3030,9 @@ static int __init its_probe_one(struct resource *res, goto out_free_its; } its->cmd_write = its->cmd_base; + its->fwnode_handle = handle; + its->get_msi_base = its_irq_get_msi_base; + its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; its_enable_quirks(its);