From patchwork Thu Aug 6 09:21:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D79FC38147 for ; Thu, 6 Aug 2020 11:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FA3422DCC for ; Thu, 6 Aug 2020 11:13:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GF9F6mWV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729257AbgHFJcl (ORCPT ); Thu, 6 Aug 2020 05:32:41 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47550 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729002AbgHFJWq (ORCPT ); Thu, 6 Aug 2020 05:22:46 -0400 X-UUID: 9b5a535d52124b33b67b243e4bcc4b26-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dGXGiunHjZndJ6cHTy/bVaVcZvEJmUdgQt8u80wNGMc=; b=GF9F6mWVU+fjxwWa8z4VOZHYFq3LUr3qvEA/mJ6FmxyH87jGLiPuMoPINvDvit195pxf1M1Td0uQdqVG6Flb5iLRQIZVN9A5DIKLkqKS+U4XWJA6eTvBUIZ/0h9yHvjYOioDwx/rA+prlmsSFzu4v8VKx6S5B+XamAtcIdDApBQ=; X-UUID: 9b5a535d52124b33b67b243e4bcc4b26-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 231799712; Thu, 06 Aug 2020 17:22:01 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:21:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:21:58 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Date: Thu, 6 Aug 2020 17:21:44 +0800 Message-ID: <1596705715-15320-2-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For scpsys driver using regmap based syscon driver API. Signed-off-by: Weiyi Lu Acked-by: Rob Herring --- .../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.8.1.1.dirty diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index b478ade..01744ec 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -20,7 +20,7 @@ Required properties: "mediatek,mt2712-smi-common" "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" "mediatek,mt8173-smi-common" - "mediatek,mt8183-smi-common" + "mediatek,mt8183-smi-common", "syscon" - reg : the register and size of the SMI block. - power-domains : a phandle to the power domain of this local arbiter. - clocks : Must contain an entry for each entry in clock-names. From patchwork Thu Aug 6 09:21:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E6B7C43619 for ; Thu, 6 Aug 2020 11:13:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B91B0230FF for ; Thu, 6 Aug 2020 11:13:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="bM9OwKWN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729163AbgHFJXy (ORCPT ); Thu, 6 Aug 2020 05:23:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:15338 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729148AbgHFJXr (ORCPT ); Thu, 6 Aug 2020 05:23:47 -0400 X-UUID: 3ec5c33400184da9ba7c50cd7abfbd4e-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=X1NDBhTPonNFCyfn+Vu9nt4rKMEPznMllsnD3UGUKPo=; b=bM9OwKWN2SxfmFrcZGo0mAN6nL07yUbC8pWrcQpEjRkkyvL4NVjMvaPtsC17wItDCBgRPs/+EHlUlQ1/nWpIJMQ6BNjRjT2vlC7/rHFYSTFa1vdCZS6OX8pEyeVYrG03JBpM9qCAFlMlIjxjbayJSIt7d1lTzkuEGLrnGlzgY7k=; X-UUID: 3ec5c33400184da9ba7c50cd7abfbd4e-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 385439523; Thu, 06 Aug 2020 17:22:01 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:21:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:21:59 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 02/12] soc: mediatek: Add basic_clk_name to scp_power_data Date: Thu, 6 Aug 2020 17:21:45 +0800 Message-ID: <1596705715-15320-3-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Try to stop extending the clk_id or clk_names if there are more and more new BASIC clocks. To get its own clocks by the basic_clk_name of each power domain. And then use basic_clk_name strings for all compatibles, instead of mixing clk_id and clk_name. Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 134 ++++++++++++-------------------------- 1 file changed, 41 insertions(+), 93 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f669d37..c9c3cf7 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -78,34 +78,6 @@ #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ #define PWR_STATUS_WB BIT(27) /* MT7622 */ -enum clk_id { - CLK_NONE, - CLK_MM, - CLK_MFG, - CLK_VENC, - CLK_VENC_LT, - CLK_ETHIF, - CLK_VDEC, - CLK_HIFSEL, - CLK_JPGDEC, - CLK_AUDIO, - CLK_MAX, -}; - -static const char * const clk_names[] = { - NULL, - "mm", - "mfg", - "venc", - "venc_lt", - "ethif", - "vdec", - "hif_sel", - "jpgdec", - "audio", - NULL, -}; - #define MAX_CLKS 3 /** @@ -116,7 +88,7 @@ enum clk_id { * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @bus_prot_mask: The mask for single step bus protection. - * @clk_id: The basic clocks required by this power domain. + * @basic_clk_name: The basic clocks required by this power domain. * @caps: The flag for active wake-up action. */ struct scp_domain_data { @@ -126,7 +98,7 @@ struct scp_domain_data { u32 sram_pdn_bits; u32 sram_pdn_ack_bits; u32 bus_prot_mask; - enum clk_id clk_id[MAX_CLKS]; + const char *basic_clk_name[MAX_CLKS]; u8 caps; }; @@ -411,12 +383,19 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) return ret; } -static void init_clks(struct platform_device *pdev, struct clk **clk) +static int init_basic_clks(struct platform_device *pdev, struct clk **clk, + const char * const *name) { int i; - for (i = CLK_NONE + 1; i < CLK_MAX; i++) - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]); + for (i = 0; i < MAX_CLKS && name[i]; i++) { + clk[i] = devm_clk_get(&pdev->dev, name[i]); + + if (IS_ERR(clk[i])) + return PTR_ERR(clk[i]); + } + + return 0; } static struct scp *init_scp(struct platform_device *pdev, @@ -426,9 +405,8 @@ static struct scp *init_scp(struct platform_device *pdev, { struct genpd_onecell_data *pd_data; struct resource *res; - int i, j; + int i, ret; struct scp *scp; - struct clk *clk[CLK_MAX]; scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); if (!scp) @@ -481,8 +459,6 @@ static struct scp *init_scp(struct platform_device *pdev, pd_data->num_domains = num; - init_clks(pdev, clk); - for (i = 0; i < num; i++) { struct scp_domain *scpd = &scp->domains[i]; struct generic_pm_domain *genpd = &scpd->genpd; @@ -493,17 +469,9 @@ static struct scp *init_scp(struct platform_device *pdev, scpd->data = data; - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { - struct clk *c = clk[data->clk_id[j]]; - - if (IS_ERR(c)) { - dev_err(&pdev->dev, "%s: clk unavailable\n", - data->name); - return ERR_CAST(c); - } - - scpd->clk[j] = c; - } + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name); + if (ret) + return ERR_PTR(ret); genpd->name = data->name; genpd->power_off = scpsys_power_off; @@ -560,7 +528,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_CONN_PWR_CON, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | MT2701_TOP_AXI_PROT_EN_CONN_S, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_DISP] = { @@ -568,7 +535,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -578,7 +545,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_VDEC] = { @@ -587,7 +554,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_ISP] = { @@ -596,7 +563,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_BDP] = { @@ -604,7 +571,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sta_mask = PWR_STATUS_BDP, .ctl_offs = SPM_BDP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_ETH] = { @@ -613,7 +579,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETH_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_HIF] = { @@ -622,14 +588,13 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_IFR_MSC] = { .name = "ifr_msc", .sta_mask = PWR_STATUS_IFR_MSC, .ctl_offs = SPM_IFR_MSC_PWR_CON, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -644,7 +609,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_VDEC] = { @@ -653,7 +618,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM, CLK_VDEC}, + .basic_clk_name = {"mm", "vdec"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_VENC] = { @@ -662,7 +627,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC}, + .basic_clk_name = {"mm", "venc", "jpgdec"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_ISP] = { @@ -671,7 +636,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_AUDIO] = { @@ -680,7 +645,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_AUDIO_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_AUDIO}, + .basic_clk_name = {"audio"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_USB] = { @@ -689,7 +654,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB_PWR_CON, .sram_pdn_bits = GENMASK(10, 8), .sram_pdn_ack_bits = GENMASK(14, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_USB2] = { @@ -698,7 +662,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB2_PWR_CON, .sram_pdn_bits = GENMASK(10, 8), .sram_pdn_ack_bits = GENMASK(14, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG] = { @@ -707,7 +670,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -717,7 +680,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x02c0, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG_SC2] = { @@ -726,7 +688,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x02c4, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG_SC3] = { @@ -735,7 +696,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x01f8, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -760,7 +720,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x300, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_VDEC}, + .basic_clk_name = {"vdec"}, }, [MT6797_POWER_DOMAIN_VENC] = { .name = "venc", @@ -768,7 +728,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x304, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_ISP] = { .name = "isp", @@ -776,7 +735,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x308, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_MM] = { .name = "mm", @@ -784,7 +742,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x30C, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = (BIT(1) | BIT(2)), }, [MT6797_POWER_DOMAIN_AUDIO] = { @@ -793,7 +751,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x314, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_MFG_ASYNC] = { .name = "mfg_async", @@ -801,7 +758,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x334, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, }, [MT6797_POWER_DOMAIN_MJC] = { .name = "mjc", @@ -809,7 +766,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x310, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_NONE}, }, }; @@ -834,7 +790,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETHSYS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -844,7 +799,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF0_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_HIFSEL}, + .basic_clk_name = {"hif_sel"}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -854,7 +809,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF1_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_HIFSEL}, + .basic_clk_name = {"hif_sel"}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -864,7 +819,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_WB_PWR_CON, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .clk_id = {CLK_NONE}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB, .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM, }, @@ -881,7 +835,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_CONN_PWR_CON, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | MT2701_TOP_AXI_PROT_EN_CONN_S, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_ETH] = { @@ -890,7 +843,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETH_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_HIF] = { @@ -899,14 +852,13 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_IFR_MSC] = { .name = "ifr_msc", .sta_mask = PWR_STATUS_IFR_MSC, .ctl_offs = SPM_IFR_MSC_PWR_CON, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -922,7 +874,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, }, [MT8173_POWER_DOMAIN_VENC] = { .name = "venc", @@ -930,7 +882,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC}, + .basic_clk_name = {"mm", "venc"}, }, [MT8173_POWER_DOMAIN_ISP] = { .name = "isp", @@ -938,7 +890,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, }, [MT8173_POWER_DOMAIN_MM] = { .name = "mm", @@ -946,7 +898,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | MT8173_TOP_AXI_PROT_EN_MM_M1, }, @@ -956,7 +908,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN2_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC_LT}, + .basic_clk_name = {"mm", "venc_lt"}, }, [MT8173_POWER_DOMAIN_AUDIO] = { .name = "audio", @@ -964,7 +916,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_AUDIO_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT8173_POWER_DOMAIN_USB] = { .name = "usb", @@ -972,7 +923,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT8173_POWER_DOMAIN_MFG_ASYNC] = { @@ -981,7 +931,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, }, [MT8173_POWER_DOMAIN_MFG_2D] = { .name = "mfg_2d", @@ -989,7 +939,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_2D_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_NONE}, }, [MT8173_POWER_DOMAIN_MFG] = { .name = "mfg", @@ -997,7 +946,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .clk_id = {CLK_NONE}, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | MT8173_TOP_AXI_PROT_EN_MFG_M0 | MT8173_TOP_AXI_PROT_EN_MFG_M1 | From patchwork Thu Aug 6 09:21:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A55A8C433FB for ; Thu, 6 Aug 2020 11:13:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D905222DFA for ; Thu, 6 Aug 2020 11:13:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Y3H2sHxr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729098AbgHFJcG (ORCPT ); Thu, 6 Aug 2020 05:32:06 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:51591 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729008AbgHFJWr (ORCPT ); Thu, 6 Aug 2020 05:22:47 -0400 X-UUID: ca487f489f414c2db250a778624f327c-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WTzfa/t8bk8sxGScWdoKmOhtLiKTTktmTscE+vpAf7A=; b=Y3H2sHxrdbxhUsv7i6HYTKbS3X042OhpO2CCpu0wA9AMhC712bvUHe2uc5i+i2OK1Jak8EZ2chZgeufiJLiBCTjuWEveiiFqyrWwTquyUkHCUqB5P22LB5JpKT3G4McQLnougvVnp7mo+vmM3VysHW15UqhJ2pF6N7H2UMY+RVM=; X-UUID: ca487f489f414c2db250a778624f327c-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1798099553; Thu, 06 Aug 2020 17:22:01 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:21:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:21:59 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 06/12] soc: mediatek: Add support for hierarchical scpsys device node Date: Thu, 6 Aug 2020 17:21:49 +0800 Message-ID: <1596705715-15320-7-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Try to list all the power domains of under power controller node to show the dependency between each power domain directly instead of filling the dependency in scp_soc_data. And could be more clearly to group subsys clocks into power domain sub node to introduce subsys clocks of bus protection in next patch. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 103 +++++++++++++++++++++++++++++++++++--- 1 file changed, 95 insertions(+), 8 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 5a2c323..502b66f 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -182,11 +182,13 @@ struct scp { struct regmap *infracfg; struct regmap *smi_common; struct scp_ctrl_reg ctrl_reg; + struct list_head dep_links; }; struct scp_subdomain { int origin; int subdomain; + struct list_head list; }; struct scp_soc_data { @@ -513,6 +515,79 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk, return 0; } +static int scpsys_get_domain_id(struct device_node *node, u32 *id) +{ + int ret; + + ret = of_property_read_u32(node, "reg", id); + if (ret) + pr_err("%pOFn: failed to retrieve domain id, ret=%d\n", node, ret); + + return ret; +} + +static int scpsys_get_domain(struct platform_device *pdev, struct scp *scp, + struct device_node *node, const struct scp_domain_data *data) +{ + struct scp_subdomain *dep_node; + struct device_node *sub; + u32 parent_id, child_id; + int ret; + + ret = scpsys_get_domain_id(node, &parent_id); + if (ret) + return ret; + + for_each_child_of_node(node, sub) { + ret = scpsys_get_domain_id(sub, &child_id); + if (ret) + goto out; + + dep_node = devm_kzalloc(&pdev->dev, sizeof(*dep_node), GFP_KERNEL); + if (!dep_node) { + ret = -ENOMEM; + goto out; + } + + dep_node->origin = parent_id; + dep_node->subdomain = child_id; + list_add(&dep_node->list, &scp->dep_links); + + scpsys_get_domain(pdev, scp, sub, data); + } + + return 0; + +out: + of_node_put(sub); + return ret; +} + +static int traverse_scp(struct platform_device *pdev, struct scp *scp, + const struct scp_domain_data *scp_domain_data) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *sub; + int ret; + + INIT_LIST_HEAD(&scp->dep_links); + + for_each_available_child_of_node(np, sub) { + ret = scpsys_get_domain(pdev, scp, sub, scp_domain_data); + if (ret) { + dev_err(&pdev->dev, "failed to handle node %pOFn: %d\n", sub, ret); + goto err; + } + } + + return 0; + +err: + of_node_put(sub); + return ret; +} + static struct scp *init_scp(struct platform_device *pdev, const struct scp_domain_data *scp_domain_data, int num, const struct scp_ctrl_reg *scp_ctrl_reg) @@ -582,6 +657,10 @@ static struct scp *init_scp(struct platform_device *pdev, pd_data->num_domains = num; + ret = traverse_scp(pdev, scp, scp_domain_data); + if (ret) + return ERR_PTR(ret); + for (i = 0; i < num; i++) { struct scp_domain *scpd = &scp->domains[i]; struct generic_pm_domain *genpd = &scpd->genpd; @@ -1208,7 +1287,7 @@ static int scpsys_probe(struct platform_device *pdev) const struct scp_soc_data *soc; struct scp *scp; struct genpd_onecell_data *pd_data; - int i, ret; + int i, ret = 0; soc = of_device_get_match_data(&pdev->dev); @@ -1220,15 +1299,23 @@ static int scpsys_probe(struct platform_device *pdev) pd_data = &scp->pd_data; - for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) { - ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin], - pd_data->domains[sd->subdomain]); - if (ret && IS_ENABLED(CONFIG_PM)) - dev_err(&pdev->dev, "Failed to add subdomain: %d\n", - ret); + if (soc->subdomains && soc->num_subdomains) { + for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) { + ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin], + pd_data->domains[sd->subdomain]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + } + } else { + list_for_each_entry(sd, &scp->dep_links, list) { + ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin], + pd_data->domains[sd->subdomain]); + if (ret && IS_ENABLED(CONFIG_PM)) + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + } } - return 0; + return ret; } static struct platform_driver scpsys_drv = { From patchwork Thu Aug 6 09:21:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6C3EC433ED for ; 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X-UUID: cffde7ae370a4f24a6aa521c9dd52791-20200806 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 866418727; Thu, 06 Aug 2020 17:22:03 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 08/12] soc: mediatek: Add extra sram control Date: Thu, 6 Aug 2020 17:21:51 +0800 Message-ID: <1596705715-15320-9-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 136E1D456467830D06C2796C988E92E6E87735DDE12877E946BEB67FF3B99FB22000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index ec62143..4587cef 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -26,6 +26,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -57,6 +58,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) @@ -290,6 +293,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr) return ret; } + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + } + return 0; } @@ -299,8 +310,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) u32 pdn_ack = scpd->data->sram_pdn_ack_bits; int tmp; - val = readl(ctl_addr); - val |= scpd->data->sram_pdn_bits; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + val &= ~PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + } + + val = readl(ctl_addr) | scpd->data->sram_pdn_bits; writel(val, ctl_addr); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ From patchwork Thu Aug 6 09:21:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org 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mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729167AbgHFJYU (ORCPT ); Thu, 6 Aug 2020 05:24:20 -0400 X-UUID: 16b02dde48cb49298c8399aeec0b9866-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=u6ZdwF8JM3tqVC2d724cXdyBA2VhdVfcqYAAPEwk01g=; b=hteQMjspiyvNRm3YgDEgWnvHJGCsKTwbYrp+Ad/lZKR6HkRJ8CiwbB7Q4Xe/zpuTCidHR6Q8S86ZvnlumiWTke5dd2znlLRRNmqUQtJdB6nqoY4F2tMCx19OI+hTl85TuYFV6rfweAZ0SlQ+tV6MFtg4Z7aA+3vlVZVYO25i43c=; X-UUID: 16b02dde48cb49298c8399aeec0b9866-20200806 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 34936211; Thu, 06 Aug 2020 17:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 09/12] soc: mediatek: Add MT8183 scpsys support Date: Thu, 6 Aug 2020 17:21:52 +0800 Message-ID: <1596705715-15320-10-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 229 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) -- 1.8.1.1.dirty diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 4587cef..9a699b4 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -20,6 +20,7 @@ #include #include #include +#include #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -100,6 +101,34 @@ #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) +#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14)) +#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22)) +#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28) +#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27) +#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17)) +#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8)) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \ + BIT(9) | BIT(13)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \ + BIT(12)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \ + BIT(4)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \ + BIT(5)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7) +#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0) +#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1) +#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2) +#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7) + #define MAX_CLKS 3 #define MAX_SUBSYS_CLKS 10 @@ -1246,6 +1275,194 @@ static void mtk_register_power_domains(struct platform_device *pdev, {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; +/* + * MT8183 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .basic_clk_name = {"audio", "audio1", "audio2"}, + }, + [MT8183_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_CONN), + }, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_name = {"mfg"}, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .name = "mfg_core1", + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + MT8183_TOP_AXI_PROT_EN_1_MFG), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_MFG), + }, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"mm"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + MT8183_TOP_AXI_PROT_EN_1_DISP), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_DISP), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_DISP), + }, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"cam"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_CAM), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_CAM), + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_CAM), + }, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"isp"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_ISP), + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_ISP), + }, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VDEC), + }, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VENC), + }, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .name = "vpu_top", + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"vpu", "vpu1"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_VPU_TOP), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .name = "vpu_core0", + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"vpu2"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .name = "vpu_core1", + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"vpu3"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -1306,6 +1523,15 @@ static void mtk_register_power_domains(struct platform_device *pdev, }, }; +static const struct scp_soc_data mt8183_data = { + .domains = scp_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183), + .regs = { + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 + } +}; + /* * scpsys driver init */ @@ -1330,6 +1556,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, }, { + .compatible = "mediatek,mt8183-scpsys", + .data = &mt8183_data, + }, { /* sentinel */ } }; From patchwork Thu Aug 6 09:21:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13B41C38145 for ; Thu, 6 Aug 2020 11:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A57922D02 for ; Thu, 6 Aug 2020 11:13:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z4lOVlI1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729047AbgHFJcW (ORCPT ); Thu, 6 Aug 2020 05:32:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38463 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729028AbgHFJWr (ORCPT ); Thu, 6 Aug 2020 05:22:47 -0400 X-UUID: e2bfd24346744ad49390cd1416a776bf-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vyt/5VZetwvfAg/d0ebCsFaxhaPADW7wXGw7LIYUkgE=; b=Z4lOVlI1B0ZYu91KgzvOWOPQZPBNJaZOhyfbdXUagsJoCpaHabDR+Y7PMwXsYRKWNKL0hkUCCdIYg9BfqgVAnwdurtTy0TPWJOkhL7xDDnT+G/bvRKcPCItE1L2dKWewZ44XfA/FE1RjMMDsECoFK9Pek+FFOZRC2/zTI/7e73U=; X-UUID: e2bfd24346744ad49390cd1416a776bf-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 900334158; Thu, 06 Aug 2020 17:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 11/12] arm64: dts: Add power controller device node of MT8183 Date: Thu, 6 Aug 2020 17:21:54 +0800 Message-ID: <1596705715-15320-12-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add power controller node and smi-common node for MT8183 In scpsys node, it contains clocks and regmapping of infracfg and smi-common for bus protection. And list all the power domains of MT8183 under scpsys node to show the dependency between each other through hierarchical structure. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) -- 1.8.1.1.dirty diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c84..4940bda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mt8183-pinfunc.h" @@ -309,6 +310,123 @@ #interrupt-cells = <2>; }; + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8183-scpsys", "syscon"; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_MM>, + <&topckgen CLK_TOP_MUX_CAM>, + <&topckgen CLK_TOP_MUX_IMG>, + <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&topckgen CLK_TOP_MUX_DSP1>, + <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "audio", "audio1", "audio2", "mfg", "mm", + "cam", "isp", "vpu", "vpu1", "vpu2", + "vpu3"; + infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + audio@MT8183_POWER_DOMAIN_AUDIO { + reg = ; + }; + + conn@MT8183_POWER_DOMAIN_CONN { + reg = ; + }; + + mfg_async@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg@MT8183_POWER_DOMAIN_MFG { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg_core0@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = ; + }; + + mfg_core1@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = ; + }; + + mfg_2d@MT8183_POWER_DOMAIN_MFG_2D { + reg = ; + }; + }; + }; + + disp@MT8183_POWER_DOMAIN_DISP { + reg = ; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + #address-cells = <1>; + #size-cells = <0>; + + cam@MT8183_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + }; + + isp@MT8183_POWER_DOMAIN_ISP { + reg = ; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + }; + + vdec@MT8183_POWER_DOMAIN_VDEC { + reg = ; + }; + + vden@MT8183_POWER_DOMAIN_VENC { + reg = ; + }; + + vpu_top@MT8183_POWER_DOMAIN_VPU_TOP { + reg = ; + clocks = <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + #address-cells = <1>; + #size-cells = <0>; + + vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = ; + }; + + vpu_core1@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = ; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; @@ -690,6 +808,11 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; From patchwork Thu Aug 6 09:21:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3156CC433F4 for ; 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X-UUID: d5e00c944d6e4ea8bf89776256ce0a6c-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 675302145; Thu, 06 Aug 2020 17:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 12/12] arm64: dts: Add power-domains property to mfgcfg Date: Thu, 6 Aug 2020 17:21:55 +0800 Message-ID: <1596705715-15320-13-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org mfgcfg clock is under MFG_ASYNC power domain Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+) -- 1.8.1.1.dirty diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4940bda..43db225 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -800,6 +800,7 @@ compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; #clock-cells = <1>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>; }; mmsys: syscon@14000000 {