From patchwork Wed Aug 19 11:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 253626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A24ECC433E5 for ; Wed, 19 Aug 2020 11:58:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78CC72072D for ; Wed, 19 Aug 2020 11:58:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597838282; bh=KR3x17k71nv+WZsdM0NYFQMSokf99W1AI+fOHiCMtjI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=HT8wnNPfkhbvKMdKf6QY1ZVfr071FIlrIQBSYcggWR9ZSwpIO9tivpx8kvUlwLLVN Lr+EUARGKHyVoFAkA21LBvnOCKMwPbbdUMbjSASTzUMUnVaC9oG99eiu0nmtQsBzxk MCQdhwmYyVEcRKnu3pr+iXh0HumA2onwmOtsZLAs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728382AbgHSL5D (ORCPT ); Wed, 19 Aug 2020 07:57:03 -0400 Received: from mail.kernel.org ([198.145.29.99]:47176 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728286AbgHSLtZ (ORCPT ); Wed, 19 Aug 2020 07:49:25 -0400 Received: from mail.kernel.org (ip5f5ad5a3.dynamic.kabel-deutschland.de [95.90.213.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A66812312B; Wed, 19 Aug 2020 11:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837583; bh=KR3x17k71nv+WZsdM0NYFQMSokf99W1AI+fOHiCMtjI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RdLMUM5Xi0M4wIe5eMeYRspaUaTagbNp3+Uu62CwqGQPWf8JjCegMi5LugjYO3zCF KalT+ThEuqx3+7rcbxyYXE9e33yLI2Q4izRGfHmxqwvnUETV97KsnkrgS+IlhWkrCN 0dmmb0hjrfOi15lbpcWXhj50V7rrObFuZWYIHchs= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00Euc5-JA; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , John Stultz , Manivannan Sadhasivam , Daniel Vetter , dri-devel , Wei Xu , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 44/49] dts: hisilicon: hi3670.dtsi: add I2C settings Date: Wed, 19 Aug 2020 13:46:12 +0200 Message-Id: <577acc4d4de8f812d4f58de167a731bfc6d1d32e.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b1acb4fb1d1c..416f69c782d7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -723,5 +723,76 @@ dwmmc2: dwmmc2@fc183000 { card-detect-delay = <200>; status = "disabled"; }; + + /* I2C */ + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@ffd73000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd73000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C2>; + resets = <&iomcu_rst 0x20 5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c4: i2c@fdf0d000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0d000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>; + resets = <&crg_rst 0x78 27>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>; + status = "disabled"; + }; }; }; From patchwork Wed Aug 19 11:46:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 253627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0605C433E1 for ; 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Wed, 19 Aug 2020 11:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837583; bh=+UhVBmbMj6lt2RenvveVdDhvKup+dtdi1C8Rlc5YXQc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gn3Rncg45FO46KGjrWfViln7lPI6scjaw6Qi6P1iGD4a5UGpsXydDEzVtlW1Xnnea sAjfuFU3NP3g/vxFtalAyXJqGAO4dWPjJVL/MCkcpbCJJ3PwcXBVpZvcpMsBs7JeGg GQuKo+Tp58wJSDZOU3q+Fl1D7NltMAf5XLGeEnUI= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00EucA-LD; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , John Stultz , Manivannan Sadhasivam , Daniel Vetter , dri-devel , Wei Xu , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 46/49] dt: hisilicon: add support for the PMIC found on Hikey 970 Date: Wed, 19 Aug 2020 13:46:14 +0200 Message-Id: <9df854e76bedc8726c634dee213f4520b6449b1e.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a device tree for the HiSilicon 6421v600 SPMI PMIC, used on HiKey970 board. As we now have support for it, change the fixed regulators used by the SD I/O to use the proper LDO supplies. Signed-off-by: Mauro Carvalho Chehab --- .../boot/dts/hisilicon/hi3670-hikey970.dts | 22 +- .../boot/dts/hisilicon/hikey970-pmic.dtsi | 197 ++++++++++++++++++ 2 files changed, 200 insertions(+), 19 deletions(-) create mode 100644 arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 01234a175dcd..a9ad90e769ad 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -12,6 +12,7 @@ #include "hi3670.dtsi" #include "hikey970-pinctrl.dtsi" +#include "hikey970-pmic.dtsi" / { model = "HiKey970"; @@ -39,23 +40,6 @@ memory@0 { reg = <0x0 0x0 0x0 0x0>; }; - sd_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - wlan_en: wlan-en-1-8v { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; @@ -402,8 +386,8 @@ &dwmmc1 { pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; - vmmc-supply = <&sd_3v3>; - vqmmc-supply = <&sd_1v8>; + vmmc-supply = <&ldo16>; + vqmmc-supply = <&ldo9>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi new file mode 100644 index 000000000000..843e841c7371 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hi6421v600 SPMI PMIC used at the HiKey970 Development Board + * + * Copyright (C) 2020, Huawei Tech. Co., Ltd. + */ + +#include + +/ { + spmi: spmi@fff24000 { + compatible = "hisilicon,kirin970-spmi-controller"; + #address-cells = <2>; + #size-cells = <0>; + status = "ok"; + reg = <0x0 0xfff24000 0x0 0x1000>; + spmi-channel = <2>; + + pmic: pmic@0 { + compatible = "hisilicon,hi6421-spmi"; + reg = <0 SPMI_USID>; + + #interrupt-cells = <2>; + interrupt-controller; + gpios = <&gpio28 0 0>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + ldo3: ldo3@16 { + reg = <0x16>; + vsel-reg = <0x51>; + + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + + enable-mask = <0x01>; + + voltage-table = <1500000>, <1550000>, + <1600000>, <1650000>, + <1700000>, <1725000>, + <1750000>, <1775000>, + <1800000>, <1825000>, + <1850000>, <1875000>, + <1900000>, <1925000>, + <1950000>, <2000000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo4: ldo4@17 { /* 40 PIN */ + reg = <0x17>; + vsel-reg = <0x52>; + + regulator-name = "ldo4"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + hi6421-vsel = <0x52 0x07>; + voltage-table = <1725000>, <1750000>, + <1775000>, <1800000>, + <1825000>, <1850000>, + <1875000>, <1900000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo9: ldo9@1C { /* SDCARD I/O */ + reg = <0x1C>; + vsel-reg = <0x57>; + + regulator-name = "ldo9"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1750000>, <1800000>, + <1825000>, <2800000>, + <2850000>, <2950000>, + <3000000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <360>; + }; + + ldo15: ldo15@21 { /* UFS */ + reg = <0x21>; + vsel-reg = <0x5c>; + + regulator-name = "ldo15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1800000>, <1850000>, + <2400000>, <2600000>, + <2700000>, <2850000>, + <2950000>, <3000000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo16: ldo16@22 { /* SD */ + reg = <0x22>; + vsel-reg = <0x5d>; + + regulator-name = "ldo16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1800000>, <1850000>, + <2400000>, <2600000>, + <2700000>, <2850000>, + <2950000>, <3000000>; + off-on-delay-us = <20000>; + startup-delay-us = <360>; + }; + + ldo17: ldo17@23 { + reg = <0x23>; + vsel-reg = <0x5e>; + + regulator-name = "ldo17"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <2500000>, <2600000>, + <2700000>, <2800000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo33: ldo33@32 { /* PEX8606 */ + reg = <0x32>; + vsel-reg = <0x6d>; + regulator-name = "ldo33"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + enable-mask = <0x01>; + + voltage-table = <2500000>, <2600000>, + <2700000>, <2800000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo34: ldo34@33 { /* GPS AUX IN VDD */ + reg = <0x33>; + vsel-reg = <0x6e>; + + regulator-name = "ldo34"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + + enable-mask = <0x01>; + + voltage-table = <2600000>, <2700000>, + <2800000>, <2900000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + }; + }; + }; +}; From patchwork Wed Aug 19 11:46:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 253628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65FB2C433DF for ; Wed, 19 Aug 2020 11:57:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30EB02072D for ; Wed, 19 Aug 2020 11:57:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597838227; bh=0s3pmtILVSiuI77kiYarCgl3FUbdNZSJJENxk4HNs1c=; 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b=XPoNKr4UNTqnAzpnnXX0ra1UVzx27ph7DOeQ7Lxg7GLPBzAJk+TZgZwglUIovjO2C Ox4rol4IoNMRrIBPrZttvUxhNAQeUcTpgYcArKxrbQqhv+FTLNfCzOp3uPn61YI22K D9se5drVv7bB9w8L2f0tMtFoW2knYrdC4sR1YRZo= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00EucG-PZ; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , John Stultz , Manivannan Sadhasivam , Daniel Vetter , dri-devel , David Airlie , Rob Herring , Wei Xu , Alexei Starovoitov , Daniel Borkmann , "David S. Miller" , Jakub Kicinski , Jesper Dangaard Brouer , John Fastabend , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 49/49] dt: display: Add binds for the DPE and DSI controller for Kirin 960/970 Date: Wed, 19 Aug 2020 13:46:17 +0200 Message-Id: <6471642f74779fecfc9d5e990d90f9475d8b32d4.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a description of the bindings used by Kirin 960/970 Display Serial Interface (DSI) controller and by its Display Engine (DPE). Signed-off-by: Mauro Carvalho Chehab --- .../display/hisilicon,hi3660-dpe.yaml | 99 +++++++++++++++++ .../display/hisilicon,hi3660-dsi.yaml | 102 ++++++++++++++++++ .../boot/dts/hisilicon/hikey970-drm.dtsi | 4 +- 3 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml new file mode 100644 index 000000000000..074997354417 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dpe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Engine (DPE) s the display controller which grab + image data from memory, do composition, do post image processing, + generate RGB timing stream and transfer to DSI. + +properties: + $nodename: + pattern: "dpe@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dpe + - hisilicon,kirin970-dpe + + reg: + minItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + description: Clocks used by the ISP and by the display + + clock-names: + description: Names for the clock lines + + dma-coherent: true + + port: + type: object + description: A port node pointing to the display output endpoint. + + + iommu-info: + type: object + description: IOMMU address and size to be used by GPU + + properties: + start-addr: + const: start address for IOMMU + size: + const: size of the mapped region + +examples: + - | + dpe: dpe@e8600000 { + compatible = "hisilicon,kirin970-dpe"; + memory-region = <&drm_dma_reserved>; + reg = <0 0xE8600000 0 0xC0000>, + <0 0xFFF35000 0 0x1000>, + <0 0xFFF0A000 0 0x1000>, + <0 0xE8A09000 0 0x1000>, + <0 0xE86C0000 0 0x10000>, + <0 0xFFF31000 0 0x1000>, + <0 0xE87FF000 0 0x1000>; + + interrupts = <0 245 4>; + + clocks = <&media1_crg HI3670_ACLK_GATE_DSS>, + <&media1_crg HI3670_PCLK_GATE_DSS>, + <&media1_crg HI3670_CLK_GATE_EDC0>, + <&media1_crg HI3670_CLK_GATE_LDI0>, + <&media1_crg HI3670_CLK_GATE_DSS_AXI_MM>, + <&media1_crg HI3670_PCLK_GATE_MMBUF>, + <&crg_ctrl HI3670_PCLK_GATE_PCTRL>; + + clock-names = "aclk_dss", + "pclk_dss", + "clk_edc0", + "clk_ldi0", + "clk_dss_axi_mm", + "pclk_mmbuf", + "pclk_pctrl"; + + dma-coherent; + + port { + dpe_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + + iommu_info { + start-addr = <0x8000>; + size = <0xbfff8000>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml new file mode 100644 index 000000000000..2265267fc53d --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Serial Interface (DSI) Host Controller for + Kirin 960 and 970 resides in the middle of display controller and + an external HDMI converter or panel. + +properties: + $nodename: + pattern: "dsi@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dsi + - hisilicon,kirin970-dsi + + reg: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 1 + maxItems: 8 + description: Clocks used by the ISP and by the display. + + clock-names: + description: Names for the clock lines. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + mux-gpio: + description: GPIO used by the mux. + + ports: + type: object + description: Display input and output ports. + +examples: + - | + dsi: dsi@e8601000 { + compatible = "hisilicon,kirin970-dsi"; + reg = <0 0xE8601000 0 0x7F000>, + <0 0xFFF35000 0 0x1000>, + <0 0xE8A09000 0 0x1000>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_CFG>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_CFG>, + <&crg_ctrl HI3670_PCLK_GATE_DSI0>, + <&crg_ctrl HI3670_PCLK_GATE_DSI1>; + clock-names = "clk_txdphy0_ref", + "clk_txdphy1_ref", + "clk_txdphy0_cfg", + "clk_txdphy1_cfg", + "pclk_dsi0", + "pclk_dsi1"; + + #address-cells = <1>; + #size-cells = <0>; + mux-gpio = <&gpio25 7 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dpe_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi index 503c7c9425c8..5758d7d181e5 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 / { - dpe: dpe@E8600000 { + dpe: dpe@e8600000 { compatible = "hisilicon,kirin970-dpe"; memory-region = <&drm_dma_reserved>; // DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG @@ -44,7 +44,7 @@ iommu_info { }; }; - dsi: dsi@E8601000 { + dsi: dsi@e8601000 { compatible = "hisilicon,kirin970-dsi"; reg = <0 0xE8601000 0 0x7F000>, <0 0xFFF35000 0 0x1000>,