From patchwork Thu Aug 20 01:03:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 253596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4988C433E4 for ; Thu, 20 Aug 2020 01:03:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74001207FB for ; Thu, 20 Aug 2020 01:03:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="kdz17yaM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726603AbgHTBDp (ORCPT ); Wed, 19 Aug 2020 21:03:45 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45442 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726578AbgHTBDm (ORCPT ); Wed, 19 Aug 2020 21:03:42 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 07K13cEC053563; Wed, 19 Aug 2020 20:03:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1597885418; bh=WOzi/0IGVTVWFmjd5KggPQLL88A+j8XkzXr6Lfyzh2U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kdz17yaMsIkEaL9NzGWXZzJDP9acgD7HoA7GHLB56Th60TstrBsvHsFJOXyVfsNdg baWgYnEkI3DQOXh2vZLsfJVj7DqUI+eZPmT7D0PcIFqq6m8Qna7Pzp72Qjv9pC1YZu Xss1zpKPmz81ECoaGsaP/IVFsT+qWFmvNAMW+9IQ= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 07K13cER097661 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Aug 2020 20:03:38 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 19 Aug 2020 20:03:37 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 19 Aug 2020 20:03:37 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13bhm011203; Wed, 19 Aug 2020 20:03:37 -0500 Received: from localhost ([10.250.32.29]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 07K13b3e022533; Wed, 19 Aug 2020 20:03:37 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: , , Suman Anna Subject: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs Date: Wed, 19 Aug 2020 20:03:26 -0500 Message-ID: <20200820010331.2911-3-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> References: <20200820010331.2911-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the required 'mboxes' property to both the C66x DSP processors on the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e8fc01d97ada..ff541dc09eca 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -379,6 +379,14 @@ &mailbox0_cluster11 { status = "disabled"; }; +&c66_0 { + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; +}; + +&c66_1 { + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; +}; + &main_sdhci0 { /* eMMC */ non-removable; From patchwork Thu Aug 20 01:03:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 253597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB0B9C433DF for ; Thu, 20 Aug 2020 01:03:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93951207FB for ; Thu, 20 Aug 2020 01:03:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="csO53jHz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726617AbgHTBDn (ORCPT ); Wed, 19 Aug 2020 21:03:43 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38740 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726482AbgHTBDl (ORCPT ); Wed, 19 Aug 2020 21:03:41 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 07K13d5T125144; Wed, 19 Aug 2020 20:03:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1597885419; bh=GYG4JVlApvrMTjS203hyiYPDg7cuscl92nUwKDEyVck=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=csO53jHz7VRpDYrBM9Z93kC9EjQn9lJbGkuMlbJFJ6+Q/X/qVt/OiJeqpaGlrTT5B COpicCLqYpSaR0BYCAxQ08696Re5bvPbmNgeDNyO7o1e+1AfEE8PR5rkvOTSjBCRHe QPj3+lWkZpYfMckDo142ZGk6xujw9nTDQrXaL6sY= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13dYT064948; Wed, 19 Aug 2020 20:03:39 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 19 Aug 2020 20:03:38 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 19 Aug 2020 20:03:38 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13ctI121591; Wed, 19 Aug 2020 20:03:38 -0500 Received: from localhost ([10.250.32.29]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 07K13cBp022537; Wed, 19 Aug 2020 20:03:38 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: , , Suman Anna Subject: [PATCH 3/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs Date: Wed, 19 Aug 2020 20:03:27 -0500 Message-ID: <20200820010331.2911-4-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> References: <20200820010331.2911-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Two carveout reserved memory nodes each have been added for each of the C66x DSP remote processor devices present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc devices, and the second region will furnish the static carveout regions for the firmware memory. The minimum granularity on the Cache settings on C66x DSP cores is 16 MB, so the DMA memory regions are chosen such that they are in separate 16 MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts. The current carveout addresses and sizes are defined statically for each device. The C66x DSP processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 34 +++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8fa3361e5e45..f1a8190e3b5a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -25,6 +25,30 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -72,3 +96,13 @@ flash@0{ #size-cells = <1>; }; }; + +&c66_0 { + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; From patchwork Thu Aug 20 01:03:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 253595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA0E9C433DF for ; Thu, 20 Aug 2020 01:03:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8219E207DA for ; Thu, 20 Aug 2020 01:03:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="R/yWMebw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726362AbgHTBDr (ORCPT ); Wed, 19 Aug 2020 21:03:47 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:36460 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726482AbgHTBDo (ORCPT ); Wed, 19 Aug 2020 21:03:44 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 07K13fVr119179; Wed, 19 Aug 2020 20:03:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1597885421; bh=x0k8xeCLis1DyQpNBVsG18vcpLEXm4cK+kWAkYgyze4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R/yWMebwTAGUKdeOWocphXI891aoU0g0W8rX5LrPJ+JWms1BTsrBAgWjcWQuEcRaV FHmGhucSXtCJd1u5CF7miEnrEgFJ3T9+d6qydo6ykSKaVsTp91OClnEau+QZTNO6ZP IYqxQPG73xsDVTupVfg5YvJmioebI3CzCrrfOCtc= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 07K13fej115766 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Aug 2020 20:03:41 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 19 Aug 2020 20:03:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 19 Aug 2020 20:03:40 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13eDJ009804; Wed, 19 Aug 2020 20:03:40 -0500 Received: from localhost ([10.250.32.29]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 07K13e84022551; Wed, 19 Aug 2020 20:03:40 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: , , Suman Anna Subject: [PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP Date: Wed, 19 Aug 2020 20:03:30 -0500 Message-ID: <20200820010331.2911-7-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> References: <20200820010331.2911-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Two carveout reserved memory nodes have been added for the lone C71x DSP remote processor device present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device node as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images currently do not need any RSC_CARVEOUT entries either in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the C71x DSP remoteproc processor. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index f1a8190e3b5a..600586cc22e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 { reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -106,3 +118,8 @@ &c66_1 { memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; + +&c71_0 { + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; From patchwork Thu Aug 20 01:03:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 253594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6614C433E8 for ; Thu, 20 Aug 2020 01:03:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9705D207DA for ; Thu, 20 Aug 2020 01:03:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UdPnw24s" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726673AbgHTBDs (ORCPT ); Wed, 19 Aug 2020 21:03:48 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38750 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726681AbgHTBDp (ORCPT ); Wed, 19 Aug 2020 21:03:45 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 07K13gMs125158; Wed, 19 Aug 2020 20:03:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1597885422; bh=fuqtcibFyfAnfIPJv9eRt9tO38sIyYu+EZMympBdU8I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UdPnw24s/7CfVlNOOPLX0WqQM2WRRlj8KyuF/mTTdAqqqyzLD7oKBsp3yTfuVW0Qv EEsSkSJ2JjlnDl6O3wSNfcGxEyf13mRVIjqBWWrxN3hlmK31EZqCw9E+60AZZEf+fP dAnLpazun1rWhNRu/EFVsA86de+9vG9u0dRRKZ5s= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13gfQ064989; Wed, 19 Aug 2020 20:03:42 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 19 Aug 2020 20:03:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 19 Aug 2020 20:03:41 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07K13fQk121623; Wed, 19 Aug 2020 20:03:41 -0500 Received: from localhost ([10.250.32.29]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 07K13fiF022556; Wed, 19 Aug 2020 20:03:41 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: , , Suman Anna Subject: [PATCH 7/7] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores Date: Wed, 19 Aug 2020 20:03:31 -0500 Message-ID: <20200820010331.2911-8-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> References: <20200820010331.2911-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS on the TI J721E EVM boards. 28 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 600586cc22e5..d30a06248027 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -61,6 +61,12 @@ c71_0_memory_region: c71-memory@a8100000 { reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; };