From patchwork Thu Aug 27 07:20:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 253318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF320C433E1 for ; Thu, 27 Aug 2020 07:21:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8DC322BEA for ; Thu, 27 Aug 2020 07:21:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="F29YgNNl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728027AbgH0HVf (ORCPT ); Thu, 27 Aug 2020 03:21:35 -0400 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:22030 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727839AbgH0HVc (ORCPT ); Thu, 27 Aug 2020 03:21:32 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07R7HlT7013427; Thu, 27 Aug 2020 09:21:19 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=KQ+9yJUzemMWVFCVMFRX7+xLDsvlII1rDD1EoRBdZsw=; b=F29YgNNl3PbFfdfhnPmZPy3O97AqOiU6gnw1thd3npR26u+hmxW7+fuaYkyGH21oCPMM T1dYz+o4fF9zxKtSM155dGj1OuoUmf2Eme5YLTiuYOMV27HH85/nDGsoxfuo2nEQJFKP aSiNPwsoirxdpAupCBUa/ygF8cqmmXThgJUj/FFGJO6wvO/vz9/KlLewNoQvB2gdc2SP 1/CcXA/Ft4s0vWbI/bMNFi6xJgwohLExE3+XMFX6jNEhG+zWEWQht6aljwTOdETPkoFp wN4BEtNg+KmXoE1xpCB5FO0v6kFiBDkDgYp4yUhMRULHnF7X3BGsdZkU3AymzykWhOzF 3Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 333b2mvfux-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 09:21:19 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4DC20100034; Thu, 27 Aug 2020 09:21:19 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3D050212648; Thu, 27 Aug 2020 09:21:19 +0200 (CEST) Received: from localhost (10.75.127.46) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 27 Aug 2020 09:21:18 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Fabien Dessenne , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson Subject: [PATCH 1/3] dt-bindings: arm: stm32: Add compatible for syscon tamp node Date: Thu, 27 Aug 2020 09:20:59 +0200 Message-ID: <20200827072101.26588-2-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200827072101.26588-1-arnaud.pouliquen@st.com> References: <20200827072101.26588-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_02:2020-08-27,2020-08-27 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32 SoC to support TAMP registers access. Signed-off-by: Arnaud Pouliquen --- Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f1cd0103c74..6634b3e0853e 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -19,6 +19,7 @@ properties: - st,stm32mp151-pwr-mcu - st,stm32-syscfg - st,stm32-power-config + - st,stm32-tamp - const: syscon reg: From patchwork Thu Aug 27 07:21:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 253317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50B78C433E3 for ; Thu, 27 Aug 2020 07:21:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 26DE622CB2 for ; Thu, 27 Aug 2020 07:21:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="SZltyI84" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728074AbgH0HVp (ORCPT ); Thu, 27 Aug 2020 03:21:45 -0400 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:22016 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726882AbgH0HVd (ORCPT ); Thu, 27 Aug 2020 03:21:33 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07R7Ho8j013608; Thu, 27 Aug 2020 09:21:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=9bTCitwnBAltRZQ7gOYLHIo8QHxlqk1VrxB1btIyl3k=; b=SZltyI84G5I3H89Zdo7KZ/TXsfPszKhCDxsNzPo5pVtE6yxVAOo1aNf45b7GHE6b/ZJQ 3ko/Hyx+2Ghn4Iv4Yx7006IPxHHOFxdCLpbJwcWe4MP/vJHmancbJGKftoMk3w4p8T2L nQXlH9ugTxMfZGyIR5T/nEfa9Ps9WvEJFt820mjWeqfSEbH+xsTceHiQCc3T+ngioGhp h8vfNSV0jymM/30WYOgci71fFvx7R7I+oFhhorZ+BNy8z9uo47nzyLygac9F/YqcdeW2 TMBj1kp41XelvDEREmqZus7i5zJaVwmWxaG5iGuy1QceWn6ZFDlVQkQ8712+9aU8saf6 aw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 333b2mvfv6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 09:21:23 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 87C5610002A; Thu, 27 Aug 2020 09:21:21 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7A770212648; Thu, 27 Aug 2020 09:21:21 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 27 Aug 2020 09:21:20 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Fabien Dessenne , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson Subject: [PATCH 3/3] ARM: dts: stm32: update stm32mp151 for remote proc synchronisation support Date: Thu, 27 Aug 2020 09:21:01 +0200 Message-ID: <20200827072101.26588-4-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200827072101.26588-1-arnaud.pouliquen@st.com> References: <20200827072101.26588-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_02:2020-08-27,2020-08-27 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Two backup registers are used to store the Cortex-M4 state and the resource table address. Declare the tamp node and add associated properties in m4_rproc node to allow Linux to attach to a firmware loaded by the first boot stages. Associated driver implementation is available in commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation"). Signed-off-by: Arnaud Pouliquen --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bfe29023fbd5..842ecffae73a 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1541,6 +1541,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1717,6 +1722,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; };