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Thu, 27 Aug 2020 18:16:52 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Thu, 27 Aug 2020 18:16:52 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 07RGGqC6031819; Thu, 27 Aug 2020 18:16:52 +0200 Received: (from sjakhade@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 07RGGq54031818; Thu, 27 Aug 2020 18:16:52 +0200 From: Swapnil Jakhade To: , , , , , CC: , , , , , Subject: [PATCH v2 01/13] phy: cadence-torrent: Add single link PCIe support Date: Thu, 27 Aug 2020 18:16:39 +0200 Message-ID: <1598545011-31772-2-git-send-email-sjakhade@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1598545011-31772-1-git-send-email-sjakhade@cadence.com> References: <1598545011-31772-1-git-send-email-sjakhade@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f1d88505-0355-465e-227f-08d84aa49f01 X-MS-TrafficTypeDiagnostic: BY5PR07MB6593: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:74; 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DIR:OUT; SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2020 16:16:57.4629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1d88505-0355-465e-227f-08d84aa49f01 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[199.43.4.23]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM12FT040.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR07MB6593 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_08:2020-08-27,2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 bulkscore=0 mlxlogscore=990 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270120 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add single link PCIe register sequences in Torrent PHY driver. Also, add support for getting SSC type from DT. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 296 +++++++++++++++++++--- 1 file changed, 266 insertions(+), 30 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index ed2140691077..fcd1a2617f0a 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -28,6 +28,9 @@ #define MAX_NUM_LANES 4 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ +#define NUM_SSC_MODE 3 +#define NUM_PHY_TYPE 2 + #define POLL_TIMEOUT_US 5000 #define TORRENT_COMMON_CDB_OFFSET 0x0 @@ -98,6 +101,14 @@ #define CMN_PLL0_LOCK_REFCNT_START 0x009CU #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU +#define CMN_PLL0_INTDIV_M1 0x00A0U +#define CMN_PLL0_FRACDIVH_M1 0x00A2U +#define CMN_PLL0_HIGH_THR_M1 0x00A3U +#define CMN_PLL0_DSM_DIAG_M1 0x00A4U +#define CMN_PLL0_SS_CTRL1_M1 0x00A8U +#define CMN_PLL0_SS_CTRL2_M1 0x00A9U +#define CMN_PLL0_SS_CTRL3_M1 0x00AAU +#define CMN_PLL0_SS_CTRL4_M1 0x00ABU #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U @@ -130,8 +141,10 @@ #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U +#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U +#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U @@ -162,6 +175,9 @@ #define RX_REE_GCSM1_CTRL 0x0108U #define RX_REE_GCSM2_CTRL 0x0110U #define RX_REE_PERGCSM_CTRL 0x0118U +#define RX_REE_TAP1_CLIP 0x0171U +#define RX_REE_TAP2TON_CLIP 0x0172U +#define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ #define PHY_PLL_CFG 0x000EU @@ -182,12 +198,24 @@ static const struct reg_field phy_pma_pll_raw_ctrl = static const struct reg_field phy_reset_ctrl = REG_FIELD(PHY_RESET, 8, 8); +enum cdns_torrent_phy_type { + TYPE_DP, + TYPE_PCIE +}; + +enum cdns_torrent_ssc_mode { + NO_SSC, + EXTERNAL_SSC, + INTERNAL_SSC +}; + struct cdns_torrent_inst { struct phy *phy; u32 mlane; - u32 phy_type; + enum cdns_torrent_phy_type phy_type; u32 num_lanes; struct reset_control *lnk_rst; + enum cdns_torrent_ssc_mode ssc_mode; }; struct cdns_torrent_phy { @@ -221,8 +249,9 @@ enum phy_powerstate { POWERSTATE_A3 = 3, }; +static int cdns_torrent_phy_init(struct phy *phy); +static int cdns_torrent_phy_exit(struct phy *phy); static int cdns_torrent_dp_init(struct phy *phy); -static int cdns_torrent_dp_exit(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes); static @@ -252,17 +281,30 @@ static int cdns_torrent_phy_on(struct phy *phy); static int cdns_torrent_phy_off(struct phy *phy); static const struct phy_ops cdns_torrent_phy_ops = { - .init = cdns_torrent_dp_init, - .exit = cdns_torrent_dp_exit, + .init = cdns_torrent_phy_init, + .exit = cdns_torrent_phy_exit, .configure = cdns_torrent_dp_configure, .power_on = cdns_torrent_phy_on, .power_off = cdns_torrent_phy_off, .owner = THIS_MODULE, }; +struct cdns_reg_pairs { + u32 val; + u32 off; +}; + +struct cdns_torrent_vals { + struct cdns_reg_pairs *reg_pairs; + u32 num_regs; +}; + struct cdns_torrent_data { - u8 block_offset_shift; - u8 reg_offset_shift; + u8 block_offset_shift; + u8 reg_offset_shift; + struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; + struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; + struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; }; struct cdns_regmap_cdb_context { @@ -846,19 +888,6 @@ static int cdns_torrent_dp_init(struct phy *phy) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; - ret = clk_prepare_enable(cdns_phy->clk); - if (ret) { - dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); - return ret; - } - - cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); - if (!(cdns_phy->ref_clk_rate)) { - dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); - clk_disable_unprepare(cdns_phy->clk); - return -EINVAL; - } - switch (cdns_phy->ref_clk_rate) { case REF_CLK_19_2MHz: case REF_CLK_25MHz: @@ -918,7 +947,7 @@ static int cdns_torrent_dp_init(struct phy *phy) return ret; } -static int cdns_torrent_dp_exit(struct phy *phy) +static int cdns_torrent_phy_exit(struct phy *phy) { struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); @@ -1725,6 +1754,74 @@ static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) return 0; } +static int cdns_torrent_phy_init(struct phy *phy) +{ + struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); + struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; + struct cdns_torrent_inst *inst = phy_get_drvdata(phy); + enum cdns_torrent_phy_type phy_type = inst->phy_type; + enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; + struct cdns_reg_pairs *reg_pairs; + struct regmap *regmap; + u32 num_regs; + int ret, i, j; + + ret = clk_prepare_enable(cdns_phy->clk); + if (ret) { + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); + return ret; + } + + cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); + if (!(cdns_phy->ref_clk_rate)) { + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); + clk_disable_unprepare(cdns_phy->clk); + return -EINVAL; + } + + if (phy_type == TYPE_DP) + return cdns_torrent_dp_init(phy); + + /* PMA common registers configurations */ + cmn_vals = cdns_phy->init_data->cmn_vals[phy_type][ssc]; + if (cmn_vals) { + reg_pairs = cmn_vals->reg_pairs; + num_regs = cmn_vals->num_regs; + regmap = cdns_phy->regmap_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, + reg_pairs[i].val); + } + + /* PMA TX lane registers configurations */ + tx_ln_vals = cdns_phy->init_data->tx_ln_vals[phy_type][ssc]; + if (tx_ln_vals) { + reg_pairs = tx_ln_vals->reg_pairs; + num_regs = tx_ln_vals->num_regs; + for (i = 0; i < inst->num_lanes; i++) { + regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; + for (j = 0; j < num_regs; j++) + regmap_write(regmap, reg_pairs[j].off, + reg_pairs[j].val); + } + } + + /* PMA RX lane registers configurations */ + rx_ln_vals = cdns_phy->init_data->rx_ln_vals[phy_type][ssc]; + if (rx_ln_vals) { + reg_pairs = rx_ln_vals->reg_pairs; + num_regs = rx_ln_vals->num_regs; + for (i = 0; i < inst->num_lanes; i++) { + regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; + for (j = 0; j < num_regs; j++) + regmap_write(regmap, reg_pairs[j].off, + reg_pairs[j].val); + } + } + + return 0; +} + static int cdns_torrent_phy_probe(struct platform_device *pdev) { struct cdns_torrent_phy *cdns_phy; @@ -1736,6 +1833,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) int ret, subnodes, node = 0, i; u32 total_num_lanes = 0; u8 init_dp_regmap = 0; + u32 phy_type; /* Get init data for this PHY */ data = of_device_get_match_data(dev); @@ -1801,14 +1899,26 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) goto put_child; } - if (of_property_read_u32(child, "cdns,phy-type", - &cdns_phy->phys[node].phy_type)) { + if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", child->full_name); ret = -EINVAL; goto put_child; } + switch (phy_type) { + case PHY_TYPE_PCIE: + cdns_phy->phys[node].phy_type = TYPE_PCIE; + break; + case PHY_TYPE_DP: + cdns_phy->phys[node].phy_type = TYPE_DP; + break; + default: + dev_err(dev, "Unsupported protocol\n"); + ret = -EINVAL; + goto put_child; + } + if (of_property_read_u32(child, "cdns,num-lanes", &cdns_phy->phys[node].num_lanes)) { dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", @@ -1819,7 +1929,18 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) total_num_lanes += cdns_phy->phys[node].num_lanes; - if (cdns_phy->phys[node].phy_type == PHY_TYPE_DP) { + /* Get SSC mode */ + cdns_phy->phys[node].ssc_mode = NO_SSC; + of_property_read_u32(child, "cdns,ssc-mode", + &cdns_phy->phys[node].ssc_mode); + + gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); + if (IS_ERR(gphy)) { + ret = PTR_ERR(gphy); + goto put_child; + } + + if (cdns_phy->phys[node].phy_type == TYPE_DP) { switch (cdns_phy->phys[node].num_lanes) { case 1: case 2: @@ -1862,13 +1983,6 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) goto put_child; } - gphy = devm_phy_create(dev, child, - &cdns_torrent_phy_ops); - if (IS_ERR(gphy)) { - ret = PTR_ERR(gphy); - goto put_child; - } - if (!init_dp_regmap) { ret = cdns_torrent_dp_regmap_init(cdns_phy); if (ret) @@ -1892,6 +2006,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) phy_set_attrs(gphy, &torrent_attr); } + cdns_phy->phys[node].phy = gphy; phy_set_drvdata(gphy, &cdns_phy->phys[node]); @@ -1935,14 +2050,135 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev) return 0; } +/* Single link PCIe, 100 MHz Ref clk, internal SSC */ +static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { + {0x0004, CMN_PLL0_DSM_DIAG_M0}, + {0x0004, CMN_PLL0_DSM_DIAG_M1}, + {0x0004, CMN_PLL1_DSM_DIAG_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, + {0x0064, CMN_PLL0_INTDIV_M0}, + {0x0050, CMN_PLL0_INTDIV_M1}, + {0x0050, CMN_PLL1_INTDIV_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M1}, + {0x0002, CMN_PLL1_FRACDIVH_M0}, + {0x0044, CMN_PLL0_HIGH_THR_M0}, + {0x0036, CMN_PLL0_HIGH_THR_M1}, + {0x0036, CMN_PLL1_HIGH_THR_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, + {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M1}, + {0x0001, CMN_PLL1_SS_CTRL1_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M1}, + {0x011B, CMN_PLL1_SS_CTRL2_M0}, + {0x006E, CMN_PLL0_SS_CTRL3_M0}, + {0x0058, CMN_PLL0_SS_CTRL3_M1}, + {0x0058, CMN_PLL1_SS_CTRL3_M0}, + {0x000E, CMN_PLL0_SS_CTRL4_M0}, + {0x0012, CMN_PLL0_SS_CTRL4_M1}, + {0x0012, CMN_PLL1_SS_CTRL4_M0}, + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} +}; + +static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { + .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), +}; + +/* PCIe, 100 MHz Ref clk, no SSC & external SSC */ +static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL} +}; + +static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { + {0x0019, RX_REE_TAP1_CLIP}, + {0x0019, RX_REE_TAP2TON_CLIP}, + {0x0001, RX_DIAG_ACYA} +}; + +static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { + .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), +}; + +static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { + .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, + .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), +}; + static const struct cdns_torrent_data cdns_map_torrent = { .block_offset_shift = 0x2, .reg_offset_shift = 0x2, + .cmn_vals = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + }, + }, + .tx_ln_vals = { + [TYPE_PCIE] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + }, + .rx_ln_vals = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + }, }; static const struct cdns_torrent_data ti_j721e_map_torrent = { .block_offset_shift = 0x0, .reg_offset_shift = 0x1, + .cmn_vals = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + }, + }, + .tx_ln_vals = { + [TYPE_PCIE] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + }, + .rx_ln_vals = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + }, }; static const struct of_device_id cdns_torrent_phy_of_match[] = { From patchwork Thu Aug 27 16:16:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Swapnil Jakhade X-Patchwork-Id: 253299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B66CC433E1 for ; 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Signed-off-by: Swapnil Jakhade Acked-by: Rob Herring --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 36e8c241cf48..887a31b250a8 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -19,5 +19,6 @@ #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 +#define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ From patchwork Thu Aug 27 16:16:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Swapnil Jakhade X-Patchwork-Id: 253296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D457AC433E4 for ; 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Currently, maximum two links are supported. In case of multilink configuration, PHY needs to be configured for both the protocols simultaneously at the beginning as per the requirement of Torrent PHY. Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink configurations are added. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 783 +++++++++++++++++++++- 1 file changed, 757 insertions(+), 26 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 3038b50c7b12..fb49abc05445 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -29,7 +29,7 @@ #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ #define NUM_SSC_MODE 3 -#define NUM_PHY_TYPE 2 +#define NUM_PHY_TYPE 5 #define POLL_TIMEOUT_US 5000 #define PLL_LOCK_TIMEOUT 100000 @@ -127,8 +127,10 @@ #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU +#define CMN_TXPUCAL_TUNE 0x0103U #define CMN_TXPUCAL_INIT_TMR 0x0104U #define CMN_TXPUCAL_ITER_TMR 0x0105U +#define CMN_TXPDCAL_TUNE 0x010BU #define CMN_TXPDCAL_INIT_TMR 0x010CU #define CMN_TXPDCAL_ITER_TMR 0x010DU #define CMN_RXCAL_INIT_TMR 0x0114U @@ -143,6 +145,7 @@ #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U +#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U @@ -151,6 +154,7 @@ #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U +#define CMN_DIAG_BIAS_OVRD1 0x01E1U /* PMA TX Lane registers */ #define TX_TXCC_CTRL 0x0040U @@ -173,11 +177,20 @@ #define RX_PSC_A2 0x0002U #define RX_PSC_A3 0x0003U #define RX_PSC_CAL 0x0006U +#define RX_CDRLF_CNFG 0x0080U #define RX_REE_GCSM1_CTRL 0x0108U +#define RX_REE_GCSM1_EQENM_PH1 0x0109U +#define RX_REE_GCSM1_EQENM_PH2 0x010AU #define RX_REE_GCSM2_CTRL 0x0110U #define RX_REE_PERGCSM_CTRL 0x0118U #define RX_REE_TAP1_CLIP 0x0171U #define RX_REE_TAP2TON_CLIP 0x0172U +#define RX_DIAG_DFE_CTRL 0x01E0U +#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U +#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U +#define RX_DIAG_NQST_CTRL 0x01E5U +#define RX_DIAG_PI_RATE 0x01F4U +#define RX_DIAG_PI_CAP 0x01F5U #define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ @@ -204,8 +217,11 @@ static const struct reg_field phy_reset_ctrl = REG_FIELD(PHY_RESET, 8, 8); enum cdns_torrent_phy_type { + TYPE_NONE, TYPE_DP, - TYPE_PCIE + TYPE_PCIE, + TYPE_SGMII, + TYPE_QSGMII, }; enum cdns_torrent_ssc_mode { @@ -309,9 +325,16 @@ struct cdns_torrent_vals { struct cdns_torrent_data { u8 block_offset_shift; u8 reg_offset_shift; - struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; - struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; - struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_SSC_MODE]; + struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; }; struct cdns_regmap_cdb_context { @@ -1787,6 +1810,7 @@ static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) static int cdns_torrent_phy_init(struct phy *phy) { struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); + const struct cdns_torrent_data *init_data = cdns_phy->init_data; struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; struct cdns_torrent_inst *inst = phy_get_drvdata(phy); enum cdns_torrent_phy_type phy_type = inst->phy_type; @@ -1809,11 +1833,14 @@ static int cdns_torrent_phy_init(struct phy *phy) return -EINVAL; } + if (cdns_phy->nsubnodes > 1) + return 0; + if (phy_type == TYPE_DP) return cdns_torrent_dp_init(phy); /* PMA common registers configurations */ - cmn_vals = cdns_phy->init_data->cmn_vals[phy_type][ssc]; + cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc]; if (cmn_vals) { reg_pairs = cmn_vals->reg_pairs; num_regs = cmn_vals->num_regs; @@ -1824,7 +1851,7 @@ static int cdns_torrent_phy_init(struct phy *phy) } /* PMA TX lane registers configurations */ - tx_ln_vals = cdns_phy->init_data->tx_ln_vals[phy_type][ssc]; + tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc]; if (tx_ln_vals) { reg_pairs = tx_ln_vals->reg_pairs; num_regs = tx_ln_vals->num_regs; @@ -1837,7 +1864,7 @@ static int cdns_torrent_phy_init(struct phy *phy) } /* PMA RX lane registers configurations */ - rx_ln_vals = cdns_phy->init_data->rx_ln_vals[phy_type][ssc]; + rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc]; if (rx_ln_vals) { reg_pairs = rx_ln_vals->reg_pairs; num_regs = rx_ln_vals->num_regs; @@ -1852,6 +1879,121 @@ static int cdns_torrent_phy_init(struct phy *phy) return 0; } +static +int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) +{ + const struct cdns_torrent_data *init_data = cdns_phy->init_data; + struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; + struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; + enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type; + int i, j, node, mlane, num_lanes; + struct cdns_reg_pairs *reg_pairs; + enum cdns_torrent_ssc_mode ssc; + struct regmap *regmap; + u32 num_regs; + + /* Maximum 2 links (subnodes) are supported */ + if (cdns_phy->nsubnodes != 2) + return -EINVAL; + + phy_t1 = cdns_phy->phys[0].phy_type; + phy_t2 = cdns_phy->phys[1].phy_type; + + regmap_field_write(cdns_phy->phy_pll_cfg, 0x0003); + + /** + * First configure the PHY for first link with phy_t1. Get the array + * values as [phy_t1][phy_t2][ssc]. + */ + for (node = 0; node < cdns_phy->nsubnodes; node++) { + if (node == 1) { + /** + * If first link with phy_t1 is configured, then + * configure the PHY for second link with phy_t2. + * Get the array values as [phy_t2][phy_t1][ssc]. + */ + tmp_phy_type = phy_t1; + phy_t1 = phy_t2; + phy_t2 = tmp_phy_type; + } + + mlane = cdns_phy->phys[node].mlane; + ssc = cdns_phy->phys[node].ssc_mode; + num_lanes = cdns_phy->phys[node].num_lanes; + + /** + * PHY configuration specific registers: + * link_cmn_vals depend on combination of PHY types being + * configured and are common for both PHY types, so array + * values should be same for [phy_t1][phy_t2][ssc] and + * [phy_t2][phy_t1][ssc]. + * xcvr_diag_vals also depend on combination of PHY types + * being configured, but these can be different for particular + * PHY type and are per lane. + */ + link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc]; + if (link_cmn_vals) { + reg_pairs = link_cmn_vals->reg_pairs; + num_regs = link_cmn_vals->num_regs; + regmap = cdns_phy->regmap_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, + reg_pairs[i].val); + } + + xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc]; + if (xcvr_diag_vals) { + reg_pairs = xcvr_diag_vals->reg_pairs; + num_regs = xcvr_diag_vals->num_regs; + for (i = 0; i < num_lanes; i++) { + regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; + for (j = 0; j < num_regs; j++) + regmap_write(regmap, reg_pairs[j].off, + reg_pairs[j].val); + } + } + + /* PMA common registers configurations */ + cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc]; + if (cmn_vals) { + reg_pairs = cmn_vals->reg_pairs; + num_regs = cmn_vals->num_regs; + regmap = cdns_phy->regmap_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, + reg_pairs[i].val); + } + + /* PMA TX lane registers configurations */ + tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc]; + if (tx_ln_vals) { + reg_pairs = tx_ln_vals->reg_pairs; + num_regs = tx_ln_vals->num_regs; + for (i = 0; i < num_lanes; i++) { + regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; + for (j = 0; j < num_regs; j++) + regmap_write(regmap, reg_pairs[j].off, + reg_pairs[j].val); + } + } + + /* PMA RX lane registers configurations */ + rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc]; + if (rx_ln_vals) { + reg_pairs = rx_ln_vals->reg_pairs; + num_regs = rx_ln_vals->num_regs; + for (i = 0; i < num_lanes; i++) { + regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; + for (j = 0; j < num_regs; j++) + regmap_write(regmap, reg_pairs[j].off, + reg_pairs[j].val); + } + } + } + + return 0; +} + static int cdns_torrent_phy_probe(struct platform_device *pdev) { struct cdns_torrent_phy *cdns_phy; @@ -1922,6 +2064,10 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dev->of_node, child) { struct phy *gphy; + /* PHY subnode name must be 'link'. */ + if (!(of_node_name_eq(child, "link"))) + continue; + cdns_phy->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { @@ -1953,6 +2099,12 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) case PHY_TYPE_DP: cdns_phy->phys[node].phy_type = TYPE_DP; break; + case PHY_TYPE_SGMII: + cdns_phy->phys[node].phy_type = TYPE_SGMII; + break; + case PHY_TYPE_QSGMII: + cdns_phy->phys[node].phy_type = TYPE_QSGMII; + break; default: dev_err(dev, "Unsupported protocol\n"); ret = -EINVAL; @@ -2059,6 +2211,12 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) goto put_lnk_rst; } + if (cdns_phy->nsubnodes > 1) { + ret = cdns_torrent_phy_configure_multilink(cdns_phy); + if (ret) + goto put_lnk_rst; + } + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) { ret = PTR_ERR(phy_provider); @@ -2092,6 +2250,311 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev) return 0; } +/* PCIe and SGMII/QSGMII Unique SSC link configuration */ +static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { + {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, + {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, + {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} +}; + +static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { + {0x0000, XCVR_DIAG_HSCLK_SEL}, + {0x0001, XCVR_DIAG_HSCLK_DIV}, + {0x0012, XCVR_DIAG_PLLDRC_CTRL} +}; + +static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { + {0x0011, XCVR_DIAG_HSCLK_SEL}, + {0x0003, XCVR_DIAG_HSCLK_DIV}, + {0x009B, XCVR_DIAG_PLLDRC_CTRL} +}; + +static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { + .reg_pairs = pcie_sgmii_link_cmn_regs, + .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), +}; + +static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { + .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, + .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), +}; + +static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { + .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, + .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), +}; + +/* SGMII 100 MHz Ref clk, no SSC */ +static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x3700, CMN_DIAG_BIAS_OVRD1}, + {0x0008, CMN_TXPUCAL_TUNE}, + {0x0008, CMN_TXPDCAL_TUNE} +}; + +static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { + {0x00F3, TX_PSC_A0}, + {0x04A2, TX_PSC_A2}, + {0x04A2, TX_PSC_A3}, + {0x0000, TX_TXCC_CPOST_MULT_00}, + {0x00B3, DRV_DIAG_TX_DRV} +}; + +static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { + {0x091D, RX_PSC_A0}, + {0x0900, RX_PSC_A2}, + {0x0100, RX_PSC_A3}, + {0x03C7, RX_REE_GCSM1_EQENM_PH1}, + {0x01C7, RX_REE_GCSM1_EQENM_PH2}, + {0x0000, RX_DIAG_DFE_CTRL}, + {0x0019, RX_REE_TAP1_CLIP}, + {0x0019, RX_REE_TAP2TON_CLIP}, + {0x0098, RX_DIAG_NQST_CTRL}, + {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, + {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, + {0x0000, RX_DIAG_PI_CAP}, + {0x0010, RX_DIAG_PI_RATE}, + {0x0001, RX_DIAG_ACYA}, + {0x018C, RX_CDRLF_CNFG}, +}; + +static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { + .reg_pairs = sgmii_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), +}; + +static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { + .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, + .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), +}; + +static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { + .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, + .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), +}; + +/* SGMII 100 MHz Ref clk, internal SSC */ +static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { + {0x0004, CMN_PLL0_DSM_DIAG_M0}, + {0x0004, CMN_PLL0_DSM_DIAG_M1}, + {0x0004, CMN_PLL1_DSM_DIAG_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, + {0x0064, CMN_PLL0_INTDIV_M0}, + {0x0050, CMN_PLL0_INTDIV_M1}, + {0x0064, CMN_PLL1_INTDIV_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M1}, + {0x0002, CMN_PLL1_FRACDIVH_M0}, + {0x0044, CMN_PLL0_HIGH_THR_M0}, + {0x0036, CMN_PLL0_HIGH_THR_M1}, + {0x0044, CMN_PLL1_HIGH_THR_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, + {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M1}, + {0x0001, CMN_PLL1_SS_CTRL1_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M1}, + {0x011B, CMN_PLL1_SS_CTRL2_M0}, + {0x006E, CMN_PLL0_SS_CTRL3_M0}, + {0x0058, CMN_PLL0_SS_CTRL3_M1}, + {0x006E, CMN_PLL1_SS_CTRL3_M0}, + {0x000E, CMN_PLL0_SS_CTRL4_M0}, + {0x0012, CMN_PLL0_SS_CTRL4_M1}, + {0x000E, CMN_PLL1_SS_CTRL4_M0}, + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, + {0x3700, CMN_DIAG_BIAS_OVRD1}, + {0x0008, CMN_TXPUCAL_TUNE}, + {0x0008, CMN_TXPDCAL_TUNE} +}; + +static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { + .reg_pairs = sgmii_100_int_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), +}; + +/* QSGMII 100 MHz Ref clk, no SSC */ +static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL} +}; + +static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { + {0x00F3, TX_PSC_A0}, + {0x04A2, TX_PSC_A2}, + {0x04A2, TX_PSC_A3}, + {0x0000, TX_TXCC_CPOST_MULT_00}, + {0x0003, DRV_DIAG_TX_DRV} +}; + +static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { + {0x091D, RX_PSC_A0}, + {0x0900, RX_PSC_A2}, + {0x0100, RX_PSC_A3}, + {0x03C7, RX_REE_GCSM1_EQENM_PH1}, + {0x01C7, RX_REE_GCSM1_EQENM_PH2}, + {0x0000, RX_DIAG_DFE_CTRL}, + {0x0019, RX_REE_TAP1_CLIP}, + {0x0019, RX_REE_TAP2TON_CLIP}, + {0x0098, RX_DIAG_NQST_CTRL}, + {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, + {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, + {0x0000, RX_DIAG_PI_CAP}, + {0x0010, RX_DIAG_PI_RATE}, + {0x0001, RX_DIAG_ACYA}, + {0x018C, RX_CDRLF_CNFG}, +}; + +static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { + .reg_pairs = qsgmii_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), +}; + +static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { + .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, + .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), +}; + +static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { + .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, + .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), +}; + +/* QSGMII 100 MHz Ref clk, internal SSC */ +static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { + {0x0004, CMN_PLL0_DSM_DIAG_M0}, + {0x0004, CMN_PLL0_DSM_DIAG_M1}, + {0x0004, CMN_PLL1_DSM_DIAG_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, + {0x0064, CMN_PLL0_INTDIV_M0}, + {0x0050, CMN_PLL0_INTDIV_M1}, + {0x0064, CMN_PLL1_INTDIV_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M1}, + {0x0002, CMN_PLL1_FRACDIVH_M0}, + {0x0044, CMN_PLL0_HIGH_THR_M0}, + {0x0036, CMN_PLL0_HIGH_THR_M1}, + {0x0044, CMN_PLL1_HIGH_THR_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, + {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M1}, + {0x0001, CMN_PLL1_SS_CTRL1_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M1}, + {0x011B, CMN_PLL1_SS_CTRL2_M0}, + {0x006E, CMN_PLL0_SS_CTRL3_M0}, + {0x0058, CMN_PLL0_SS_CTRL3_M1}, + {0x006E, CMN_PLL1_SS_CTRL3_M0}, + {0x000E, CMN_PLL0_SS_CTRL4_M0}, + {0x0012, CMN_PLL0_SS_CTRL4_M1}, + {0x000E, CMN_PLL1_SS_CTRL4_M0}, + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} +}; + +static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { + .reg_pairs = qsgmii_100_int_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), +}; + +/* Multi link PCIe, 100 MHz Ref clk, internal SSC */ +static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { + {0x0004, CMN_PLL0_DSM_DIAG_M0}, + {0x0004, CMN_PLL0_DSM_DIAG_M1}, + {0x0004, CMN_PLL1_DSM_DIAG_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, + {0x0064, CMN_PLL0_INTDIV_M0}, + {0x0050, CMN_PLL0_INTDIV_M1}, + {0x0064, CMN_PLL1_INTDIV_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M1}, + {0x0002, CMN_PLL1_FRACDIVH_M0}, + {0x0044, CMN_PLL0_HIGH_THR_M0}, + {0x0036, CMN_PLL0_HIGH_THR_M1}, + {0x0044, CMN_PLL1_HIGH_THR_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, + {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M1}, + {0x0001, CMN_PLL1_SS_CTRL1_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M1}, + {0x011B, CMN_PLL1_SS_CTRL2_M0}, + {0x006E, CMN_PLL0_SS_CTRL3_M0}, + {0x0058, CMN_PLL0_SS_CTRL3_M1}, + {0x006E, CMN_PLL1_SS_CTRL3_M0}, + {0x000E, CMN_PLL0_SS_CTRL4_M0}, + {0x0012, CMN_PLL0_SS_CTRL4_M1}, + {0x000E, CMN_PLL1_SS_CTRL4_M0}, + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} +}; + +static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { + .reg_pairs = pcie_100_int_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), +}; + /* Single link PCIe, 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { {0x0004, CMN_PLL0_DSM_DIAG_M0}, @@ -2174,25 +2637,159 @@ static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { static const struct cdns_torrent_data cdns_map_torrent = { .block_offset_shift = 0x2, .reg_offset_shift = 0x2, + .link_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_SGMII] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + }, + .xcvr_diag_vals = { + [TYPE_PCIE] = { + [TYPE_SGMII] = { + [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + }, + }, + }, .cmn_vals = { [TYPE_PCIE] = { - [NO_SSC] = &pcie_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, - [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + [TYPE_NONE] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + }, + [TYPE_SGMII] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, + }, }, }, .tx_ln_vals = { [TYPE_PCIE] = { - [NO_SSC] = NULL, - [EXTERNAL_SSC] = NULL, - [INTERNAL_SSC] = NULL, + [TYPE_NONE] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + [TYPE_SGMII] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + [TYPE_QSGMII] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + }, }, }, .rx_ln_vals = { [TYPE_PCIE] = { - [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, - [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [TYPE_NONE] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + [TYPE_SGMII] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + }, }, }, }; @@ -2200,25 +2797,159 @@ static const struct cdns_torrent_data cdns_map_torrent = { static const struct cdns_torrent_data ti_j721e_map_torrent = { .block_offset_shift = 0x0, .reg_offset_shift = 0x1, + .link_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_SGMII] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &pcie_sgmii_link_cmn_vals, + [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, + }, + }, + }, + .xcvr_diag_vals = { + [TYPE_PCIE] = { + [TYPE_SGMII] = { + [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, + }, + }, + }, .cmn_vals = { [TYPE_PCIE] = { - [NO_SSC] = &pcie_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, - [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + [TYPE_NONE] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, + }, + [TYPE_SGMII] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, + }, }, }, .tx_ln_vals = { [TYPE_PCIE] = { - [NO_SSC] = NULL, - [EXTERNAL_SSC] = NULL, - [INTERNAL_SSC] = NULL, + [TYPE_NONE] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + [TYPE_SGMII] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + [TYPE_QSGMII] = { + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, + [INTERNAL_SSC] = NULL, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + }, }, }, .rx_ln_vals = { [TYPE_PCIE] = { - [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, - [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [TYPE_NONE] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + [TYPE_SGMII] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + [TYPE_QSGMII] = { + [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, + }, + }, + [TYPE_SGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, + }, + }, + [TYPE_QSGMII] = { + [TYPE_PCIE] = { + [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, + }, }, }, }; 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DIR:OUT; SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2020 16:17:03.0932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3732cab8-20ca-4882-5b42-08d84aa4a250 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[199.43.4.23]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM12FT057.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB4972 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_08:2020-08-27,2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270120 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For multilink configuration, deassert PHY and link reset after PHY registers are configured in probe and only check link status in power_on callback. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 28 +++++++++++++++++------ 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index fb49abc05445..56673806812f 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -1603,13 +1603,15 @@ static int cdns_torrent_phy_on(struct phy *phy) u32 read_val; int ret; - /* Take the PHY out of reset */ - ret = reset_control_deassert(cdns_phy->phy_rst); - if (ret) - return ret; + if (cdns_phy->nsubnodes == 1) { + /* Take the PHY lane group out of reset */ + reset_control_deassert(inst->lnk_rst); - /* Take the PHY lane group out of reset */ - reset_control_deassert(inst->lnk_rst); + /* Take the PHY out of reset */ + ret = reset_control_deassert(cdns_phy->phy_rst); + if (ret) + return ret; + } /* * Wait for cmn_ready assertion @@ -1623,6 +1625,8 @@ static int cdns_torrent_phy_on(struct phy *phy) return ret; } + mdelay(10); + return 0; } @@ -1632,6 +1636,9 @@ static int cdns_torrent_phy_off(struct phy *phy) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); int ret; + if (cdns_phy->nsubnodes != 1) + return 0; + ret = reset_control_assert(cdns_phy->phy_rst); if (ret) return ret; @@ -1886,7 +1893,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type; - int i, j, node, mlane, num_lanes; + int i, j, node, mlane, num_lanes, ret; struct cdns_reg_pairs *reg_pairs; enum cdns_torrent_ssc_mode ssc; struct regmap *regmap; @@ -1989,8 +1996,15 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) reg_pairs[j].val); } } + + reset_control_deassert(cdns_phy->phys[node].lnk_rst); } + /* Take the PHY out of reset */ + ret = reset_control_deassert(cdns_phy->phy_rst); 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Thu, 27 Aug 2020 18:16:52 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Thu, 27 Aug 2020 18:16:52 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 07RGGqYO031850; Thu, 27 Aug 2020 18:16:52 +0200 Received: (from sjakhade@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 07RGGq7f031849; Thu, 27 Aug 2020 18:16:52 +0200 From: Swapnil Jakhade To: , , , , , CC: , , , , , Subject: [PATCH v2 07/13] phy: cadence-torrent: Add clk changes for multilink configuration Date: Thu, 27 Aug 2020 18:16:45 +0200 Message-ID: <1598545011-31772-8-git-send-email-sjakhade@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1598545011-31772-1-git-send-email-sjakhade@cadence.com> References: <1598545011-31772-1-git-send-email-sjakhade@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9386c071-d729-4510-8d71-08d84aa4a1b9 X-MS-TrafficTypeDiagnostic: BL0PR07MB5521: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:475; 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DIR:OUT; SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2020 16:17:02.1039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9386c071-d729-4510-8d71-08d84aa4a1b9 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[199.43.4.23]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM12FT003.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR07MB5521 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-27_08:2020-08-27,2020-08-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 mlxscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270120 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Prepare and enable clock in probe instead of phy_init. Also, remove phy_exit callback. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 41 ++++++++++------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 56673806812f..9a87ee39a15a 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -273,7 +273,6 @@ enum phy_powerstate { }; static int cdns_torrent_phy_init(struct phy *phy); -static int cdns_torrent_phy_exit(struct phy *phy); static int cdns_torrent_dp_init(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes); @@ -305,7 +304,6 @@ static int cdns_torrent_phy_off(struct phy *phy); static const struct phy_ops cdns_torrent_phy_ops = { .init = cdns_torrent_phy_init, - .exit = cdns_torrent_phy_exit, .configure = cdns_torrent_dp_configure, .power_on = cdns_torrent_phy_on, .power_off = cdns_torrent_phy_off, @@ -977,14 +975,6 @@ static int cdns_torrent_dp_init(struct phy *phy) return ret; } -static int cdns_torrent_phy_exit(struct phy *phy) -{ - struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); - - clk_disable_unprepare(cdns_phy->clk); - return 0; -} - static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) { @@ -1825,20 +1815,7 @@ static int cdns_torrent_phy_init(struct phy *phy) struct cdns_reg_pairs *reg_pairs; struct regmap *regmap; u32 num_regs; - int ret, i, j; - - ret = clk_prepare_enable(cdns_phy->clk); - if (ret) { - dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); - return ret; - } - - cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); - if (!(cdns_phy->ref_clk_rate)) { - dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); - clk_disable_unprepare(cdns_phy->clk); - return -EINVAL; - } + int i, j; if (cdns_phy->nsubnodes > 1) return 0; @@ -2072,6 +2049,19 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) if (ret) return ret; + ret = clk_prepare_enable(cdns_phy->clk); + if (ret) { + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); + return ret; + } + + cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); + if (!(cdns_phy->ref_clk_rate)) { + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); + clk_disable_unprepare(cdns_phy->clk); + return -EINVAL; + } + /* Enable APB */ reset_control_deassert(cdns_phy->apb_rst); @@ -2246,6 +2236,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) reset_control_put(cdns_phy->phys[i].lnk_rst); of_node_put(child); reset_control_assert(cdns_phy->apb_rst); + clk_disable_unprepare(cdns_phy->clk); return ret; } @@ -2261,6 +2252,8 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev) reset_control_put(cdns_phy->phys[i].lnk_rst); } + clk_disable_unprepare(cdns_phy->clk); + return 0; } From patchwork Thu Aug 27 16:16:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Swapnil Jakhade X-Patchwork-Id: 253294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E015BC433E1 for ; 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Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 260 +++++++++++++++++++++- 1 file changed, 259 insertions(+), 1 deletion(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 5bc9bbddcc9c..a444184acca3 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -29,7 +29,7 @@ #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ #define NUM_SSC_MODE 3 -#define NUM_PHY_TYPE 5 +#define NUM_PHY_TYPE 6 #define POLL_TIMEOUT_US 5000 #define PLL_LOCK_TIMEOUT 100000 @@ -82,6 +82,8 @@ #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU #define CMN_PLLSM1_PLLPRE_TMR 0x0032U #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U +#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U +#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U #define CMN_BGCAL_INIT_TMR 0x0064U #define CMN_BGCAL_ITER_TMR 0x0065U #define CMN_IBCAL_INIT_TMR 0x0074U @@ -159,13 +161,16 @@ /* PMA TX Lane registers */ #define TX_TXCC_CTRL 0x0040U #define TX_TXCC_CPOST_MULT_00 0x004CU +#define TX_TXCC_CPOST_MULT_01 0x004DU #define TX_TXCC_MGNFS_MULT_000 0x0050U #define DRV_DIAG_TX_DRV 0x00C6U #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U #define XCVR_DIAG_HSCLK_SEL 0x00E6U #define XCVR_DIAG_HSCLK_DIV 0x00E7U #define XCVR_DIAG_BIDI_CTRL 0x00EAU +#define XCVR_DIAG_PSC_OVRD 0x00EBU #define TX_PSC_A0 0x0100U +#define TX_PSC_A1 0x0101U #define TX_PSC_A2 0x0102U #define TX_PSC_A3 0x0103U #define TX_RCVDET_ST_TMR 0x0123U @@ -174,27 +179,37 @@ /* PMA RX Lane registers */ #define RX_PSC_A0 0x0000U +#define RX_PSC_A1 0x0001U #define RX_PSC_A2 0x0002U #define RX_PSC_A3 0x0003U #define RX_PSC_CAL 0x0006U #define RX_CDRLF_CNFG 0x0080U +#define RX_CDRLF_CNFG3 0x0082U +#define RX_SIGDET_HL_FILT_TMR 0x0090U #define RX_REE_GCSM1_CTRL 0x0108U #define RX_REE_GCSM1_EQENM_PH1 0x0109U #define RX_REE_GCSM1_EQENM_PH2 0x010AU #define RX_REE_GCSM2_CTRL 0x0110U #define RX_REE_PERGCSM_CTRL 0x0118U +#define RX_REE_ATTEN_THR 0x0149U #define RX_REE_TAP1_CLIP 0x0171U #define RX_REE_TAP2TON_CLIP 0x0172U +#define RX_REE_SMGM_CTRL1 0x0177U +#define RX_REE_SMGM_CTRL2 0x0178U #define RX_DIAG_DFE_CTRL 0x01E0U #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U #define RX_DIAG_NQST_CTRL 0x01E5U +#define RX_DIAG_SIGDET_TUNE 0x01E8U #define RX_DIAG_PI_RATE 0x01F4U #define RX_DIAG_PI_CAP 0x01F5U #define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ #define PHY_PLL_CFG 0x000EU +#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U +#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U +#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U /* PHY PMA common registers */ #define PHY_PMA_CMN_CTRL1 0x0000U @@ -222,6 +237,7 @@ enum cdns_torrent_phy_type { TYPE_PCIE, TYPE_SGMII, TYPE_QSGMII, + TYPE_USB, }; enum cdns_torrent_ssc_mode { @@ -327,6 +343,8 @@ struct cdns_torrent_data { [NUM_SSC_MODE]; struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] [NUM_SSC_MODE]; + struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] [NUM_SSC_MODE]; struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] @@ -1813,6 +1831,7 @@ static int cdns_torrent_phy_init(struct phy *phy) struct cdns_torrent_inst *inst = phy_get_drvdata(phy); enum cdns_torrent_phy_type phy_type = inst->phy_type; enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; + struct cdns_torrent_vals *pcs_cmn_vals; struct cdns_reg_pairs *reg_pairs; struct regmap *regmap; u32 num_regs; @@ -1861,6 +1880,17 @@ static int cdns_torrent_phy_init(struct phy *phy) } } + /* PHY PCS common registers configurations */ + pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; + if (pcs_cmn_vals) { + reg_pairs = pcs_cmn_vals->reg_pairs; + num_regs = pcs_cmn_vals->num_regs; + regmap = cdns_phy->regmap_phy_pcs_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, + reg_pairs[i].val); + } + /* PMA common registers configurations */ cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc]; if (cmn_vals) { @@ -2153,6 +2183,9 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) case PHY_TYPE_QSGMII: cdns_phy->phys[node].phy_type = TYPE_QSGMII; break; + case PHY_TYPE_USB3: + cdns_phy->phys[node].phy_type = TYPE_USB; + break; default: dev_err(dev, "Unsupported protocol\n"); ret = -EINVAL; @@ -2301,6 +2334,143 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev) return 0; } +/* Single USB link configuration */ +static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { + {0x0000, PHY_PLL_CFG}, + {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} +}; + +static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { + {0x0000, XCVR_DIAG_HSCLK_SEL}, + {0x0001, XCVR_DIAG_HSCLK_DIV}, + {0x0041, XCVR_DIAG_PLLDRC_CTRL} +}; + +static struct cdns_torrent_vals sl_usb_link_cmn_vals = { + .reg_pairs = sl_usb_link_cmn_regs, + .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), +}; + +static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { + .reg_pairs = sl_usb_xcvr_diag_ln_regs, + .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), +}; + +/* USB PHY PCS common configuration */ +static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { + {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, + {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, + {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} +}; + +static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { + .reg_pairs = usb_phy_pcs_cmn_regs, + .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), +}; + +/* USB 100 MHz Ref clk, no SSC */ +static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, + {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} +}; + +static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { + {0x02FF, TX_PSC_A0}, + {0x06AF, TX_PSC_A1}, + {0x06AE, TX_PSC_A2}, + {0x06AE, TX_PSC_A3}, + {0x2A82, TX_TXCC_CTRL}, + {0x0014, TX_TXCC_CPOST_MULT_01}, + {0x0003, XCVR_DIAG_PSC_OVRD} +}; + +static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { + {0x0D1D, RX_PSC_A0}, + {0x0D1D, RX_PSC_A1}, + {0x0D00, RX_PSC_A2}, + {0x0500, RX_PSC_A3}, + {0x0013, RX_SIGDET_HL_FILT_TMR}, + {0x0000, RX_REE_GCSM1_CTRL}, + {0x0C02, RX_REE_ATTEN_THR}, + {0x0330, RX_REE_SMGM_CTRL1}, + {0x0300, RX_REE_SMGM_CTRL2}, + {0x0019, RX_REE_TAP1_CLIP}, + {0x0019, RX_REE_TAP2TON_CLIP}, + {0x1004, RX_DIAG_SIGDET_TUNE}, + {0x00F9, RX_DIAG_NQST_CTRL}, + {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, + {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, + {0x0000, RX_DIAG_PI_CAP}, + {0x0031, RX_DIAG_PI_RATE}, + {0x0001, RX_DIAG_ACYA}, + {0x018C, RX_CDRLF_CNFG}, + {0x0003, RX_CDRLF_CNFG3} +}; + +static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { + .reg_pairs = usb_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), +}; + +static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { + .reg_pairs = usb_100_no_ssc_tx_ln_regs, + .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), +}; + +static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { + .reg_pairs = usb_100_no_ssc_rx_ln_regs, + .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), +}; + +/* Single link USB, 100 MHz Ref clk, internal SSC */ +static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { + {0x0004, CMN_PLL0_DSM_DIAG_M0}, + {0x0004, CMN_PLL1_DSM_DIAG_M0}, + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, + {0x0064, CMN_PLL0_INTDIV_M0}, + {0x0064, CMN_PLL1_INTDIV_M0}, + {0x0002, CMN_PLL0_FRACDIVH_M0}, + {0x0002, CMN_PLL1_FRACDIVH_M0}, + {0x0044, CMN_PLL0_HIGH_THR_M0}, + {0x0044, CMN_PLL1_HIGH_THR_M0}, + {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, + {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, + {0x0001, CMN_PLL0_SS_CTRL1_M0}, + {0x0001, CMN_PLL1_SS_CTRL1_M0}, + {0x011B, CMN_PLL0_SS_CTRL2_M0}, + {0x011B, CMN_PLL1_SS_CTRL2_M0}, + {0x006E, CMN_PLL0_SS_CTRL3_M0}, + {0x006E, CMN_PLL1_SS_CTRL3_M0}, + {0x000E, CMN_PLL0_SS_CTRL4_M0}, + {0x000E, CMN_PLL1_SS_CTRL4_M0}, + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, + {0x0003, CMN_PLL0_VCOCAL_TCTRL}, + {0x0003, CMN_PLL1_VCOCAL_TCTRL}, + {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, + {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, + {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} +}; + +static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { + .reg_pairs = sl_usb_100_int_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), +}; + /* PCIe and SGMII/QSGMII Unique SSC link configuration */ static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { {0x0003, PHY_PLL_CFG}, @@ -2749,6 +2919,13 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &sl_usb_link_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, + [INTERNAL_SSC] = &sl_usb_link_cmn_vals, + }, + }, }, .xcvr_diag_vals = { [TYPE_PCIE] = { @@ -2788,6 +2965,22 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, + }, + }, + }, + .pcs_cmn_vals = { + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_phy_pcs_cmn_vals, + [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, + [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, + }, + }, }, .cmn_vals = { [TYPE_PCIE] = { @@ -2827,6 +3020,13 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, + }, + }, }, .tx_ln_vals = { [TYPE_PCIE] = { @@ -2866,6 +3066,13 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, + }, + }, }, .rx_ln_vals = { [TYPE_PCIE] = { @@ -2905,6 +3112,13 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, + }, + }, }, }; @@ -2949,6 +3163,13 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &sl_usb_link_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, + [INTERNAL_SSC] = &sl_usb_link_cmn_vals, + }, + }, }, .xcvr_diag_vals = { [TYPE_PCIE] = { @@ -2988,6 +3209,22 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, + [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, + [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, + }, + }, + }, + .pcs_cmn_vals = { + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_phy_pcs_cmn_vals, + [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, + [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, + }, + }, }, .cmn_vals = { [TYPE_PCIE] = { @@ -3027,6 +3264,13 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, + }, + }, }, .tx_ln_vals = { [TYPE_PCIE] = { @@ -3066,6 +3310,13 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, + }, + }, }, .rx_ln_vals = { [TYPE_PCIE] = { @@ -3105,6 +3356,13 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, }, }, + [TYPE_USB] = { + [TYPE_NONE] = { + [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, + [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, + [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, + }, + }, }, };