From patchwork Fri Oct 13 15:56:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115780 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp887858qgn; Fri, 13 Oct 2017 08:57:56 -0700 (PDT) X-Received: by 10.101.80.7 with SMTP id f7mr1711498pgo.408.1507910276106; Fri, 13 Oct 2017 08:57:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507910276; cv=none; d=google.com; s=arc-20160816; b=QmT7gb3U7r7qsOf+xDrJLrmMx1JsbCP0oW5JpGt+pRayD5L9kbO+AonlkNRDhWd+gq 0Qp0DiaZSU8ttBuBD6Mrrm1Xc65PukCcHNbHbiifRv1dT+8kNJWuGYXmt4i1LBka+oJi nFWdIWVXg65K93TqruIscx25WUv01XrNiB85g2XgpqglYtpeV7Ivk4QWj+G83Do3qeEO FS6Sp/C1VphuDbS/gRnW3mdJBzoQus4XGHhd01MC068nudNeijgjQ7YAQQKdeQK9M8JW fm8lOU2V8uhHihdui5TLRU1NPry+b4QK8yas6dUUJjVOBdBj1cZ1X9FEvL793V7K1A5o 5Yew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EQu7PFLjrq2GiEHpKuuMmsW9JiqjM6AT0EmeueAqLhg=; b=isbsU4yZ2VB8qAQ0JH+AVFdOzscSS2ZKMirh+GLp6txtf+ZSdX+xcmxbqC8yBy8SiB SDycGYNEbMdtgjZwxY9f6/IDHn5a2OJLNeSSlDgv6m+wOLRwVq7nD1w3f1dR7iHNtNn7 QnPX0JqiGtzvP/YnOuvef4BcRHPHFi6iWH/ur8C4tvyEIDTdwsWqM+xI6xNO+NKdoJkr xH7ZnOqrFdEsJcBbSCEEs1z7M/2jZEFUzPOcHQDgDBH/Ddu233M7kVcS+mUcCAsYgNcO +umIreGqPiIo/tlCR4EZ2+KdQrvFMOx2DaWn0sxpO7cAFE0fY2pAzvXQq2Lo/KHGJYgb MuzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HY3JEgg1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n8si794263plk.532.2017.10.13.08.57.55; Fri, 13 Oct 2017 08:57:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HY3JEgg1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751040AbdJMP5z (ORCPT + 6 others); Fri, 13 Oct 2017 11:57:55 -0400 Received: from mail-wr0-f176.google.com ([209.85.128.176]:53976 "EHLO mail-wr0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750973AbdJMP5y (ORCPT ); Fri, 13 Oct 2017 11:57:54 -0400 Received: by mail-wr0-f176.google.com with SMTP id y44so1371063wry.10 for ; Fri, 13 Oct 2017 08:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hcoqsPVs5C7Pd8/M04kFqx7qMm95VJSP1qF5aCHerpw=; b=HY3JEgg1CQ66MpEB0OtrjfLPB6nkesoTd4N0OE4LpVJzg9zrUkHHr9Wb1op3A5HCSU D3gBIlvLkUou0tdbPG5lkd4DGbFZBz7H9PWlFQabbfkPvUrY8BLCrf3jhRUg+3jHonph UCePjQN+QyvIzKhQ65rthR4uPLm6CHBl1G9yU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hcoqsPVs5C7Pd8/M04kFqx7qMm95VJSP1qF5aCHerpw=; b=C2bMqjB3iYjxhqLRFlIyY6ndsqCVbJ18eoLXPPcCQri05LZaTrBLhoW25RXFpLJjuq xohXtVQyAkx1uhWjGnDYQPm22Nw4fD+fVQyGeV30TY820VWic09my2t74691s3HNjMzn 4yH4Ojlz7SXJz3eY6a+zCQj6DB/MS6tpoUcX0m/zw64u0eFpycFZD/+o2B7EUuDlhcgZ ngXeXn1XUFHTXeg2ohwv9VD8u8xYyZ49HqvzN9gSThJow2ZW0EaBY6p1wbps0jdWA/A6 TcA8zGICtgqi1PNYCaiypX29LdJ8Myb9es35mVIrrq1fzRtnOabtnFqWbFnIc4+xooPl oHFA== X-Gm-Message-State: AMCzsaUmiYnEbO+3FygHViRKCFKaosEi0v6sgw0vqaAeZZH7X9Jm1fv7 PI4HRMZF4gjamRSAevTQ7F6UvrBSnww= X-Google-Smtp-Source: AOwi7QAB5pQsk9aTN+wGZs0nBitee7CGhVke/dApnvaQMdmlHulCABq4r/ggzrlER0OgnhJ861eytA== X-Received: by 10.223.172.242 with SMTP id o105mr1690568wrc.242.1507910273724; Fri, 13 Oct 2017 08:57:53 -0700 (PDT) Received: from localhost.localdomain ([154.146.29.151]) by smtp.gmail.com with ESMTPSA id l19sm1636046wre.26.2017.10.13.08.57.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 08:57:52 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v4 1/3] drivers/irqchip: gicv3: probe device ID space before quirks handling Date: Fri, 13 Oct 2017 16:56:05 +0100 Message-Id: <20171013155607.5211-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171013155607.5211-1-ard.biesheuvel@linaro.org> References: <20171013155607.5211-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Before adding another SoC whose device ID space deviates from the value presented in the GIC ID registers, let's slightly refactor the code so that the ID registers are probed before that quirks handling executes. This allows us to move the device ID override into the quirk handler itself. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-v3-its.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e8d89343d613..891de07fd4cc 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1650,23 +1650,14 @@ static void its_free_tables(struct its_node *its) static int its_alloc_tables(struct its_node *its) { - u64 typer = gic_read_typer(its->base + GITS_TYPER); - u32 ids = GITS_TYPER_DEVBITS(typer); u64 shr = GITS_BASER_InnerShareable; u64 cache = GITS_BASER_RaWaWb; u32 psz = SZ_64K; int err, i; - if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { - /* - * erratum 22375: only alloc 8MB table size - * erratum 24313: ignore memory access type - */ - cache = GITS_BASER_nCnB; - ids = 0x14; /* 20 bits, 8MB */ - } - - its->device_ids = ids; + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) + /* erratum 24313: ignore memory access type */ + cache = GITS_BASER_nCnB; for (i = 0; i < GITS_BASER_NR_REGS; i++) { struct its_baser *baser = its->tables + i; @@ -2741,6 +2732,8 @@ static void __maybe_unused its_enable_quirk_cavium_22375(void *data) { struct its_node *its = data; + /* erratum 22375: only alloc 8MB table size */ + its->device_ids = 0x14; /* 20 bits, 8MB */ its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; } @@ -2942,6 +2935,7 @@ static int __init its_probe_one(struct resource *res, its->base = its_base; its->phys_base = res->start; its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); + its->device_ids = GITS_TYPER_DEVBITS(typer); its->is_v4 = !!(typer & GITS_TYPER_VLPIS); if (its->is_v4) { if (!(typer & GITS_TYPER_VMOVP)) { From patchwork Fri Oct 13 15:56:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115781 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp887916qgn; Fri, 13 Oct 2017 08:57:59 -0700 (PDT) X-Received: by 10.98.161.24 with SMTP id b24mr1792107pff.297.1507910279380; Fri, 13 Oct 2017 08:57:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507910279; cv=none; d=google.com; s=arc-20160816; b=nWREP5ncHxZJ641ULUPmjn8CuW1pL/SJ7hMK7IjaDjuuHi1Rk1b0bsLnVrerv4EJWC beCQco6IiydEkHXI99x1Gy0WHOISLmjqV8iK/cgSAgWK6UL8JbutpYi/A2v+auKKjq6a t7S04PWs04cF96zvBaOBkaVQ9d30oW8XUiCbN1TCVZVDjIUdTDOPKHWVlMMgr0EGBpI0 96cFUTTGvP+eqCsW9dXN7/224Z6kFEj7blTPJc4NIujrYVsQxNceiqFoLphLwZr/3WlN 7xnNPzcvdT3OLp7bNiYdb38sQJjJbkRDEsRY0JuPDYoFPeBxDCdjhr5AZ0OowvIShj7q z83g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MmKOl5SAc5SB6evwTPYxNICjnstxUP7IIORre6iFlwI=; b=y3TXaDhmm0+XsbU2/xzc2GprZTqtxH/k6aGVtDkFsQAdzdLHOLqia94W4tE27TYJsw V/MuvVzt7o9CfCi2xGzXSQIpfZG0XrT7VDRXZIRUHeSeMSGR/kRUnBYNWg9s7CfspWHP D3TEFbDdoAtnMqe/JP6vbNGsM7ewpCNqqr37ENDxtG0YsxzrRtOoDlsVwd+lQBNMMKpg dhzou8lH2uVxrWSugWZSRDg48UocD/Z/XypRaW0KepDOaUl8Qo2g21BbqxjweM9br9WP iw9wLlTtvQjEPCYcStwPb2E3/G+rxmdPpLkO6YjZkRzqVBk9AecaAoEicMTTfOIQELmp ibNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Cq3E2/Pg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n8si794263plk.532.2017.10.13.08.57.59; Fri, 13 Oct 2017 08:57:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Cq3E2/Pg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751092AbdJMP56 (ORCPT + 6 others); Fri, 13 Oct 2017 11:57:58 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:46475 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdJMP56 (ORCPT ); Fri, 13 Oct 2017 11:57:58 -0400 Received: by mail-wm0-f46.google.com with SMTP id m72so22406402wmc.1 for ; Fri, 13 Oct 2017 08:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5MZeF5H0kxfAkUgudBaKRgw2g16JWJEnv8PWhghXnhE=; b=Cq3E2/Pg0OcAgHU6cWxduVAl8XUrC5AfFWPrX39ezVT7DFPIIkU2J9acuMB9gvl5W1 /nx7w0mwfZEa6iPn9XmYdu47KNw/V7phCgWgxYxQNUeFs/zMIPuKqr9KFGwX3rz6Yn3J bGgmgynxWsDWGRr/izXZ61v1GWDfCyZ3ynKLU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5MZeF5H0kxfAkUgudBaKRgw2g16JWJEnv8PWhghXnhE=; b=SV9XqmIIF/QLqC5qJ8LxVQCd6eO2ZkJqdjOPAmhMkYQ3ojjtoH2ybcFFNovoG4LTKb lcnZ6R/vGfjnF3GI5E67ywk7CyGV1CqDkT3jr13WuTddUK3/JsxnHyfQTFDv4MDByNdL W0rC+NkMqFVrzzPLwyBVmx84H8+h7W/uWLNkXmIPpa9Wu/M89qs6JAMVpc0uBL599i3Q bstaX2Mzp4jxAPwUsi7Ae68EegUqY/WQlT4PT6dsxpvGWTVjFpJNlbO9FhqRDG33PRqc U2kKdN81EIdw9evI8ARpWKmXpXb+x7uzT08JtnEPw3UxzZn4DMW2vJCvK0xemhGxaSO2 G9Yg== X-Gm-Message-State: AMCzsaUd1hTdsZ67BQH86yYfJtj1Yepbcl7G1hw5u5RKmo7fEGWN3lA6 2D6n1O6EMwK+ZLqb8RYqUNA2fQ== X-Google-Smtp-Source: ABhQp+RYKY2LYYLrIdvHoQu8Hb9RADCQWeZDft4PSUjal3Qll6mla3YULYjvNSfPaR4JZVvutrUteQ== X-Received: by 10.28.28.138 with SMTP id c132mr1779678wmc.48.1507910276928; Fri, 13 Oct 2017 08:57:56 -0700 (PDT) Received: from localhost.localdomain ([154.146.29.151]) by smtp.gmail.com with ESMTPSA id l19sm1636046wre.26.2017.10.13.08.57.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 08:57:56 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v4 2/3] drivers/irqchip: gic: make quirks matching conditional on init return value Date: Fri, 13 Oct 2017 16:56:06 +0100 Message-Id: <20171013155607.5211-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171013155607.5211-1-ard.biesheuvel@linaro.org> References: <20171013155607.5211-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As it turns out, the IIDR is not sufficient to distinguish between GICv3 implementations when it comes to enabling quirks. So update the prototype of the init() hook to return a bool, and interpret a 'false' return value as no match, in which case the 'enabling workaround' log message should not be printed. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-common.c | 5 +++-- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3-its.c | 12 +++++++++--- 3 files changed, 13 insertions(+), 6 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9ae71804b5dd..30017df5b54c 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -40,8 +40,9 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, for (; quirks->desc; quirks++) { if (quirks->iidr != (quirks->mask & iidr)) continue; - quirks->init(data); - pr_info("GIC: enabling workaround for %s\n", quirks->desc); + if (quirks->init(data)) + pr_info("GIC: enabling workaround for %s\n", + quirks->desc); } } diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 205e5fddf6da..3919cd7c5285 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -23,7 +23,7 @@ struct gic_quirk { const char *desc; - void (*init)(void *data); + bool (*init)(void *data); u32 iidr; u32 mask; }; diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 891de07fd4cc..c34f21c7a38e 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2728,28 +2728,34 @@ static int its_force_quiescent(void __iomem *base) } } -static void __maybe_unused its_enable_quirk_cavium_22375(void *data) +static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) { struct its_node *its = data; /* erratum 22375: only alloc 8MB table size */ its->device_ids = 0x14; /* 20 bits, 8MB */ its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; + + return true; } -static void __maybe_unused its_enable_quirk_cavium_23144(void *data) +static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) { struct its_node *its = data; its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; + + return true; } -static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) +static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) { struct its_node *its = data; /* On QDF2400, the size of the ITE is 16Bytes */ its->ite_size = 16; + + return true; } static const struct gic_quirk its_quirks[] = { From patchwork Fri Oct 13 15:56:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115782 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp887964qgn; Fri, 13 Oct 2017 08:58:02 -0700 (PDT) X-Received: by 10.98.103.93 with SMTP id b90mr1783197pfc.2.1507910282820; Fri, 13 Oct 2017 08:58:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507910282; cv=none; d=google.com; s=arc-20160816; b=Z0+cJmo23L2j0HPZcRXn2WXYU0qFH4kHRnq7mUArglbUo52gUZuGviy/Hc2Xg3IUhl 1oE00yXJzpDzoFDGeJi2/c9hMi/RWXQK8oq20TsBod9LcujoIjcbL7i+twGtAqtwdHWi 3IYdBaHsX+YkZa6UDTkXF3rxrS294VwxVf2egZ6vECJ68LZrbFwIWqCEqmC4J5AyVFRv TKh2vy3dataedcM7EfXmVsTh9L1Ge6p8hVzAMjCngsd7vsTI2uoHcd0SutOx40hxFqss sQmTjzqFp6D0IyZ85gWpUAxZm4Iu5bfoj9DwV8zoN2/iBKtB13kDcAhXcF862loE+rZY uv/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=v6N5jlfsitl2YHWYye+FNBuJirmeBGPIPtul4sO82rw=; b=eI7fzPymZXEZN/cdQ9w6jDjV2NHV7X7o8+ufJ44LF6PPwRp/k4WwreMSSYzKUzZj9W MQHtgChBWnghYIlIGI9li/q87TSFttof55nJwG13caPs484aEftLucQsWHIOkJQr7shz u+xhMhuv56kkFRICbEFtNJ16p1T9/tqjWA64p1tRGc6F2KvfMUcArd9/3pNfWLqNtj5u 6QgXrgKXaXMt/q+AwpTH1zvXauZrO9KsgmgeRAb41Z/+P9I349kYuSo0jBPh9I/pa5pp 6Ln8uGcrTUo7jkxPojKS92j6gppX2oKOxlhKdmqjo3sPK9ATjJLwaSm/68uVGSkIiPGG Ijyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OCb7N4Xe; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n8si794263plk.532.2017.10.13.08.58.02; Fri, 13 Oct 2017 08:58:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OCb7N4Xe; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751138AbdJMP6C (ORCPT + 6 others); Fri, 13 Oct 2017 11:58:02 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:51573 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdJMP6B (ORCPT ); Fri, 13 Oct 2017 11:58:01 -0400 Received: by mail-wr0-f170.google.com with SMTP id j14so1370993wre.8 for ; Fri, 13 Oct 2017 08:58:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=01p1cj1B+Ofr/XXTHbjZO7Z497vs74NYTtmq1yVAjTg=; b=OCb7N4Xeyitnca8Ow0+8NmcvC8QZZGl4udvDkOYnyY0IaS8Klh77lKbOkI7ZsJXa/I cvJBBeR9RWp6uJXrg5aL1+771y0ZSZXKgrB9zUi7sHuirisGNY+RupRWbNymbWZFr8yN wqQyPui+tsDRqS+0Pd8cHE55LNkJllN0luEi0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=01p1cj1B+Ofr/XXTHbjZO7Z497vs74NYTtmq1yVAjTg=; b=abeAQ6bYL4C+z4Px0NAd4GsSLDZhQ81nToRl8hrnGS9pgogCmqeCfY88h8uXjdwBI2 6VKgq5UeXDA7bmzNYd2cYqio/QnIgIiZJYhJJerpsEXBJK9xdTCqzCz4lX6RrCBrS/97 /iAJ7yr0Oort4WoATfpUnyabR6lM00Q/9FkwtQeLK9PRWf4je1pzXaczqRWHMLfBEt1B c+w18bJleU9xNSOXZQTaPO57QuHGtiQIbNDx4ayt4c4cKYXaHy9Bn7YFnLeKNigXxABO a068R7/vHUyHYLtCwHknlUK9sVU8O1i+p6/eYwBA/s1l4cnzqVzXf3HBv/qV/N55nAKV kV+g== X-Gm-Message-State: AMCzsaWEDJykmfPuooaL/sJB23LCuPbP2oaUC7Upb2i/GcTLlJQl9GQI VI9n0cN8P3nxyF7BvWWK25QV6Q== X-Google-Smtp-Source: AOwi7QDPelSqq2QGLgVY+ORgQpLxPSbBHOtEW8FIaXiwEIefEZxOm5VmV19QhcF2xJAvzZGvM7uJGg== X-Received: by 10.223.163.151 with SMTP id l23mr1768579wrb.73.1507910280037; Fri, 13 Oct 2017 08:58:00 -0700 (PDT) Received: from localhost.localdomain ([154.146.29.151]) by smtp.gmail.com with ESMTPSA id l19sm1636046wre.26.2017.10.13.08.57.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 08:57:59 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v4 3/3] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Date: Fri, 13 Oct 2017 16:56:07 +0100 Message-Id: <20171013155607.5211-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171013155607.5211-1-ard.biesheuvel@linaro.org> References: <20171013155607.5211-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 + arch/arm64/Kconfig | 8 ++ drivers/irqchip/irq-gic-v3-its.c | 83 +++++++++++++++++++- 3 files changed, 91 insertions(+), 4 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..a50d348df43b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optionally, an ITS node may have a sub-node describing a so-called pre-ITS: +- compatible : Should contain "socionext,synquacer-pre-its" +- reg : Specifies the base physical address and size of the pre-ITS window + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index c34f21c7a38e..f4321dac367a 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -83,6 +83,8 @@ struct its_baser { u32 psz; }; +struct its_device; + /* * The ITS structure - contains most of the infrastructure, with the * top-level MSI domain, the command queue, the collections, and the @@ -97,11 +99,15 @@ struct its_node { struct its_cmd_block *cmd_write; struct its_baser tables[GITS_BASER_NR_REGS]; struct its_collection *collections; + struct fwnode_handle *fwnode_handle; + u64 (*get_msi_base)(struct its_device *its_dev); struct list_head its_device_list; u64 flags; u32 ite_size; u32 device_ids; int numa_node; + unsigned int msi_domain_flags; + u32 pre_its_base; /* for Socionext Synquacer */ bool is_v4; }; @@ -1095,14 +1101,19 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); - struct its_node *its; u64 addr; - its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its_dev->its->get_msi_base(its_dev); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); @@ -2758,6 +2769,54 @@ static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) return true; } +static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); +} + +static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) +{ + struct its_node *its = data; + struct device_node *its_np = to_of_node(its->fwnode_handle); + struct device_node *np; + struct resource res; + u32 ids; + + if (!its_np) + return false; + + for_each_child_of_node(its_np, np) { + if (!of_device_is_compatible(np, "socionext,synquacer-pre-its")) + continue; + + if (of_address_to_resource(np, 0, &res)) { + pr_err("pre-ITS window unspecified!\n"); + return false; + } + + its->pre_its_base = (u32)res.start; + its->get_msi_base = its_irq_get_msi_base_pre_its; + + ids = ilog2(res.end - res.start + 1) - 2; + if (its->device_ids > ids) + its->device_ids = ids; + + /* the pre-ITS breaks isolation, so disable MSI remapping */ + its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; + return true; + } + return false; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -2783,6 +2842,19 @@ static const struct gic_quirk its_quirks[] = { .init = its_enable_quirk_qdf2400_e0065, }, #endif +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + { + /* + * The Socionext Synquacer SoC incorporates ARM's own GIC-500 + * implementation, but with a 'pre-ITS' added that requires + * special handling in software. + */ + .desc = "ITS: Socionext Synquacer pre-ITS", + .iidr = 0x0001143b, + .mask = 0xffffffff, + .init = its_enable_quirk_socionext_synquacer, + }, +#endif { } }; @@ -2811,7 +2883,7 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); - inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + inner_domain->flags |= its->msi_domain_flags; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -2965,6 +3037,9 @@ static int __init its_probe_one(struct resource *res, goto out_free_its; } its->cmd_write = its->cmd_base; + its->fwnode_handle = handle; + its->get_msi_base = its_irq_get_msi_base; + its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; its_enable_quirks(its);