From patchwork Tue Sep 22 10:16:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 292720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD1E7C4727F for ; Tue, 22 Sep 2020 10:17:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70AA92396D for ; Tue, 22 Sep 2020 10:17:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="UympiQXC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726534AbgIVKQ6 (ORCPT ); Tue, 22 Sep 2020 06:16:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIVKQn (ORCPT ); Tue, 22 Sep 2020 06:16:43 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29113C0613CF for ; Tue, 22 Sep 2020 03:16:43 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id z23so21970744ejr.13 for ; Tue, 22 Sep 2020 03:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H2zrh0T/aIHB5coIgfEht7vUXRrR/Y3M7r4qi6VXEaA=; b=UympiQXCt6fSNYJZEkM75bM6uu438A8LrRvvuV0VEK4dezP51mfXPLgU5RQOhOB22X XDxN2p3oHrEHqaHRYiR41TkRoI1jhS4h3CES20VdYQmPPgT62ARcqIO3I3n/pd0rw0mG Vw+/M37l87W9QW8uJKzAP9zQjRkjlpPt25zgfiIweFJN4Ltbpxk4NYG1v9VoCk5532mY hu2obc1tmMlAWTB5OlcwgJMvcqzICsPErQWt0eW9n+BwCRcPILiKLUF9NPTXTu0ECZV9 R6EV+3A+AcajLcXVuHTeXot4uPNVUU8lvMZ0aonIHZL7bh9+QWUSPRpvFC0905DEfgZT AeaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H2zrh0T/aIHB5coIgfEht7vUXRrR/Y3M7r4qi6VXEaA=; b=Bnr8BtXPDITbKmlZqCwVZhD9E8qOTdQbRrdEZtFPbHm1kQRpgBnm98GqOfgfhDUeG3 zAUoWa/ajn2Eby81+xe/LiRKjGAgtHHcB2jl9OlBwLkvrAb0v2GD5U8TUz5akDmLbPNO c58h13xp/F69PayQKfJ0b46gKGW47dS/40nQWz+hgdxhzORDUMhTb7vmbu0Fbiji+mSk JB15gro4+yrAdPb/SnOMTg+qJF/ShG3U7lgvKgsjSLz2Oiu8rp4lPWMPrEOtP9Z0DcOS WZb66+pOdfWBEIwFm0bznUgLZKy8IppisEBhv5ky/G+FKopw70+CYqI1mZADRKlQPO59 gghQ== X-Gm-Message-State: AOAM530KMX5r4XLd4ULstN8Ax7wwvSNZ90Ji9Z61Ji8Dne0CX+RblwuR qOuaqtq5m3Ae9BWe1d+6u+bRNg== X-Google-Smtp-Source: ABdhPJwjRDrTW32hpcyKevocJzPX9wpy+spdPh9kR2ZCuGoDnBVt/boBY3L8SR6IQqagqwm9zUQmqQ== X-Received: by 2002:a17:906:4a51:: with SMTP id a17mr3992258ejv.381.1600769801791; Tue, 22 Sep 2020 03:16:41 -0700 (PDT) Received: from localhost.localdomain ([88.207.4.22]) by smtp.googlemail.com with ESMTPSA id p3sm10595368edp.28.2020.09.22.03.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 03:16:41 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , Luka Perkov , Florian Fainelli Subject: [PATCH v5 1/2] net: mdio-ipq4019: change defines to upper case Date: Tue, 22 Sep 2020 12:16:31 +0200 Message-Id: <20200922101632.54896-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200922101632.54896-1-robert.marko@sartura.hr> References: <20200922101632.54896-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep partially used lower case. Lets change it to upper case in line with the rest of driver defines. Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli --- Changes since v4: * Rebase onto net-next.git drivers/net/mdio/mdio-ipq4019.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 1ce81ff2f41d..64b169e5a699 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -21,8 +21,8 @@ #define MDIO_CMD_ACCESS_CODE_READ 0 #define MDIO_CMD_ACCESS_CODE_WRITE 1 -#define ipq4019_MDIO_TIMEOUT 10000 -#define ipq4019_MDIO_SLEEP 10 +#define IPQ4019_MDIO_TIMEOUT 10000 +#define IPQ4019_MDIO_SLEEP 10 struct ipq4019_mdio_data { void __iomem *membase; @@ -35,7 +35,7 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus) return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, (busy & MDIO_CMD_ACCESS_BUSY) == 0, - ipq4019_MDIO_SLEEP, ipq4019_MDIO_TIMEOUT); + IPQ4019_MDIO_SLEEP, IPQ4019_MDIO_TIMEOUT); } static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) From patchwork Tue Sep 22 10:16:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 250119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B341C4727E for ; Tue, 22 Sep 2020 10:17:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF9242396D for ; Tue, 22 Sep 2020 10:17:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="qfjrHGnP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726419AbgIVKQ7 (ORCPT ); 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Tue, 22 Sep 2020 03:16:43 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH v5 2/2] net: mdio-ipq4019: add Clause 45 support Date: Tue, 22 Sep 2020 12:16:32 +0200 Message-Id: <20200922101632.54896-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200922101632.54896-1-robert.marko@sartura.hr> References: <20200922101632.54896-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org While up-streaming the IPQ4019 driver it was thought that the controller had no Clause 45 support, but it actually does and its activated by writing a bit to the mode register. So lets add it as newer SoC-s use the same controller and Clause 45 compliant PHY-s. Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Andrew Lunn --- Changes since v4: * Rebase onto net-next.git Changes since v3: * Rename MDIO_MODE_BIT to MDIO_MODE_C45 Changes since v2: * Fix missed reverse christmas tree Changes since v1: * Maintain reverse christmas tree drivers/net/mdio/mdio-ipq4019.c | 103 +++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 64b169e5a699..25c25ea6da66 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -12,6 +12,7 @@ #include #include +#define MDIO_MODE_REG 0x40 #define MDIO_ADDR_REG 0x44 #define MDIO_DATA_WRITE_REG 0x48 #define MDIO_DATA_READ_REG 0x4c @@ -20,6 +21,12 @@ #define MDIO_CMD_ACCESS_START BIT(8) #define MDIO_CMD_ACCESS_CODE_READ 0 #define MDIO_CMD_ACCESS_CODE_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_READ 2 + +/* 0 = Clause 22, 1 = Clause 45 */ +#define MDIO_MODE_C45 BIT(8) #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -41,19 +48,44 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus) static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + } /* issue read command */ writel(cmd, priv->membase + MDIO_CMD_REG); @@ -62,6 +94,15 @@ static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } + /* Read and return data */ return readl(priv->membase + MDIO_DATA_READ_REG); } @@ -70,23 +111,57 @@ static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + } /* issue write data */ writel(value, priv->membase + MDIO_DATA_WRITE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; /* issue write command */ + if (regnum & MII_ADDR_C45) + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; + else + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; + writel(cmd, priv->membase + MDIO_CMD_REG); /* Wait write complete */