From patchwork Wed Oct 11 05:37:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radha Mohan Chintakuntla X-Patchwork-Id: 115496 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp359900qgn; Tue, 10 Oct 2017 22:38:04 -0700 (PDT) X-Received: by 10.84.248.144 with SMTP id q16mr14470705pll.345.1507700284506; Tue, 10 Oct 2017 22:38:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507700284; cv=none; d=google.com; s=arc-20160816; b=CG2J7zl2zHB9kJ28Oe+uQ3orudVrVfXdrn0Jni1z1rGcnvPTlg0emav3aB4gtFCnT7 DXSPRe7wn8P2iUuvXn1LwUGUKPsKn4pCYILqdTQSZMLA5pL7znIMqO82MxdRLLh3rqyS EuypFmblZujkH8MCgu0rT/Hb2xxezRs/2PAUYKF2XoqW7SkrIstBwOhZ4oPltOHj/TaG WP6JL9ynUkQRBRFl5sR/qVS4pYoi8TfTsl8jshws63t5S5d/wllrLOTqPdv/fztru7sM 5NG6szpKIPSqwmEmvyoz/QKXW/YLbM3BqWMakvLUYxG3qgU64GA2DsOmqbdwM7uwbHOj 4ZQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=uUzqB0ZXJPw1u0sRdwsUdypOZg14ykP9vRXSoCYkfOc=; b=JCrZU4Q770YASaOu9LOASUNG7U3XJxXFvMIB2tw9ZF6JCj/nhLT8GsTv5mDlpnfEDj 78RLsHd38PrFaEGcRNWRWmo12kcYgjJG1GiLapCH+gT+3HylImy02htNDrced6leK3wZ VnUL88GtmqC2hWhrElsLl1wIh4dS1UOSJtIlUbJCmsQjWx2W4xUQRIr89AvSi4euXc7u n2Y1uxeHqnRqbBDMEKmoS3M2f2k3yFx7xP/9qVLo08s2P9rIIBf4mLE04KfGwdXsYgpf 9BgXesK05N0Vo6PWBZXCscNSrywVckvE8exQ9eqbxXT/HJ8KYvYEnrdh5e+rcFfX/msH oQbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=lXXl3Tex; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z96si10401200plh.681.2017.10.10.22.38.03; Tue, 10 Oct 2017 22:38:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=lXXl3Tex; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756746AbdJKFiB (ORCPT + 26 others); Wed, 11 Oct 2017 01:38:01 -0400 Received: from mail-qt0-f194.google.com ([209.85.216.194]:34399 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754285AbdJKFh6 (ORCPT ); Wed, 11 Oct 2017 01:37:58 -0400 Received: by mail-qt0-f194.google.com with SMTP id y45so1112266qty.1; Tue, 10 Oct 2017 22:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=uUzqB0ZXJPw1u0sRdwsUdypOZg14ykP9vRXSoCYkfOc=; b=lXXl3Texzln7JzJRk+6pk3+KSrx7ZPEk5VoLFE46jHqK5pFw5Ke1far0jwDYSgfI+m zVf1DRpMjm29vcgbzTNwblDc+shJ3glN9qWv+celM2BPSYRQ4e/MnDleSQK7ba5pTxsF K8nMlvKhnhWYXwHZvjabqHS1FxmXkStNsdWA+a8OqCCp5+CzqaiwyhebsitbkhvzwyTn Uu2qk8IhKqzk2Wj7H+j1pmQaQwvm1EHl/5gHDvPimddKtLpixGObcmR+KDSbhLuW+6du TTRsVBQ56JsWKHrM8vGdoJkU/ZHGWTG+v1OXl55IuIMZpu6WGlYjOM6wIGWjL2ZZvnNN IEyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uUzqB0ZXJPw1u0sRdwsUdypOZg14ykP9vRXSoCYkfOc=; b=daEg8OoV9sdhj/PfyYBZP5uBJ7BZNWC2fA6lgMrL5VoNad7hJddERFHNt+aCCtCNr+ qZ6klwxCwuaY3GO/oegiqtGP1R/DIWfhYZ3LRBmJ2Yi+mMZbI9+5lfAAr7jr5FS4IfXg SmME8nUw8FmQZ3d37STsCO5O+0bVMoFmNiQ6gzppKahP2ZXg8C+9DGNvPXxGujWn+1pu /xNzZCQzGPeuSyIDMAA9h7lob4/IKka48GviqsoaNpynCJtIwLAXxFqYq8ZUw37eeG/S YtugXjV9wCCcPjSYsxCovGXO7Euax22kUW4Tyk5YiWwXHpT89wc1Y4d131bxZ4q61yiJ 2pkA== X-Gm-Message-State: AMCzsaX8tkTdZhr0rdIdbVBZT8ZMWZz6dIAde4HIjJNh/yUHffVf/Q2R eYx/JxakXRsxu5h1SW/GSq4= X-Google-Smtp-Source: AOwi7QB5SUgLlJSOjfuE6+lCOcu/IHFWPaulVqnk5/r72/bIGIBmvbE+pMrzL7z/K5w+qoJRgGWVlg== X-Received: by 10.37.232.2 with SMTP id k2mr3536539ybd.333.1507700278068; Tue, 10 Oct 2017 22:37:58 -0700 (PDT) Received: from localhost.localdomain (50-233-148-156-static.hfc.comcastbusiness.net. [50.233.148.156]) by smtp.gmail.com with ESMTPSA id c17sm5161468ywk.103.2017.10.10.22.37.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Oct 2017 22:37:57 -0700 (PDT) From: Radha Mohan Chintakuntla To: tj@kernel.org, linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Radha Mohan Chintakuntla Subject: [PATCH] ahci: Add support for Cavium's fifth generation SATA controller Date: Tue, 10 Oct 2017 22:37:51 -0700 Message-Id: <1507700271-12910-1-git-send-email-mohun106@gmail.com> X-Mailer: git-send-email 1.7.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Radha Mohan Chintakuntla This patch adds support for Cavium's fifth generation SATA controller. It is an on-chip controller and complies with AHCI 1.3.1. As the controller uses 64-bit addresses it cannot use the standard AHCI BAR5 and so uses BAR4. Signed-off-by: Radha Mohan Chintakuntla --- drivers/ata/ahci.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) -- 1.7.1 diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 9f78bb0..5443cb7 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -57,6 +57,7 @@ enum { AHCI_PCI_BAR_STA2X11 = 0, AHCI_PCI_BAR_CAVIUM = 0, AHCI_PCI_BAR_ENMOTUS = 2, + AHCI_PCI_BAR_CAVIUM_GEN5 = 4, AHCI_PCI_BAR_STANDARD = 5, }; @@ -1570,8 +1571,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ahci_pci_bar = AHCI_PCI_BAR_STA2X11; else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; - else if (pdev->vendor == 0x177d && pdev->device == 0xa01c) - ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; + else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { + if (pdev->device == 0xa01c) + ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; + if (pdev->device == 0xa084) + ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; + } /* acquire resources */ rc = pcim_enable_device(pdev);