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Add bindings for the MMCX power domain. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.28.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml index 0b905a4e9ada..6325d9969913 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -66,6 +66,16 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + + power-domain-names: + items: + - const: mmcx + + required-opps: + maxItems: 1 + required: - compatible - reg @@ -81,6 +91,7 @@ examples: - | #include #include + #include clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0x0af00000 0x10000>; @@ -105,5 +116,22 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + /* this is a part of sm8250 setup the power domain example */ + power-domains = <&rpmhpd SDM845_CX>; + power-domain-names = "mmcx"; + required-opps = <&rpmhpd_opp_low_svs>; + }; + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + }; }; ... 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Use dev_pm/opp to enable corresponding power domain. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 56 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 5 ++++ 2 files changed, 57 insertions(+), 4 deletions(-) -- 2.28.0 diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index bfc4ac02f9ea..a522e062a79a 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -110,13 +111,31 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) return -ETIMEDOUT; } +int gdsc_toggle_on(struct gdsc *sc) +{ + if (sc->rsupply) + return regulator_enable(sc->rsupply); + if (sc->pd_dev) + return dev_pm_genpd_set_performance_state(sc->pd_dev, sc->pd_opp); + return 0; +} + +int gdsc_toggle_off(struct gdsc *sc) +{ + if (sc->pd_dev) + return dev_pm_genpd_set_performance_state(sc->pd_dev, 0); + if (sc->rsupply) + return regulator_disable(sc->rsupply); + return 0; +} + static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) { int ret; u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK; - if (status == GDSC_ON && sc->rsupply) { - ret = regulator_enable(sc->rsupply); + if (status == GDSC_ON) { + ret = gdsc_toggle_on(sc); if (ret < 0) return ret; } @@ -153,8 +172,8 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) ret = gdsc_poll_status(sc, status); WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); - if (!ret && status == GDSC_OFF && sc->rsupply) { - ret = regulator_disable(sc->rsupply); + if (!ret && status == GDSC_OFF) { + ret = gdsc_toggle_off(sc); if (ret < 0) return ret; } @@ -407,6 +426,27 @@ int gdsc_register(struct gdsc_desc *desc, return PTR_ERR(scs[i]->rsupply); } + for (i = 0; i < num; i++) { + if (!scs[i] || !scs[i]->domain) + continue; + + scs[i]->pd_opp = of_get_required_opp_performance_state(dev->of_node, scs[i]->perf_idx); + if (scs[i]->pd_opp < 0) + return scs[i]->pd_opp; + + scs[i]->pd_dev = dev_pm_domain_attach_by_name(dev, scs[i]->domain); + if (IS_ERR(scs[i]->pd_dev)) { + ret = PTR_ERR(scs[i]->pd_dev); + /* Single domain has been already attached, so reuse dev */ + if (ret == -EEXIST) { + scs[i]->pd_dev = dev; + } else { + scs[i]->pd_dev = NULL; + goto pm_detach; + } + } + } + data->num_domains = num; for (i = 0; i < num; i++) { if (!scs[i]) @@ -428,6 +468,12 @@ int gdsc_register(struct gdsc_desc *desc, } return of_genpd_add_provider_onecell(dev->of_node, data); + +pm_detach: + for (i = 0; i < num; i++) + if (scs[i]->pd_dev) + dev_pm_domain_detach(scs[i]->pd_dev, false); + return ret; } void gdsc_unregister(struct gdsc_desc *desc) @@ -443,6 +489,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + if (scs[i]->pd_dev && scs[i]->pd_dev != dev) + dev_pm_domain_detach(scs[i]->pd_dev, true); } of_genpd_del_provider(dev->of_node); } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index bd537438c793..d58575f8f25f 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -57,6 +57,11 @@ struct gdsc { const char *supply; struct regulator *rsupply; + + const char *domain; + unsigned int perf_idx; + struct device *pd_dev; + int pd_opp; }; struct gdsc_desc { From patchwork Fri Sep 11 13:09:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 249723 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ecf:0:0:0:0 with SMTP id i15csp1649128ilk; Fri, 11 Sep 2020 06:12:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUGTHQEkJFbrn7/2Yzsvniug+eyeTYHByj3gUm9rQMYSNhSpR7I+czQXU2IWXld0IuiqwQ X-Received: by 2002:a05:6402:6d6:: with SMTP id n22mr1886038edy.79.1599829966252; Fri, 11 Sep 2020 06:12:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599829966; cv=none; d=google.com; s=arc-20160816; b=dMjgIJ/FtRppRQl97s2Sr64MuAMgZX9BXTDfccok8gMKRDoLilhrTdmBrP0N8m+HhJ w55/fTXvbH9QlFycUsmEQbe0aa3yj0ABSok9L/H0lwEP++Aw8BKhOjxZlHkLhSTleVwG BjoYsuvuKtwxCjDgZt6AQffO2yK1yt2bP8sTS2b63Z96mWmkG3c4B9rC8xvNPKUEYaQR bjJI+ujis/xIJs51pDdjLbrK+RQB5XajNGKwZsGAx/oNAvCh+gOXRBF4QINOe695uTbm CriTLZFobQpGwFxUwibjNPKwiHyUfxOhUMp/7LWbTkPEG+c+0OAyIwlcKgWZ87uYKAx6 KmZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KSlhvEq07UrSHzoeR1SRzs3RyWctK5k6m6swaX7LLqY=; b=c9rer4aZCb6dH8TCIHyM3PYX3in8dNzC24mZO39WWd5QWdEj0JCsv0jAL20XOLKAHL MBECJSKqaLEbdzMTRi0YjjEJzpDhV060mdGNc0nGMAZ8kQt2EjU6IakAGqKzgGSWrNTy /okI5PcR2+Cl2ej4NHKI5fkFKhLAMWHe+QJqZENUVWG3yQlPjF0x/dwo7XMXQ/HL06Xs tOj4izXGmzvCSVyZ4e0xUbPCtUk97BENTZFGNWZ76wUqH38rcJz4Qyq68rm4Y+hOwshv PVQdiRrvE80kx0HgBwoGO4rMvyJVKEiOH1X1IfrSY9odQxYAtSx1MJL3hzlGLUU/m7S5 ydvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wFaVSsWY; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Enable using this power domain for the gdsc. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.28.0 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 7c0f384a3a42..fc5fb2b2fe5e 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -970,6 +970,8 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, + .domain = "mmcx", + .perf_idx = 0, }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Fri Sep 11 13:09:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9140FC433E2 for ; Fri, 11 Sep 2020 14:35:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47F132226B for ; Fri, 11 Sep 2020 14:35:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sEuCMNpN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726160AbgIKOfi (ORCPT ); Fri, 11 Sep 2020 10:35:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbgIKNLy (ORCPT ); Fri, 11 Sep 2020 09:11:54 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9A0CC0617A4 for ; Fri, 11 Sep 2020 06:10:05 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id b19so12338976lji.11 for ; Fri, 11 Sep 2020 06:10:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JSPHG+gWrol4xtMWqlVawkUp7PUHXa4piQC1yx4WIUQ=; b=sEuCMNpNZYYuAs0LAOewYrhOb/4Ro2IUzL3kV17d/lgV7TVvfrubtNKkZAdRvWopCR Eji5hFzeP6LDqZAVhwLcGoVZOrdveHmVbI+MPe4vI+tGD3TgHQHJ3Utvz/UymyXWuMWU HN3mJ4oMGNRoQWQNOBAnSsTkm2V+lqdJSknF0yt1SqCvhZruKP0Mcem0bPnN3j64tIkV VuPa1w9xzlajgmQNMLKwPq0z8oCVgJgEL+jsnOK05rwpp/s8eFou1NsSQpvSilYsiJm1 u15+8CJjnNj1jfCsweCkHWaZqdYgAgyEBuzz+bv3IErK3ObQn0zbpwTHk6LB8DNKNZKP nKrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JSPHG+gWrol4xtMWqlVawkUp7PUHXa4piQC1yx4WIUQ=; b=dcoip7gME7kzq+RRrMAqjSC+XAjHjys4XKfdTtCreSRJE0zv8GGvjm93S5G6R9rh+n pIMkGHfKObM3ziRsdQAU2lHxBGtNkbPqIoTJwwpF1BBqIAudcoqIfwOEjgYt+21deDno 89Ofut9d8EnId9+zS+7Z1tUw7GkQzqAfyPc0U2EhTukbGzD/NuuJURklawsLrrs8x5AU puA32hDhOw5BjD295bu2+tSiVLJyGm0dlf5nwWGIXXmiDVmBfQjG3VONyb/U1jHlDmQQ cZ3gMcvYPkRwmvgetTYpI8IvzeQcwDZBe+r4Edz8ub4qG+WT0REjS1co9+D1ROJgz7zb IDPA== X-Gm-Message-State: AOAM533vfjYCbVdsRRD87WMt5GMDzxbXXkqTcASdeKP5YT7KeFWVbSoq 07bYSB05aP9sEoMWH4sYBhifzQ== X-Google-Smtp-Source: ABdhPJweLFzvwR0GykH9HcZst3Q+Y2PFxn41CgZ06JQB1cBkINnhG0UexuZHCND63cR+N8Y6v2gFTQ== X-Received: by 2002:a2e:8153:: with SMTP id t19mr851775ljg.334.1599829803419; Fri, 11 Sep 2020 06:10:03 -0700 (PDT) Received: from eriador.lan ([188.162.64.141]) by smtp.gmail.com with ESMTPSA id 10sm429500lfq.64.2020.09.11.06.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2020 06:10:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek , Stephen Boyd , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , devicetree@vger.kernel.org Subject: [RFC 4/4] arm64: dts: qcom: sm8250: pin MMCX to stop the board from crashing Date: Fri, 11 Sep 2020 16:09:50 +0300 Message-Id: <20200911130950.578483-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200911130950.578483-1-dmitry.baryshkov@linaro.org> References: <20200911130950.578483-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use MMCX domain to power up MDSS_GDSC. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 5045fe89a494..c42640228ceb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1732,6 +1732,9 @@ dp_out: endpoint { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; + power-domains = <&rpmhpd SM8250_MMCX>; + power-domain-names = "mmcx"; + required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>,