From patchwork Fri Sep 11 08:50:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 249713 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ecf:0:0:0:0 with SMTP id i15csp1457447ilk; Fri, 11 Sep 2020 01:50:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxN8YPg4RhDS9KpRW1JlF7ZgJHOM6vdoZV3E+aD67K37txMfavZEj9rz+ZJbE27sguuk0If X-Received: by 2002:a05:6402:1016:: with SMTP id c22mr929851edu.89.1599814217121; Fri, 11 Sep 2020 01:50:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599814217; cv=none; d=google.com; s=arc-20160816; b=NAWZ1omf2QobPlzncFFoR4KZpwi0z4RnIIk6c6dupiJg1moKk5udVFi1hMdToTF8tV M+RmJ02twZZAAYKy556HQeSm6vJZpdmQni/lmVaeL/lXxl0+ZlawBEpSZ7ixnpoAMqzB 4FFWj9Tc0zgTikJIThC+9lmlWumFV9Q3CMgSkOyHJk14oF0krmlcmBjKSvMS6RrFqsQc 49ecfDP50+AgWgTjEcdwzPglSwIdG7pisc0f0E6BYnaD1QngM+oapvnCfU2I+tGLgzIL AXeX8wufIx6M6NSOMbdtHPb3VFDX/wJywtQdL1Eql/J6a+vd2nbe/lxxYClLXhK1VaUH IaUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=NES0+Yk8OnWgH95/pv+pL4gMwYf8bdYustHRFZhhU/U=; b=knEcRggpUunjrd/k5r4A+VRibXSpb2GQXexUZDCwYK+slPRCHnFeegVAgqKW+bee7B Y/SGeRoMOgxFxrWvQjwCUgZlYGbEjAsKFEtQfyrhiOj4+OKht1l3M5VyzwuBI8lw8m5i ODyRGyecEaAx4rvd48Z/DxQo7lDZ+UgG+LOTB1mcYP0E8Bsva6fGzNOACas0Z2YH3Ava pQRgVVFLSYN8XW1Pd8eN3cLFDARDxwA6K1jFKgVEzLAtrLn6ZSc2q464EahDDgC41P6W LUppi5dS6NXvOv2pIgAzi3zCRNortcISdJwciIOChYBiZr1tRl2cxs2/LgOrpbdXGdke F30w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j14si815706edy.412.2020.09.11.01.50.16; Fri, 11 Sep 2020 01:50:17 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725730AbgIKIuQ (ORCPT + 6 others); Fri, 11 Sep 2020 04:50:16 -0400 Received: from mx.socionext.com ([202.248.49.38]:29483 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725554AbgIKIuP (ORCPT ); Fri, 11 Sep 2020 04:50:15 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 11 Sep 2020 17:50:14 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 28C0B1800EE; Fri, 11 Sep 2020 17:50:14 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 11 Sep 2020 17:50:14 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 9D5351A050C; Fri, 11 Sep 2020 17:50:13 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri , Rob Herring Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 1/3] dt-bindings: PCI: uniphier: Add iATU register description Date: Fri, 11 Sep 2020 17:50:01 +0900 Message-Id: <1599814203-14441-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Fri Sep 11 08:50:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 249715 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ecf:0:0:0:0 with SMTP id i15csp1457509ilk; Fri, 11 Sep 2020 01:50:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxx+PDtRtaE3a1jb7hONwg3g+5Iqm85jopondHNj5qYCytOubhpmoUjPK4q93aJTrbFRVSx X-Received: by 2002:a17:906:3ad0:: with SMTP id z16mr1067934ejd.193.1599814223461; Fri, 11 Sep 2020 01:50:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599814223; cv=none; d=google.com; s=arc-20160816; b=PELXFT5LJT53zwgGcTzo1Ju93ByQ2sJa078wqTxLjUSe32TEmNwKY7mnvex3AO2ii9 FqmXiR3NwlzD47ZankSN6AlsZ+oM3Bw0HKMZE/UOrm29N50BGbmmO8xD1bXGC7d9VoiF 3Mcf0j89atU++3jA5S+vJpuGzyKkOkHbjoqERAu0O9/w2OD1dZ2gJLAS1jCcEyklVfvP rhHQoXKh+21Nn9PUAeaQZebK93TDEWrhSWQ+iHIsV6hVFKo255UBA4Yfu7NXTE+kSWY8 vsuj4G4Rj61Lfm75NWc7pe0VW6NEMogeN5Od/yN5mr0ufS3EI49lNbL2KQGQmCd3QIR6 5MZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=mToNfLR1Q/w/9WVdvjF7kxZzrzGbGz9ecJUT7xh1qUE=; b=IOa8k9k88kpfVvOawgFe8ufwMtkSNjngreUOLC4WvFMW36P2uJ/gFySHlzcqJadlmp 9sO0dCIb/cQLBPrdCUwfrEFwMmbptKoE2RG0GdZ5GXJNpVZRgjPAYhbkPIJT9lytgAHl fUywbJLfDnj86WVZQTYhuiO6QHWGfzNjU1kPR+ODZbiJj5V8Nm9QUfJU2Gck2wSY28Mj ud8zv62TZ0GJkXp5o90CC0Fmg7bHoH0QfpkMKJEoZmt555vQb2q+EWI43qj7YBqEexQV bH6vtxAHWcWjFh6MqFuPIuxoI3gcCV/g4eyFTCJIiG7Ad+GkZWRQeJWD7PO/e7j588Vu GHog== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ng3si869352ejb.720.2020.09.11.01.50.23; Fri, 11 Sep 2020 01:50:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725809AbgIKIuW (ORCPT + 6 others); Fri, 11 Sep 2020 04:50:22 -0400 Received: from mx.socionext.com ([202.248.49.38]:29490 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725613AbgIKIuR (ORCPT ); Fri, 11 Sep 2020 04:50:17 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 11 Sep 2020 17:50:15 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 392C960060; Fri, 11 Sep 2020 17:50:15 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 11 Sep 2020 17:50:15 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 8AA521A0508; Fri, 11 Sep 2020 17:50:14 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri , Rob Herring Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 2/3] PCI: dwc: Add common iATU register support Date: Fri, 11 Sep 2020 17:50:02 +0900 Message-Id: <1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 4d105ef..4a360bc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "../../pci.h" @@ -526,11 +527,16 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 val; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct platform_device *pdev; if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; - if (!pci->atu_base) + pdev = of_find_device_by_node(np); + if (!pci->atu_base && pdev) + pci->atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR_OR_NULL(pci->atu_base)) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; } dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? From patchwork Fri Sep 11 08:50:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 249714 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ecf:0:0:0:0 with SMTP id i15csp1457498ilk; Fri, 11 Sep 2020 01:50:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHiEqM64BrSNxmh+8AXgcE+IAgAmfkqOJf8gyxn2wYSPspWmx0j9iER6459oj2hYoqn98H X-Received: by 2002:a17:906:8695:: with SMTP id g21mr976897ejx.504.1599814222673; Fri, 11 Sep 2020 01:50:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599814222; cv=none; d=google.com; s=arc-20160816; b=UFMlPi3Ivop6jmkOVJtOM5tnCaRTBl16t0El5muQdD7zpXAlBWnwxzmZFXdbrCRig9 yJS7cu1IurgcZqZsSw6KSxS8QnxHRywAkexpVGmnRtgCcUYWYVnV7gM1YHnKnkoMxQgD Ym1uNP7+f/tlVoL/m6GwOCGVOhlsymNP908SuXg6xJQ6zD18lcK9ScNZKRgeBOpdVLjt snmaJWSncw5mbfgKwbv/tIE8ZGAn1WiyWXv8MubvHXzNQv1hN6Sj7dNTbueoIU2Km2Ok aYT4aLMNqoq6IZhJx4eWosI+CVr29q4tIBK7mur+DF8VY7r+V6C0+rWZdNbT0zIgndnf hpxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=wCSJRUZ8zHysaAVGAbBQ0WrSjPhtGf2RcLHV/jxXgAM=; b=ACpF9DiNQxibakq3lgNSsPuY0nVQiyRRj65P/vJ31lbvhxwK4xwy0cpn4MUqkA3plr Bjc89bgXfWFRm/mMPHcGFUq9LeEe4JiLk7J/f/IfthE1jZ0JdSHl545TyVm0Ba6g4OJy gWM78I4jb/qqJohPsJl4tueXa5sjjfVQY9LTlxxMxwQuh2QVz+RO9SvLMCeDC8FxFhyw q8uhr+oJS543rBy+da54Knb8UBHGw31OdIsFTHYg9X74Z9MLftAMOjV5wCSDYVsw87Jw nBfeHIyZ9y4Tmqeffgalk4inwA782XzKyJeGnSB+Hs120YIifFosY11zusRVrnYH/5q7 3SNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ng3si869352ejb.720.2020.09.11.01.50.22; Fri, 11 Sep 2020 01:50:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725805AbgIKIuU (ORCPT + 6 others); Fri, 11 Sep 2020 04:50:20 -0400 Received: from mx.socionext.com ([202.248.49.38]:29476 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgIKIuR (ORCPT ); Fri, 11 Sep 2020 04:50:17 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 11 Sep 2020 17:50:16 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 252741800EE; Fri, 11 Sep 2020 17:50:16 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 11 Sep 2020 17:50:16 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 6316D1A0508; Fri, 11 Sep 2020 17:50:15 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri , Rob Herring Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 3/3] PCI: keystone: Remove iATU register mapping Date: Fri, 11 Sep 2020 17:50:03 +0900 Message-Id: <1599814203-14441-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pci-keystone.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b554812..a222728 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1154,7 +1154,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct keystone_pcie *ks_pcie; struct device_link **link; struct gpio_desc *gpiod; - void __iomem *atu_base; struct resource *res; unsigned int version; void __iomem *base; @@ -1275,23 +1274,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - if (pci->version >= 0x480A) { - atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); - if (IS_ERR(atu_base)) { - ret = PTR_ERR(atu_base); - goto err_get_sync; - } - - pci->atu_base = atu_base; - + if (pci->version >= 0x480A) ret = ks_pcie_am654_set_mode(dev, mode); - if (ret < 0) - goto err_get_sync; - } else { + else ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; - } + if (ret < 0) + goto err_get_sync; switch (mode) { case DW_PCIE_RC_TYPE: