From patchwork Tue Oct 10 20:32:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 115472 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp3893458edb; Tue, 10 Oct 2017 13:32:55 -0700 (PDT) X-Received: by 10.98.89.9 with SMTP id n9mr14594362pfb.133.1507667575312; Tue, 10 Oct 2017 13:32:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507667575; cv=none; d=google.com; s=arc-20160816; b=yFcrnVUbYAxTlhKY5RljJBPmteuwpMgGspJdby8v+8NwLDa+NKhePw3bdGlsT3MWOg USoxj0UfLPF3B6iVP2TPV0A9j42qEOU4TI8zYnvKTEG2NJ5BXXQTKkdvrc6D/ysemM95 xYS+YT3ItAgqLhBDxLcaACIRrUqHVFoXfg3lhC0AVYoppegdgfSVziyuUXSApNWF/gCp +baqgY+FoxWqSqJOnsdCywZj9rYEzPS6lkWCjhLoZdeowaUre7684+/MS93mFDXcUCTn +um4+3cuJgHAnL8g/2XNSSBTgv0tvTzoJoIbQQQfGXe00SvlaZRgI33zUBtJKqJeXyYM G07A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CXIGf5xgU5HAb3cBGJld6R9Pp5V7nvPDJzpoiM/pxEI=; b=f2lufuukVL8H+LQZsrgoxL9ID/UjisDIZRnXQ0ro6xTDs5axIUpL+yY+4ZxCkedee3 go2TyCVKePWV5iwdS/yGW0khJj2RhJJiReUarit25D16eDJAZunty2fXwkdEKEm5/5Mk skxxEHekHJpDsJxrc0oFEBsqhcVdt5B9B915oHpqUpduhC8IzSTMoCumEkkNJE16YJPU thYMhHXfIdjuAOPQ8Ub8g9S57WEL268ts/3FU4UaLKrrpo9S5C3ueJN7BnAz01LzJgFt 0cw457YerC97+mUzqL6xN3urF2APRolEk66cxjBmZlTAIsoni41TsaqBKvrHpuQvQ/Eu Rx4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C1qAl1s+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id f14sm5689739itc.13.2017.10.10.13.32.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 Oct 2017 13:32:16 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH 1/2] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Date: Tue, 10 Oct 2017 14:32:12 -0600 Message-Id: <1507667533-21707-2-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507667533-21707-1-git-send-email-mathieu.poirier@linaro.org> References: <1507667533-21707-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose As per coresight standards, PIDR2 register has the following format : [2-0] - JEP106_bits6to4 [3] - JEDEC, designer ID is specified by JEDEC. However some of the drivers only use mask of 0x3 for the PIDR2 leaving bits [3-2] unchecked, which could potentially match the component for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier Cc: Linus Walleij Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- .../coresight/coresight-dynamic-replicator.c | 4 ++-- drivers/hwtracing/coresight/coresight-etb10.c | 4 ++-- drivers/hwtracing/coresight/coresight-etm3x.c | 24 +++++++++++----------- drivers/hwtracing/coresight/coresight-funnel.c | 4 ++-- drivers/hwtracing/coresight/coresight-stm.c | 8 ++++---- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++-- drivers/hwtracing/coresight/coresight-tpiu.c | 4 ++-- 7 files changed, 26 insertions(+), 26 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c index accc2056f7c6..8f4357e2626c 100644 --- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c @@ -199,8 +199,8 @@ static const struct dev_pm_ops replicator_dev_pm_ops = { static const struct amba_id replicator_ids[] = { { - .id = 0x0003b909, - .mask = 0x0003ffff, + .id = 0x000bb909, + .mask = 0x000fffff, }, { /* Coresight SoC-600 */ diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 56ecd7aff5eb..e03e58933141 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -748,8 +748,8 @@ static const struct dev_pm_ops etb_dev_pm_ops = { static const struct amba_id etb_ids[] = { { - .id = 0x0003b907, - .mask = 0x0003ffff, + .id = 0x000bb907, + .mask = 0x000fffff, }, { 0, 0}, }; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index e5b1ec57dbde..39f42fdd503d 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -901,33 +901,33 @@ static const struct dev_pm_ops etm_dev_pm_ops = { static const struct amba_id etm_ids[] = { { /* ETM 3.3 */ - .id = 0x0003b921, - .mask = 0x0003ffff, + .id = 0x000bb921, + .mask = 0x000fffff, .data = "ETM 3.3", }, { /* ETM 3.5 - Cortex-A5 */ - .id = 0x0003b955, - .mask = 0x0003ffff, + .id = 0x000bb955, + .mask = 0x000fffff, .data = "ETM 3.5", }, { /* ETM 3.5 */ - .id = 0x0003b956, - .mask = 0x0003ffff, + .id = 0x000bb956, + .mask = 0x000fffff, .data = "ETM 3.5", }, { /* PTM 1.0 */ - .id = 0x0003b950, - .mask = 0x0003ffff, + .id = 0x000bb950, + .mask = 0x000fffff, .data = "PTM 1.0", }, { /* PTM 1.1 */ - .id = 0x0003b95f, - .mask = 0x0003ffff, + .id = 0x000bb95f, + .mask = 0x000fffff, .data = "PTM 1.1", }, { /* PTM 1.1 Qualcomm */ - .id = 0x0003006f, - .mask = 0x0003ffff, + .id = 0x000b006f, + .mask = 0x000fffff, .data = "PTM 1.1", }, { 0, 0}, diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 77642e0e955b..fd3c396717f6 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -248,8 +248,8 @@ static const struct dev_pm_ops funnel_dev_pm_ops = { static const struct amba_id funnel_ids[] = { { - .id = 0x0003b908, - .mask = 0x0003ffff, + .id = 0x000bb908, + .mask = 0x000fffff, }, { /* Coresight SoC-600 */ diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 92a780a6df1d..15e7ef3891f5 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -917,13 +917,13 @@ static const struct dev_pm_ops stm_dev_pm_ops = { static const struct amba_id stm_ids[] = { { - .id = 0x0003b962, - .mask = 0x0003ffff, + .id = 0x000bb962, + .mask = 0x000fffff, .data = "STM32", }, { - .id = 0x0003b963, - .mask = 0x0003ffff, + .id = 0x000bb963, + .mask = 0x000fffff, .data = "STM500", }, { 0, 0}, diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 2ff4a66a3caa..0ea04f588de0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -439,8 +439,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) static const struct amba_id tmc_ids[] = { { - .id = 0x0003b961, - .mask = 0x0003ffff, + .id = 0x000bb961, + .mask = 0x000fffff, }, { /* Coresight SoC 600 TMC-ETR/ETS */ diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index d7a3e453016d..bef49a3a5ca7 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -194,8 +194,8 @@ static const struct dev_pm_ops tpiu_dev_pm_ops = { static const struct amba_id tpiu_ids[] = { { - .id = 0x0003b912, - .mask = 0x0003ffff, + .id = 0x000bb912, + .mask = 0x000fffff, }, { .id = 0x0004b912, From patchwork Tue Oct 10 20:32:13 2017 Content-Type: text/plain; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id f14sm5689739itc.13.2017.10.10.13.32.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 Oct 2017 13:32:18 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH 2/2] doc: coresight: correct usage for disabling idle states Date: Tue, 10 Oct 2017 14:32:13 -0600 Message-Id: <1507667533-21707-3-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507667533-21707-1-git-send-email-mathieu.poirier@linaro.org> References: <1507667533-21707-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan In the coresight CPU debug document it suggests to use 'echo' command to set latency request to /dev/cpu_dma_latency so can disable all CPU idle states, but in fact this doesn't work. This is because when the command 'echo' exits, it releases the device node's file descriptor and the kernel release function removes the QoS constraint; finally when the command 'echo' finished there have no constraint imposed on cpu_dma_latency. This patch changes to use 'exec' to access '/dev/cpu_dma_latency', the command 'exec' can avoid the file descriptor to be closed so we can keep the constraint on cpu_dma_latency. This patch also adds the info for reference docs for PM QoS and cpuidle sysfs. Cc: Jonathan Corbet Cc: Sudeep Holla Reported-by: Kim Phillips Suggested-by: Mathieu Poirier Signed-off-by: Leo Yan Signed-off-by: Mathieu Poirier --- Documentation/trace/coresight-cpu-debug.txt | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight-cpu-debug.txt index b3da1f90b861..2b9b51cd501e 100644 --- a/Documentation/trace/coresight-cpu-debug.txt +++ b/Documentation/trace/coresight-cpu-debug.txt @@ -149,11 +149,23 @@ If you want to limit idle states at boot time, you can use "nohlt" or At the runtime you can disable idle states with below methods: -Set latency request to /dev/cpu_dma_latency to disable all CPUs specific idle -states (if latency = 0uS then disable all idle states): -# echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency - -Disable specific CPU's specific idle state: +It is possible to disable CPU idle states by way of the PM QoS +subsystem, more specifically by using the "/dev/cpu_dma_latency" +interface (see Documentation/power/pm_qos_interface.txt for more +details). As specified in the PM QoS documentation the requested +parameter will stay in effect until the file descriptor is released. +For example: + +# exec 3<> /dev/cpu_dma_latency; echo 0 >&3 +... +Do some work... +... +# exec 3<>- + +The same can also be done from an application program. + +Disable specific CPU's specific idle state from cpuidle sysfs (see +Documentation/cpuidle/sysfs.txt): # echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable