From patchwork Wed Sep 9 06:58:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249436 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp147656ilg; Tue, 8 Sep 2020 23:59:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFZiM5oWU8XKQsVnrDH+db+wB+G8Cn442iVngCmid0gEcx26j8mc0k1F9nDbBOr0zC3I5m X-Received: by 2002:a17:907:104c:: with SMTP id oy12mr2306832ejb.450.1599634781515; Tue, 08 Sep 2020 23:59:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599634781; cv=none; d=google.com; s=arc-20160816; b=lVIKPIqiKhNcAp0lm5TysS/cQnGWuRQOxcR6SHoGDrAJKgstxxiIRgsF871PzeBMDL yEYOHI4CevRIkuJnd0K+XjupP/1Wafw2GDHlGvwB6tzkbJOVKndT4gM5VEGprmpScN5u oOU1g6k6fV+Wmq2BKgcF3I0w7Lr4KqUP+Dn+fS56S4ST+xApMAOfFZtyyoagMlPXmmd3 ebjYbELLj417XY4n8J9L5Ew/2cr7XzkMZt2LSfa8HNMTuxm+ELl4GSws8oalLwSv9Bb5 OzoZVapplgpkl75ZffdZVA6mnSavbsMFtqYvdVYLrEriXYMm+16uSASNlw6AZhTzSeTZ cTAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Zr+OJOrLKA50IAOSFSprBbTZG7alMc1dzmiM9lXKIHA=; b=eA6kt7KI59k7/Jcb4urNIDAAwoMp40YAAFtWMvwF8ia1/v7z2lBzBV+tVhoOLO/MUA w5gYPIGbwSws3WwcVjTxuqsRMR34Y1fnXcEcacPMX0prrBZ8XdZR1SL1e05tXHtLkBpT Ngl6RET8gRhaUL4B5x1uRTXq1FRpz+ITH5Bn0Jl1Ilr/ETchYNcJyRzup8x5dB/8pJ6K q0ddNG78omT7TE7QYQqsGIcQWdb5pJ/dIOLrkM/CUgAZurRHZIBpon5zxCWREP4Y1O/R iZePpAd7X4BcPVJQ6WhHk0arxVHPhqbZTolXUKTKSzuK7x6lRffb8KQwShA5NKvDGM6o YNdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id mj21si920639ejb.271.2020.09.08.23.59.41; Tue, 08 Sep 2020 23:59:41 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbgIIG7j (ORCPT + 6 others); Wed, 9 Sep 2020 02:59:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55162 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725877AbgIIG7W (ORCPT ); Wed, 9 Sep 2020 02:59:22 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 467553311BEC91ED1E7B; Wed, 9 Sep 2020 14:59:17 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Wed, 9 Sep 2020 14:59:07 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v3 1/3] irqchip: dw-apb-ictl: prepare for support hierarchy irq domain Date: Wed, 9 Sep 2020 14:58:34 +0800 Message-ID: <20200909065836.2631-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200909065836.2631-1-thunder.leizhen@huawei.com> References: <20200909065836.2631-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename some functions and variables in advance, to make the next patch looks more clear. The details are as follows: 1. rename dw_apb_ictl_handler() to dw_apb_ictl_handle_irq_cascaded(). 2. change (1 << hwirq) to BIT(hwirq). In function dw_apb_ictl_init(): 1. rename local variable irq to parent_irq. 2. add "const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops", then replace &irq_generic_chip_ops in other places with domain_ops. No functional change. Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/irq-dw-apb-ictl.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.26.0.106.g9fadedd diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index e4550e9c810b..5458004242e9 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -26,7 +26,7 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 -static void dw_apb_ictl_handler(struct irq_desc *desc) +static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -43,7 +43,7 @@ static void dw_apb_ictl_handler(struct irq_desc *desc) u32 virq = irq_find_mapping(d, gc->irq_base + hwirq); generic_handle_irq(virq); - stat &= ~(1 << hwirq); + stat &= ~BIT(hwirq); } } @@ -73,12 +73,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, struct irq_domain *domain; struct irq_chip_generic *gc; void __iomem *iobase; - int ret, nrirqs, irq, i; + int ret, nrirqs, parent_irq, i; u32 reg; + const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; /* Map the parent interrupt for the chained handler */ - irq = irq_of_parse_and_map(np, 0); - if (irq <= 0) { + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { pr_err("%pOF: unable to parse irq\n", np); return -EINVAL; } @@ -120,8 +121,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, else nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); - domain = irq_domain_add_linear(np, nrirqs, - &irq_generic_chip_ops, NULL); + domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL); if (!domain) { pr_err("%pOF: unable to add irq domain\n", np); ret = -ENOMEM; @@ -146,7 +146,8 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain); + irq_set_chained_handler_and_data(parent_irq, + dw_apb_ictl_handle_irq_cascaded, domain); return 0; From patchwork Wed Sep 9 06:58:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249434 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp147524ilg; Tue, 8 Sep 2020 23:59:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw6kelMxwH0OXgtuKjO5i7AMaczht50lJher2qQ4ZtHO+r+EoSjSkLytGv8QRFkzFZJ/SXq X-Received: by 2002:a17:906:8690:: with SMTP id g16mr2190099ejx.187.1599634764340; Tue, 08 Sep 2020 23:59:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599634764; cv=none; d=google.com; s=arc-20160816; b=oFHpp02EDBEyN0aWELjCZVfpck3CHsluI7KQyGILK2nSn5HwJhnZ1Bc8AU1X8sOdKv sutLe7HGT/vZz8ItuKxpVs1QaDa0mnhqXT8Fg5HKN7dOOKD2zElvgCc98YQ/C5E7Ysu7 Wzi56SWcMqAULTkzFBaI4U/u4iU941bWfvFoQinfOutco2uTQxK3DbIGQ3hr86dRzww3 5WPJuY93BwXmqkuRn9wraAm1qESb1yNWTPDxIg7Y4lzIAB4IecF1sxbARDg9V1hIXjPW rokEPVl5v1YAZ7zml3zYSJlNCz/jjtGvDfLP2TxvwyUdBfx7+wu+HP8pP9Wa08DhWzxJ 7axw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=q5RJO64i60Lh0yW24euq4annCy7PoKEmM6ek8uXmqU4=; b=Dsx0yHUsL0ZQ5GRKL3cplqLOZQ1MWAKZ0bacXi/6YMVDGEis92Atq1AEWEjr48jSGS xDZ91bMEYc8ny+bNoqZe++7+63jYkk08tZhcq/QmxPMfUacWYX2C1VCXgeEUh+u1CJnj NSjgzZeqG7Pdme8tyfW34W7PVzdlrMpjz+9LfTJnRdM/1eDav1MS8Hke89UHaO1CAfYY F7YLsYeOKKTPk6JxHLhSUyZSn0kJJUGbRfKITXgmCfBXXYX8FNQz+Tdl8OIzUjjpu7ZI Ux6FAw1RfL5hDzdfqwxYtKC+1i4G2zx55PRebl9DB8RFjJaWc6J4aPJh3WbBWvE+kJiN l5Dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id mj21si920639ejb.271.2020.09.08.23.59.24; Tue, 08 Sep 2020 23:59:24 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725772AbgIIG7X (ORCPT + 6 others); Wed, 9 Sep 2020 02:59:23 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55158 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725864AbgIIG7W (ORCPT ); Wed, 9 Sep 2020 02:59:22 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 56372782562A495340CB; Wed, 9 Sep 2020 14:59:17 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Wed, 9 Sep 2020 14:59:08 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v3 2/3] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Wed, 9 Sep 2020 14:58:35 +0800 Message-ID: <20200909065836.2631-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200909065836.2631-1-thunder.leizhen@huawei.com> References: <20200909065836.2631-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 76 +++++++++++++++++++++++++++---- 2 files changed, 69 insertions(+), 9 deletions(-) -- 2.26.0.106.g9fadedd diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc..7c2d1c8fa551 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 5458004242e9..3c7bebe1b947 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include #include #include +#include #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,27 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* irq domain of the primary interrupt controller. */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~BIT(hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +72,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -75,13 +121,20 @@ static int __init dw_apb_ictl_init(struct device_node *np, void __iomem *iobase; int ret, nrirqs, parent_irq, i; u32 reg; - const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; - - /* Map the parent interrupt for the chained handler */ - parent_irq = irq_of_parse_and_map(np, 0); - if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + const struct irq_domain_ops *domain_ops; + + if (!parent || (np == parent)) { + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + } else { + /* Map the parent interrupt for the chained handler */ + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + domain_ops = &irq_generic_chip_ops; } ret = of_address_to_resource(np, 0, &r); @@ -144,10 +197,17 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; + if (!parent_irq) + gc->chip_types[0].chip.irq_eoi = irq_gc_noop; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0; From patchwork Wed Sep 9 06:58:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249433 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp147516ilg; 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[23.128.96.18]) by mx.google.com with ESMTP id mj21si920639ejb.271.2020.09.08.23.59.23; Tue, 08 Sep 2020 23:59:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725975AbgIIG7W (ORCPT + 6 others); Wed, 9 Sep 2020 02:59:22 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55164 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725772AbgIIG7V (ORCPT ); Wed, 9 Sep 2020 02:59:21 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4B77312699858D27CDD8; Wed, 9 Sep 2020 14:59:17 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Wed, 9 Sep 2020 14:59:08 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v3 3/3] dt-bindings: dw-apb-ictl: support hierarchy irq domain Date: Wed, 9 Sep 2020 14:58:36 +0800 Message-ID: <20200909065836.2631-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200909065836.2631-1-thunder.leizhen@huawei.com> References: <20200909065836.2631-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Signed-off-by: Zhen Lei --- .../interrupt-controller/snps,dw-apb-ictl.txt | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.26.0.106.g9fadedd diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt index 086ff08322db..2db59df9408f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt @@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl) Synopsys DesignWare provides interrupt controller IP for APB known as dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. +APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt +controller in some SoCs, e.g. Hisilicon SD5203. Required properties: - compatible: shall be "snps,dw-apb-ictl" @@ -10,6 +11,8 @@ Required properties: region starting with ENABLE_LOW register - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +Additional required property when it's used as secondary interrupt controller: - interrupts: interrupt reference to primary interrupt controller The interrupt sources map to the corresponding bits in the interrupt @@ -21,6 +24,7 @@ registers, i.e. - (optional) fast interrupts start at 64. Example: + /* dw_apb_ictl is used as secondary interrupt controller */ aic: interrupt-controller@3000 { compatible = "snps,dw-apb-ictl"; reg = <0x3000 0xc00>; @@ -29,3 +33,11 @@ Example: interrupt-parent = <&gic>; interrupts = ; }; + + /* dw_apb_ictl is used as primary interrupt controller */ + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + };